235 lines
6.6 KiB
C
235 lines
6.6 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#ifndef CFG_RAMBOOT
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static void sdram_start (int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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#ifdef CONFIG_MPC5200_DDR
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f00 | hi_addr_bit;
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
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/* set mode register: extended mode */
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*(vu_long *)MPC5XXX_SDRAM_MODE = 0x40090000;
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/* set mode register: reset DLL */
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*(vu_long *)MPC5XXX_SDRAM_MODE = 0x058d0000;
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f02 | hi_addr_bit;
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xf05f0f04 | hi_addr_bit;
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/* set mode register */
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*(vu_long *)MPC5XXX_SDRAM_MODE = 0x018d0000;
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/* normal operation */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x705f0f00 | hi_addr_bit;
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#else
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
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/* set mode register */
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#if defined(CONFIG_MPC5200)
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*(vu_long *)MPC5XXX_SDRAM_MODE = 0x00cd0000;
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#elif defined(CONFIG_MGT5100)
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*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
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#endif
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
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/* set mode register */
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*(vu_long *)MPC5XXX_SDRAM_MODE = 0x00cd0000;
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/* normal operation */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
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#endif
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}
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#endif
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long int initdram (int board_type)
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{
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ulong dramsize = 0;
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#ifdef CONFIG_MPC5200_DDR
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ulong dramsize2 = 0;
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#endif
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#ifndef CFG_RAMBOOT
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ulong test1, test2;
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/* configure SDRAM start/end */
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#if defined(CONFIG_MPC5200)
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
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#ifdef CONFIG_MPC5200_DDR
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0x73722930;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x47770000;
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/* set tap delay to 0x10 */
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*(vu_long *)MPC5XXX_CDM_PORCFG = 0x10000000;
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#else
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xd2322800;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x8ad70000;
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#endif
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#elif defined(CONFIG_MGT5100)
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*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
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*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
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*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
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/* address select register */
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*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
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#endif
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sdram_start(0);
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test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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#if defined(CONFIG_MPC5200)
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG =
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(0x13 + __builtin_ffs(dramsize >> 20) - 1);
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#ifdef CONFIG_MPC5200_DDR
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
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sdram_start(0);
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test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize2 = test1;
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} else {
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dramsize2 = test2;
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}
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG =
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dramsize + (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
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#else
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
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#endif
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#elif defined(CONFIG_MGT5100)
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*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
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#endif
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#else /* CFG_RAMBOOT */
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#ifdef CONFIG_MGT5100
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*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
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dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
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#else
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dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
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#ifdef CONFIG_MPC5200_DDR
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dramsize2 = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS1CFG - 0x13)) << 20);
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#endif
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#endif
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#endif /* CFG_RAMBOOT */
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#ifdef CONFIG_MPC5200_DDR
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dramsize += dramsize2;
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#endif
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/* return total ram size */
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return dramsize;
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}
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int checkboard (void)
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{
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#if defined(CONFIG_MPC5200)
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puts ("Board: Motorola MPC5200 (IceCube)\n");
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#elif defined(CONFIG_MGT5100)
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puts ("Board: Motorola MGT5100 (IceCube)\n");
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#endif
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return 0;
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}
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void flash_preinit(void)
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{
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/*
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* Now, when we are in RAM, enable flash write
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* access for detection process.
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* Note that CS_BOOT cannot be cleared when
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* executing in flash.
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*/
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#if defined(CONFIG_MGT5100)
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*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
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*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
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#endif
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*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
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}
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void flash_afterinit(ulong size)
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{
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if (size == 0x800000) { /* adjust mapping */
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*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
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START_REG(CFG_BOOTCS_START | size);
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*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
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STOP_REG(CFG_BOOTCS_START | size, size);
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}
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}
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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extern void pci_mpc5xxx_init(struct pci_controller *);
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void pci_init_board(void)
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{
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pci_mpc5xxx_init(&hose);
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}
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#endif
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#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
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#define GPIO_PSC1_4 0x01000000UL
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void init_ide_reset (void)
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{
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debug ("init_ide_reset\n");
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/* Configure PSC1_4 as GPIO output for ATA reset */
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
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}
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void ide_set_reset (int idereset)
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{
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debug ("ide_reset(%d)\n", idereset);
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if (idereset) {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
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} else {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
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}
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}
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#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
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