193 lines
6.0 KiB
C
193 lines
6.0 KiB
C
/*
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* MCF5282 Internal Memory Map
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*
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* Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __IMMAP_5282__
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#define __IMMAP_5282__
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#define MMAP_SCM (CFG_MBAR + 0x00000000)
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#define MMAP_SDRAMC (CFG_MBAR + 0x00000040)
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#define MMAP_FBCS (CFG_MBAR + 0x00000080)
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#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
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#define MMAP_DMA1 (CFG_MBAR + 0x00000140)
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#define MMAP_DMA2 (CFG_MBAR + 0x00000180)
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#define MMAP_DMA3 (CFG_MBAR + 0x000001C0)
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#define MMAP_UART0 (CFG_MBAR + 0x00000200)
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#define MMAP_UART1 (CFG_MBAR + 0x00000240)
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#define MMAP_UART2 (CFG_MBAR + 0x00000280)
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#define MMAP_I2C (CFG_MBAR + 0x00000300)
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#define MMAP_QSPI (CFG_MBAR + 0x00000340)
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#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
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#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
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#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
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#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
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#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
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#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
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#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
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#define MMAP_FEC (CFG_MBAR + 0x00001000)
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#define MMAP_FECFIFO (CFG_MBAR + 0x00001400)
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#define MMAP_GPIO (CFG_MBAR + 0x00100000)
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#define MMAP_CCM (CFG_MBAR + 0x00110000)
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#define MMAP_PLL (CFG_MBAR + 0x00120000)
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#define MMAP_EPORT (CFG_MBAR + 0x00130000)
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#define MMAP_WDOG (CFG_MBAR + 0x00140000)
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#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
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#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
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#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
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#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
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#define MMAP_QADC (CFG_MBAR + 0x00190000)
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#define MMAP_GPTMRA (CFG_MBAR + 0x001A0000)
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#define MMAP_GPTMRB (CFG_MBAR + 0x001B0000)
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#define MMAP_CAN (CFG_MBAR + 0x001C0000)
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#define MMAP_CFMC (CFG_MBAR + 0x001D0000)
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#define MMAP_CFMMEM (CFG_MBAR + 0x04000000)
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/* System Control Module */
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typedef struct scm_ctrl {
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u32 ipsbar;
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u32 res1;
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u32 rambar;
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u32 res2;
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u8 crsr;
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u8 cwcr;
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u8 lpicr;
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u8 cwsr;
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u32 res3;
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u8 mpark;
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u8 res4[3];
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u8 pacr0;
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u8 pacr1;
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u8 pacr2;
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u8 pacr3;
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u8 pacr4;
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u8 res5;
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u8 pacr5;
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u8 pacr6;
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u8 pacr7;
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u8 res6;
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u8 pacr8;
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u8 res7;
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u8 gpacr0;
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u8 gpacr1;
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u16 res8;
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} scm_t;
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/* Flexbus module Chip select registers */
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typedef struct fbcs_ctrl {
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u16 csar0; /* 0x00 Chip-Select Address Register 0 */
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u16 res0;
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u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
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u16 res1; /* 0x08 */
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u16 cscr0; /* 0x0A Chip-Select Control Register 0 */
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u16 csar1; /* 0x0C Chip-Select Address Register 1 */
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u16 res2;
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u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
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u16 res3; /* 0x14 */
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u16 cscr1; /* 0x16 Chip-Select Control Register 1 */
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u16 csar2; /* 0x18 Chip-Select Address Register 2 */
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u16 res4;
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u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
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u16 res5; /* 0x20 */
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u16 cscr2; /* 0x22 Chip-Select Control Register 2 */
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u16 csar3; /* 0x24 Chip-Select Address Register 3 */
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u16 res6;
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u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
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u16 res7; /* 0x2C */
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u16 cscr3; /* 0x2E Chip-Select Control Register 3 */
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u16 csar4; /* 0x30 Chip-Select Address Register 4 */
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u16 res8;
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u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
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u16 res9; /* 0x38 */
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u16 cscr4; /* 0x3A Chip-Select Control Register 4 */
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u16 csar5; /* 0x3C Chip-Select Address Register 5 */
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u16 res10;
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u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
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u16 res11; /* 0x44 */
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u16 cscr5; /* 0x46 Chip-Select Control Register 5 */
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u16 csar6; /* 0x48 Chip-Select Address Register 5 */
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u16 res12;
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u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */
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u16 res13; /* 0x50 */
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u16 cscr6; /* 0x52 Chip-Select Control Register 5 */
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u16 csar7; /* 0x54 Chip-Select Address Register 5 */
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u16 res14;
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u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */
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u16 res15; /* 0x5C */
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u16 cscr7; /* 0x5E Chip-Select Control Register 5 */
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} fbcs_t;
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/* Interrupt module registers */
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typedef struct int0_ctrl {
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/* Interrupt Controller 0 */
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u32 iprh0; /* 0x00 Pending Register High */
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u32 iprl0; /* 0x04 Pending Register Low */
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u32 imrh0; /* 0x08 Mask Register High */
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u32 imrl0; /* 0x0C Mask Register Low */
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u32 frch0; /* 0x10 Force Register High */
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u32 frcl0; /* 0x14 Force Register Low */
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u8 irlr; /* 0x18 */
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u8 iacklpr; /* 0x19 */
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u16 res1[19]; /* 0x1a - 0x3c */
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u8 icr0[64]; /* 0x40 - 0x7F Control registers */
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u32 res3[24]; /* 0x80 - 0xDF */
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u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
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u8 res4[3]; /* 0xE1 - 0xE3 */
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u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
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u8 res5[3]; /* 0xE5 - 0xE7 */
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u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
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u8 res6[3]; /* 0xE9 - 0xEB */
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u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
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u8 res7[3]; /* 0xED - 0xEF */
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u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
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u8 res8[3]; /* 0xF1 - 0xF3 */
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u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
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u8 res9[3]; /* 0xF5 - 0xF7 */
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u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
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u8 resa[3]; /* 0xF9 - 0xFB */
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u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
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u8 resb[3]; /* 0xFD - 0xFF */
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} int0_t;
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/* Clock Module registers */
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typedef struct pll_ctrl {
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u16 syncr; /* 0x00 synthesizer control register */
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u16 synsr; /* 0x02 synthesizer status register */
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} pll_t;
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/* Watchdog registers */
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typedef struct wdog_ctrl {
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ushort wcr;
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ushort wmr;
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ushort wcntr;
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ushort wsr;
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} wdog_t;
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#endif /* __IMMAP_5282__ */
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