309 lines
8.7 KiB
C
309 lines
8.7 KiB
C
/*
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <i2c.h>
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#include <spd.h>
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#include <asm/mmu.h>
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#ifdef CONFIG_SPD_EEPROM
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#undef DEBUG
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#if defined(DEBUG)
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#define DEB(x) x
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#else
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#define DEB(x)
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#endif
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#define ns2clk(ns) ((ns) / (2000000000 /get_bus_freq(0) + 1))
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long int spd_sdram(void) {
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_ddr_t *ddr = &immap->im_ddr;
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volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
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spd_eeprom_t spd;
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unsigned int memsize,tmp,tmp1,tmp2;
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unsigned char caslat;
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i2c_read (SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
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if ( spd.nrows > 2 ) {
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printf("DDR:Only two chip selects are supported on ADS.\n");
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return 0;
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}
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if ( spd.nrow_addr < 12 || spd.nrow_addr > 14 || spd.ncol_addr < 8 || spd.ncol_addr > 11) {
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printf("DDR:Row or Col number unsupported.\n");
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return 0;
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}
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ddr->cs0_bnds = ((spd.row_dens>>2) - 1);
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ddr->cs0_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
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DEB(printf("\n"));
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DEB(printf("cs0_bnds = 0x%08x\n",ddr->cs0_bnds));
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DEB(printf("cs0_config = 0x%08x\n",ddr->cs0_config));
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if ( spd.nrows == 2 ) {
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ddr->cs1_bnds = ((spd.row_dens<<14) | ((spd.row_dens>>1) - 1));
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ddr->cs1_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
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DEB(printf("cs1_bnds = 0x%08x\n",ddr->cs1_bnds));
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DEB(printf("cs1_config = 0x%08x\n",ddr->cs1_config));
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}
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memsize = spd.nrows * (4 * spd.row_dens);
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if( spd.mem_type == 0x07 ) {
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printf("DDR module detected, total size:%dMB.\n",memsize);
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} else {
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printf("No DDR module found!\n");
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return 0;
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}
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switch(memsize) {
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case 16:
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tmp = 7; /* TLB size */
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tmp1 = 1; /* TLB entry number */
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tmp2 = 23; /* Local Access Window size */
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break;
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case 32:
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tmp = 7;
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tmp1 = 2;
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tmp2 = 24;
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break;
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case 64:
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tmp = 8;
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tmp1 = 1;
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tmp2 = 25;
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break;
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case 128:
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tmp = 8;
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tmp1 = 2;
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tmp2 = 26;
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break;
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case 256:
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tmp = 9;
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tmp1 = 1;
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tmp2 = 27;
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break;
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case 512:
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tmp = 9;
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tmp1 = 2;
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tmp2 = 28;
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break;
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case 1024:
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tmp = 10;
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tmp1 = 1;
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tmp2 = 29;
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break;
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default:
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printf("DDR:we only added support 16M,32M,64M,128M,256M,512M and 1G DDR I.\n");
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return 0;
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break;
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}
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/* configure DDR TLB to TLB1 Entry 4,5 */
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mtspr(MAS0, TLB1_MAS0(1,4,0));
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mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
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mtspr(MAS2, TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0));
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mtspr(MAS3, TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
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asm volatile("isync;msync;tlbwe;isync");
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DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,4,0)));
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DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
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DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) \
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& 0xfffff),0,0,0,0,0,0,0,0)));
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DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) \
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& 0xfffff),0,0,0,0,0,1,0,1,0,1)));
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if(tmp1 == 2) {
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mtspr(MAS0, TLB1_MAS0(1,5,0));
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mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
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mtspr(MAS2, TLB1_MAS2((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
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& 0xfffff),0,0,0,0,0,0,0,0));
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mtspr(MAS3, TLB1_MAS3((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
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& 0xfffff),0,0,0,0,0,1,0,1,0,1));
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asm volatile("isync;msync;tlbwe;isync");
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DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,5,0)));
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DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
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DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2((((CFG_DDR_SDRAM_BASE \
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+(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,0,0,0)));
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DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3((((CFG_DDR_SDRAM_BASE \
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+(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)));
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}
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#if defined(CONFIG_RAM_AS_FLASH)
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ecm->lawbar2 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
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ecm->lawar2 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
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DEB(printf("DDR:LAWBAR2=0x%08x\n",ecm->lawbar2));
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DEB(printf("DDR:LARAR2=0x%08x\n",ecm->lawar2));
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#else
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ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
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ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
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DEB(printf("DDR:LAWBAR1=0x%08x\n",ecm->lawbar1));
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DEB(printf("DDR:LARAR1=0x%08x\n",ecm->lawar1));
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#endif
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tmp = 20000/(((spd.clk_cycle & 0xF0) >> 4) * 10 + (spd.clk_cycle & 0x0f));
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DEB(printf("DDR:Module maximum data rate is: %dMhz\n",tmp));
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/* find the largest CAS */
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if(spd.cas_lat & 0x40) {
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caslat = 7;
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} else if (spd.cas_lat & 0x20) {
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caslat = 6;
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} else if (spd.cas_lat & 0x10) {
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caslat = 5;
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} else if (spd.cas_lat & 0x08) {
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caslat = 4;
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} else if (spd.cas_lat & 0x04) {
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caslat = 3;
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} else if (spd.cas_lat & 0x02) {
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caslat = 2;
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} else if (spd.cas_lat & 0x01) {
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caslat = 1;
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} else {
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printf("DDR:no valid CAS Latency information.\n");
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return 0;
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}
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tmp1 = get_bus_freq(0)/1000000;
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if(tmp1<230 && tmp1>=90 && tmp>=230) { /* 90~230 range, treated as DDR 200 */
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if(spd.clk_cycle3 == 0xa0) caslat -= 2;
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else if(spd.clk_cycle2 == 0xa0) caslat--;
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} else if(tmp1<280 && tmp1>=230 && tmp>=280) { /* 230-280 range, treated as DDR 266 */
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if(spd.clk_cycle3 == 0x75) caslat -= 2;
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else if(spd.clk_cycle2 == 0x75) caslat--;
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} else if(tmp1<350 && tmp1>=280 && tmp>=350) { /* 280~350 range, treated as DDR 333 */
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if(spd.clk_cycle3 == 0x60) caslat -= 2;
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else if(spd.clk_cycle2 == 0x60) caslat--;
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} else if(tmp1<90 || tmp1 >=350) { /* DDR rate out-of-range */
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printf("DDR:platform frequency is not fit for DDR rate\n");
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return 0;
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}
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/* note: caslat must also be programmed into ddr->sdram_mode register */
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/* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,use conservative value here */
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#if 1
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ddr->timing_cfg_1 = (((ns2clk(spd.trp/4) & 0x07) << 28 ) | \
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((ns2clk(spd.tras) & 0x0f ) << 24 ) | \
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((ns2clk(spd.trcd/4) & 0x07) << 20 ) | \
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((caslat & 0x07)<< 16 ) | \
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(((ns2clk(spd.sset[6]) - 8) & 0x0f) << 12 ) | \
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( 0x300 ) | \
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((ns2clk(spd.trrd/4) & 0x07) << 4) | 1);
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#else
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ddr->timing_cfg_1 = 0x37344321;
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caslat = 4;
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#endif
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DEB(printf("DDR:timing_cfg_1=0x%08x\n",ddr->timing_cfg_1));
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/* note: hand-coded value for timing_cfg_2, see Errata DDR1*/
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#if defined(CONFIG_MPC85xx_REV1)
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ddr->timing_cfg_2 = 0x00000800;
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#endif
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DEB(printf("DDR:timing_cfg_2=0x%08x\n",ddr->timing_cfg_2));
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/* only DDR I is supported, DDR I and II have different mode-register-set definition */
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/* burst length is always 4 */
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switch(caslat) {
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case 2:
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ddr->sdram_mode = 0x52; /* 1.5 */
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break;
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case 3:
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ddr->sdram_mode = 0x22; /* 2.0 */
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break;
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case 4:
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ddr->sdram_mode = 0x62; /* 2.5 */
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break;
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case 5:
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ddr->sdram_mode = 0x32; /* 3.0 */
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break;
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default:
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printf("DDR:only CAS Latency 1.5,2.0,2.5,3.0 is supported.\n");
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return 0;
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}
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DEB(printf("DDR:sdram_mode=0x%08x\n",ddr->sdram_mode));
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switch(spd.refresh) {
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case 0x00:
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case 0x80:
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tmp = ns2clk(15625);
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break;
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case 0x01:
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case 0x81:
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tmp = ns2clk(3900);
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break;
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case 0x02:
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case 0x82:
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tmp = ns2clk(7800);
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break;
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case 0x03:
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case 0x83:
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tmp = ns2clk(31300);
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break;
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case 0x04:
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case 0x84:
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tmp = ns2clk(62500);
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break;
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case 0x05:
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case 0x85:
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tmp = ns2clk(125000);
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break;
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default:
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tmp = 0x512;
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break;
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}
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/* set BSTOPRE to 0x100 for page mode, if auto-charge is used, set BSTOPRE = 0 */
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ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
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DEB(printf("DDR:sdram_interval=0x%08x\n",ddr->sdram_interval));
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/* is this an ECC DDR chip? */
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#if defined(CONFIG_DDR_ECC)
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if(spd.config == 0x02) {
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ddr->err_disable = 0x0000000d;
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ddr->err_sbe = 0x00ff0000;
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}
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DEB(printf("DDR:err_disable=0x%08x\n",ddr->err_disable));
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DEB(printf("DDR:err_sbe=0x%08x\n",ddr->err_sbe));
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#endif
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asm("sync;isync;msync");
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udelay(500);
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/* registered or unbuffered? */
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#if defined(CONFIG_DDR_ECC)
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ddr->sdram_cfg = (spd.config == 0x02)?0x20000000:0x0;
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#endif
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ddr->sdram_cfg = 0xc2000000|((spd.mod_attr == 0x20) ? 0x0 : \
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((spd.mod_attr == 0x26) ? 0x10000000:0x0));
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asm("sync;isync;msync");
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udelay(500);
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DEB(printf("DDR:sdram_cfg=0x%08x\n",ddr->sdram_cfg));
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return (memsize*1024*1024);
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}
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#endif /* CONFIG_SPD_EEPROM */
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