155 lines
4.0 KiB
ArmAsm
155 lines
4.0 KiB
ArmAsm
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Based on code provided from UDTech and AMCC
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#define mtsdram_as(reg, value) \
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addi r4,0,reg ; \
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mtdcr memcfga,r4 ; \
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addis r4,0,value@h ; \
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ori r4,r4,value@l ; \
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mtdcr memcfgd,r4 ;
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.globl ext_bus_cntlr_init
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ext_bus_cntlr_init:
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
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/*
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* DDR2 setup
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*/
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/* Following the DDR Core Manual, here is the initialization */
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/* Step 1 */
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/* Step 2 */
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/* Step 3 */
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/* base=00000000, size=256MByte (6), mode=7 (n*10*8) */
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mtsdram_as(SDRAM_MB0CF, 0x00006701);
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/* SET SDRAM_MB1CF - Not enabled */
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mtsdram_as(SDRAM_MB1CF, 0x00000000);
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/* SET SDRAM_MB2CF - Not enabled */
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mtsdram_as(SDRAM_MB2CF, 0x00000000);
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/* SET SDRAM_MB3CF - Not enabled */
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mtsdram_as(SDRAM_MB3CF, 0x00000000);
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/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
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mtsdram_as(SDRAM_CLKTR, 0x80000000);
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/* Refresh Time register (0x30) Refresh every 7.8125uS */
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mtsdram_as(SDRAM_RTR, 0x06180000);
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/* SDRAM_SDTR1 */
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mtsdram_as(SDRAM_SDTR1, 0x80201000);
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/* SDRAM_SDTR2 */
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mtsdram_as(SDRAM_SDTR2, 0x32204232);
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/* SDRAM_SDTR3 */
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mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
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mtsdram_as(SDRAM_MMODE, 0x00000442);
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mtsdram_as(SDRAM_MEMODE, 0x00000404);
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/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
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mtsdram_as(SDRAM_MCOPT1, 0x04322000);
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/* NOP */
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mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
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/* precharge 3 DDR clock cycle */
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mtsdram_as(SDRAM_INITPLR1, 0x81900400);
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/* EMR2 twr = 2tck */
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mtsdram_as(SDRAM_INITPLR2, 0x81020000);
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/* EMR3 twr = 2tck */
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mtsdram_as(SDRAM_INITPLR3, 0x81030000);
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/* EMR DLL ENABLE twr = 2tck */
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mtsdram_as(SDRAM_INITPLR4, 0x81010404);
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/* MR w/ DLL reset
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* Note: 5 is CL. May need to be changed
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*/
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mtsdram_as(SDRAM_INITPLR5, 0x81000542);
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/* precharge 3 DDR clock cycle */
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mtsdram_as(SDRAM_INITPLR6, 0x81900400);
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/* Auto-refresh trfc = 26tck */
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mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
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/* Auto-refresh trfc = 26tck */
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mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
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/* Auto-refresh */
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mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
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/* Auto-refresh */
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mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
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/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
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mtsdram_as(SDRAM_INITPLR11, 0x81000442);
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mtsdram_as(SDRAM_INITPLR12, 0x81010780);
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mtsdram_as(SDRAM_INITPLR13, 0x81010400);
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mtsdram_as(SDRAM_INITPLR14, 0x00000000);
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mtsdram_as(SDRAM_INITPLR15, 0x00000000);
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/* SET MCIF0_CODT Die Termination On */
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mtsdram_as(SDRAM_CODT, 0x0080f837);
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mtsdram_as(SDRAM_MODT0, 0x01800000);
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mtsdram_as(SDRAM_MODT1, 0x00000000);
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mtsdram_as(SDRAM_WRDTR, 0x00000000);
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/* SDRAM0_MCOPT2 (0X21) Start initialization */
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mtsdram_as(SDRAM_MCOPT2, 0x20000000);
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/* Step 5 */
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lis r3,0x1 /* 400000 = wait 100ms */
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mtctr r3
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pll_wait:
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bdnz pll_wait
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/* Step 6 */
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/* SDRAM_DLCR */
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mtsdram_as(SDRAM_DLCR, 0x030000a5);
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/* SDRAM_RDCC */
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mtsdram_as(SDRAM_RDCC, 0x40000000);
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/* SDRAM_RQDC */
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mtsdram_as(SDRAM_RQDC, 0x80000038);
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/* SDRAM_RFDC */
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mtsdram_as(SDRAM_RFDC, 0x00000209);
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/* Enable memory controller */
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mtsdram_as(SDRAM_MCOPT2, 0x28000000);
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#endif /* #ifndef CONFIG_NAND_U_BOOT */
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blr
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