129 lines
3.6 KiB
C
129 lines
3.6 KiB
C
/*
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* Copyright 2008-2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address)
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{
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i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
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}
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unsigned int fsl_ddr_get_mem_data_rate(void)
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{
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return get_ddr_freq(0);
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}
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void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
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unsigned int ctrl_num)
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{
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unsigned int i;
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unsigned int i2c_address = 0;
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
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if (ctrl_num == 0 && i == 0)
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i2c_address = SPD_EEPROM_ADDRESS1;
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get_spd(&(ctrl_dimms_spd[i]), i2c_address);
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}
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}
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typedef struct {
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u32 datarate_mhz_low;
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u32 datarate_mhz_high;
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u32 n_ranks;
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u32 clk_adjust;
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u32 cpo;
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u32 write_data_delay;
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u32 force_2T;
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} board_specific_parameters_t;
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/* ranges for parameters:
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* wr_data_delay = 0-6
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* clk adjust = 0-8
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* cpo 2-0x1E (30)
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*/
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const board_specific_parameters_t board_specific_parameters[][20] = {
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{
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/* memory controller 0 */
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/* lo| hi| num| clk| cpo|wrdata|2T */
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/* mhz| mhz|ranks|adjst| | delay| */
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#ifdef CONFIG_FSL_DDR2
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{ 0, 333, 2, 4, 0x1f, 2, 0},
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{334, 400, 2, 4, 0x1f, 2, 0},
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{401, 549, 2, 4, 0x1f, 2, 0},
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{550, 680, 2, 4, 0x1f, 3, 0},
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{681, 850, 2, 4, 0x1f, 4, 0},
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{ 0, 333, 1, 4, 0x1f, 2, 0},
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{334, 400, 1, 4, 0x1f, 2, 0},
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{401, 549, 1, 4, 0x1f, 2, 0},
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{550, 680, 1, 4, 0x1f, 3, 0},
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{681, 850, 1, 4, 0x1f, 4, 0}
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#else
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{ 0, 850, 2, 4, 0x1f, 4, 0},
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{ 0, 850, 1, 4, 0x1f, 4, 0}
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#endif
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},
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const board_specific_parameters_t *pbsp =
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&(board_specific_parameters[ctrl_num][0]);
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u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
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sizeof(board_specific_parameters[0][0]);
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u32 i;
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ulong ddr_freq;
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/* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
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* that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
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* there are two dimms in the controller, set odt_rd_cfg to 3 and
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* odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
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*/
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 1;
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}
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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for (i = 0; i < num_params; i++) {
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if (ddr_freq >= pbsp->datarate_mhz_low &&
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ddr_freq <= pbsp->datarate_mhz_high &&
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pdimm->n_ranks == pbsp->n_ranks) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay = pbsp->write_data_delay;
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popts->twoT_en = pbsp->force_2T;
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}
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pbsp++;
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}
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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popts->wrlvl_en = 1;
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/* Write leveling override */
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xa;
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popts->wrlvl_start = 0x7;
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/* Rtt and Rtt_WR override */
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popts->rtt_override = 1;
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popts->rtt_override_value = DDR3_RTT_120_OHM;
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popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
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}
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