143 lines
4.6 KiB
C
143 lines
4.6 KiB
C
/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_MX31_REGS_H
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#define __ASM_ARCH_MX31_REGS_H
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#define __REG(x) (*((volatile u32 *)(x)))
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#define __REG16(x) (*((volatile u16 *)(x)))
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#define __REG8(x) (*((volatile u8 *)(x)))
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#define CCM_BASE 0x53f80000
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#define CCM_CCMR (CCM_BASE + 0x00)
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#define CCM_PDR0 (CCM_BASE + 0x04)
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#define CCM_PDR1 (CCM_BASE + 0x08)
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#define CCM_RCSR (CCM_BASE + 0x0c)
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#define CCM_MPCTL (CCM_BASE + 0x10)
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#define CCM_UPCTL (CCM_BASE + 0x10)
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#define CCM_SPCTL (CCM_BASE + 0x18)
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#define CCM_COSR (CCM_BASE + 0x1C)
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#define CCM_CGR0 (CCM_BASE + 0x20)
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#define CCM_CGR1 (CCM_BASE + 0x24)
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#define CCM_CGR2 (CCM_BASE + 0x28)
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#define CCMR_MDS (1 << 7)
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#define CCMR_SBYCS (1 << 4)
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#define CCMR_MPE (1 << 3)
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#define CCMR_PRCS_MASK (3 << 1)
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#define CCMR_FPM (1 << 1)
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#define CCMR_CKIH (2 << 1)
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#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
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#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
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#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
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#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
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#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
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#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
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#define PDR0_MCU_PODF(x) ((x) & 0x7)
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#define PLL_PD(x) (((x) & 0xf) << 26)
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#define PLL_MFD(x) (((x) & 0x3ff) << 16)
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#define PLL_MFI(x) (((x) & 0xf) << 10)
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#define PLL_MFN(x) (((x) & 0x3ff) << 0)
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#define WEIM_BASE 0xb8002000
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#define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
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#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
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#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
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#define IOMUXC_BASE 0x43FAC000
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#define IOMUXC_GPR (IOMUXC_BASE + 0x8)
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#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
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#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
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#define IPU_BASE 0x53fc0000
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#define IPU_CONF IPU_BASE
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#define IPU_CONF_PXL_ENDIAN (1<<8)
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#define IPU_CONF_DU_EN (1<<7)
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#define IPU_CONF_DI_EN (1<<6)
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#define IPU_CONF_ADC_EN (1<<5)
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#define IPU_CONF_SDC_EN (1<<4)
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#define IPU_CONF_PF_EN (1<<3)
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#define IPU_CONF_ROT_EN (1<<2)
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#define IPU_CONF_IC_EN (1<<1)
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#define IPU_CONF_SCI_EN (1<<0)
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#define WDOG_BASE 0x53FDC000
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/*
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* Signal Multiplexing (IOMUX)
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*/
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/* bits in the SW_MUX_CTL registers */
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#define MUX_CTL_OUT_GPIO_DR (0 << 4)
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#define MUX_CTL_OUT_FUNC (1 << 4)
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#define MUX_CTL_OUT_ALT1 (2 << 4)
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#define MUX_CTL_OUT_ALT2 (3 << 4)
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#define MUX_CTL_OUT_ALT3 (4 << 4)
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#define MUX_CTL_OUT_ALT4 (5 << 4)
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#define MUX_CTL_OUT_ALT5 (6 << 4)
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#define MUX_CTL_OUT_ALT6 (7 << 4)
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#define MUX_CTL_IN_NONE (0 << 0)
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#define MUX_CTL_IN_GPIO (1 << 0)
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#define MUX_CTL_IN_FUNC (2 << 0)
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#define MUX_CTL_IN_ALT1 (4 << 0)
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#define MUX_CTL_IN_ALT2 (8 << 0)
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#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
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#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
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#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
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#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
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/* Register offsets based on IOMUXC_BASE */
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/* 0x00 .. 0x7b */
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#define MUX_CTL_RTS1 0x7c
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#define MUX_CTL_CTS1 0x7d
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#define MUX_CTL_DTR_DCE1 0x7e
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#define MUX_CTL_DSR_DCE1 0x7f
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#define MUX_CTL_CSPI2_SCLK 0x80
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#define MUX_CTL_CSPI2_SPI_RDY 0x81
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#define MUX_CTL_RXD1 0x82
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#define MUX_CTL_TXD1 0x83
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#define MUX_CTL_CSPI2_MISO 0x84
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#define MUX_CTL_CSPI2_SS0 0x85
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#define MUX_CTL_CSPI2_SS1 0x86
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#define MUX_CTL_CSPI2_SS2 0x87
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#define MUX_CTL_CSPI2_MOSI 0x8b
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/* The modes a specific pin can be in
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* these macros can be used in mx31_gpio_mux() and have the form
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* MUX_[contact name]__[pin function]
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*/
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#define MUX_RXD1__UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1)
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#define MUX_TXD1__UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1)
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#define MUX_RTS1__UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1)
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#define MUX_RTS1__UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
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#define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
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#define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
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#endif /* __ASM_ARCH_MX31_REGS_H */
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