429 lines
17 KiB
C
429 lines
17 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <ppc405.h>
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#include <libfdt.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#if defined(CONFIG_PCI)
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#include <pci.h>
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#include <asm/4xx_pcie.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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void fpga_init(void)
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{
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/*
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* Set FPGA regs
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*/
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out32(CFG_FPGA_BASE, 0xff570cc0);
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}
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/*
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* Board early initialization function
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*/
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int board_early_init_f (void)
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{
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u32 val;
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/*--------------------------------------------------------------------+
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| Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
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+--------------------------------------------------------------------+
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+---------------------------------------------------------------------+
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|Interrupt| Source | Pol. | Sensi.| Crit. |
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+---------+-----------------------------------+-------+-------+-------+
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| IRQ 00 | UART0 | High | Level | Non |
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| IRQ 01 | UART1 | High | Level | Non |
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| IRQ 02 | IIC0 | High | Level | Non |
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| IRQ 03 | TBD | High | Level | Non |
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| IRQ 04 | TBD | High | Level | Non |
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| IRQ 05 | EBM | High | Level | Non |
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| IRQ 06 | BGI | High | Level | Non |
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| IRQ 07 | IIC1 | Rising| Edge | Non |
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| IRQ 08 | SPI | High | Lvl/ed| Non |
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| IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
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| IRQ 10 | MAL TX EOB | High | Level | Non |
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| IRQ 11 | MAL RX EOB | High | Level | Non |
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| IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
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| IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
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| IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
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| IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
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| IRQ 16 | PCIE0 AL | high | Level | Non |
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| IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
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| IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
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| IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
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| IRQ 20 | PCIE0 TCR | High | Level | Non |
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| IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
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| IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
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| IRQ 23 | Security EIP-94 | High | Level | Non |
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| IRQ 24 | EMAC0 interrupt | High | Level | Non |
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| IRQ 25 | EMAC1 interrupt | High | Level | Non |
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| IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
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| IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
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| IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
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| IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
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| IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
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| IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
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|----------------------------------------------------------------------
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| IRQ 32 | MAL Serr | High | Level | Non |
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| IRQ 33 | MAL Txde | High | Level | Non |
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| IRQ 34 | MAL Rxde | High | Level | Non |
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| IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
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| IRQ 36 | PCIE0 DCR Error | High | Level | Non |
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| IRQ 37 | EBC | High |Lvl Edg| Non |
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| IRQ 38 | NDFC | High | Level | Non |
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| IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
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| IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
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| IRQ 41 | PCIE1 AL | high | Level | Non |
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| IRQ 42 | PCIE1 VPD access | rising| edge | Non |
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| IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
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| IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
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| IRQ 45 | PCIE1 TCR | High | Level | Non |
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| IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
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| IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
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| IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
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| IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
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| IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
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| IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
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| IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
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| IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
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| IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
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| IRQ 55 | Serial ROM | High | Level | Non |
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| IRQ 56 | GPT Decrement Pulse | High | Level | Non |
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| IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
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| IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
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| IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
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| IRQ 60 | EMAC0 Wake-up | High | Level | Non |
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| IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
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| IRQ 62 | EMAC1 Wake-up | High | Level | Non |
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|----------------------------------------------------------------------
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| IRQ 64 | PE0 AL | High | Level | Non |
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| IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
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| IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
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| IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
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| IRQ 68 | PE0 TCR | High | Level | Non |
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| IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
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| IRQ 70 | PE0 DCR Error | High | Level | Non |
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| IRQ 71 | Reserved | N/A | N/A | Non |
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| IRQ 72 | PE1 AL | High | Level | Non |
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| IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
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| IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
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| IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
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| IRQ 76 | PE1 TCR | High | Level | Non |
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| IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
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| IRQ 78 | PE1 DCR Error | High | Level | Non |
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| IRQ 79 | Reserved | N/A | N/A | Non |
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| IRQ 80 | PE2 AL | High | Level | Non |
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| IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
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| IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
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| IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
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| IRQ 84 | PE2 TCR | High | Level | Non |
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| IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
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| IRQ 86 | PE2 DCR Error | High | Level | Non |
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| IRQ 87 | Reserved | N/A | N/A | Non |
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| IRQ 88 | External IRQ(5) | Progr | Progr | Non |
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| IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
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| IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
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| IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
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| IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
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| IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
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| IRQ 94 | Reserved | N/A | N/A | Non |
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| IRQ 95 | Reserved | N/A | N/A | Non |
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|---------------------------------------------------------------------
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+---------+-----------------------------------+-------+-------+------*/
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/*--------------------------------------------------------------------+
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| Initialise UIC registers. Clear all interrupts. Disable all
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| interrupts.
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| Set critical interrupt values. Set interrupt polarities. Set
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| interrupt trigger levels. Make bit 0 High priority. Clear all
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| interrupts again.
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+-------------------------------------------------------------------*/
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mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
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mtdcr (uic2er, 0x00000000); /* disable all interrupts */
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mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
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mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
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mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
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mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
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mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
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mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
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mtdcr (uic1er, 0x00000000); /* disable all interrupts */
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mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
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mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
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mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
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mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
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mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
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mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
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mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
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/* Except cascade UIC0 and UIC1 */
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mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
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mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
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mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
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mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
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mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
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/*
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* Note: Some cores are still in reset when the chip starts, so
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* take them out of reset
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*/
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mtsdr(SDR0_SRST, 0);
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fpga_init();
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/* Configure 405EX for NAND usage */
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val = SDR0_CUST0_MUX_NDFC_SEL |
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SDR0_CUST0_NDFC_ENABLE |
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SDR0_CUST0_NDFC_BW_8_BIT |
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SDR0_CUST0_NRB_BUSY |
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(0x80000000 >> (28 + CFG_NAND_CS));
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mtsdr(SDR0_CUST0, val);
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return 0;
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}
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int misc_init_r(void)
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{
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#ifdef CFG_ENV_IS_IN_FLASH
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/* Monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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-CFG_MONITOR_LEN,
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0xffffffff,
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&flash_info[0]);
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#endif
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return 0;
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}
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int board_emac_count(void)
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{
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u32 pvr = get_pvr();
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/*
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* 405EXr only has one EMAC interface, 405EX has two
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*/
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if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
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return 1;
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else
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return 2;
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}
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static int board_pcie_count(void)
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{
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u32 pvr = get_pvr();
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/*
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* 405EXr only has one EMAC interface, 405EX has two
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*/
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if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
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return 1;
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else
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return 2;
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}
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int checkboard (void)
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{
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char *s = getenv("serial#");
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u32 pvr = get_pvr();
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if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
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printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
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else
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printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return (0);
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}
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int pci_pre_init(struct pci_controller * hose )
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{
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return 0;
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}
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#endif /* defined(CONFIG_PCI) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller * hose )
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{
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/*-------------------------------------------------------------------+
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* Disable everything
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*-------------------------------------------------------------------*/
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out32r( PCIX0_PIM0SA, 0 ); /* disable */
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out32r( PCIX0_PIM1SA, 0 ); /* disable */
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out32r( PCIX0_PIM2SA, 0 ); /* disable */
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out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
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/*-------------------------------------------------------------------+
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
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* strapping options to not support sizes such as 128/256 MB.
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*-------------------------------------------------------------------*/
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out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
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out32r( PCIX0_PIM0LAH, 0 );
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out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
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out32r( PCIX0_BAR0, 0 );
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/*-------------------------------------------------------------------+
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* Program the board's subsystem id/vendor id
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*-------------------------------------------------------------------*/
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out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
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out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
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out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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#ifdef CONFIG_PCI
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static struct pci_controller pcie_hose[2] = {{0},{0}};
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void pcie_setup_hoses(int busno)
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{
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struct pci_controller *hose;
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int i, bus;
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int ret = 0;
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bus = busno;
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char *env;
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unsigned int delay;
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for (i = 0; i < board_pcie_count(); i++) {
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if (is_end_point(i)) {
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printf("PCIE%d: will be configured as endpoint\n", i);
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ret = ppc4xx_init_pcie_endport(i);
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} else {
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printf("PCIE%d: will be configured as root-complex\n", i);
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ret = ppc4xx_init_pcie_rootport(i);
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}
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if (ret) {
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printf("PCIE%d: initialization failed\n", i);
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continue;
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}
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hose = &pcie_hose[i];
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hose->first_busno = bus;
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hose->last_busno = bus;
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hose->current_busno = bus;
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/* setup mem resource */
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pci_set_region(hose->regions + 0,
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CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
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CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
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CFG_PCIE_MEMSIZE,
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PCI_REGION_MEM);
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hose->region_count = 1;
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pci_register_hose(hose);
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if (is_end_point(i)) {
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ppc4xx_setup_pcie_endpoint(hose, i);
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/*
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* Reson for no scanning is endpoint can not generate
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* upstream configuration accesses.
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*/
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} else {
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ppc4xx_setup_pcie_rootpoint(hose, i);
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env = getenv ("pciscandelay");
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if (env != NULL) {
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delay = simple_strtoul(env, NULL, 10);
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if (delay > 5)
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printf("Warning, expect noticable delay before "
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"PCIe scan due to 'pciscandelay' value!\n");
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mdelay(delay * 1000);
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}
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/*
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* Config access can only go down stream
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*/
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hose->last_busno = pci_hose_scan(hose);
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bus = hose->last_busno + 1;
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}
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}
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}
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#endif
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#if defined(CONFIG_POST)
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/*
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* Returns 1 if keys pressed to start the power-on long-running tests
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* Called from board_init_f().
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*/
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int post_hotkeys_pressed(void)
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{
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return 0; /* No hotkeys supported */
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}
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#endif /* CONFIG_POST */
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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u32 val[4];
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int rc;
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ft_cpu_setup(blob, bd);
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/* Fixup NOR mapping */
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val[0] = 0; /* chip select number */
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val[1] = 0; /* always 0 */
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val[2] = gd->bd->bi_flashstart;
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val[3] = gd->bd->bi_flashsize;
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rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
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val, sizeof(val), 1);
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if (rc)
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printf("Unable to update property NOR mapping, err=%s\n",
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fdt_strerror(rc));
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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