393 lines
9.8 KiB
C
393 lines
9.8 KiB
C
/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <gdsys_fpga.h>
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#define CH7301_I2C_ADDR 0x75
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#define ICS8N3QV01_I2C_ADDR 0x6E
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#define ICS8N3QV01_FREF 114285
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#define SIL1178_MASTER_I2C_ADDRESS 0x38
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#define SIL1178_SLAVE_I2C_ADDRESS 0x39
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#define PIXCLK_640_480_60 25180000
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#define BASE_WIDTH 32
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#define BASE_HEIGHT 16
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#define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
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enum {
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CH7301_CM = 0x1c, /* Clock Mode Register */
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CH7301_IC = 0x1d, /* Input Clock Register */
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CH7301_GPIO = 0x1e, /* GPIO Control Register */
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CH7301_IDF = 0x1f, /* Input Data Format Register */
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CH7301_CD = 0x20, /* Connection Detect Register */
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CH7301_DC = 0x21, /* DAC Control Register */
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CH7301_HPD = 0x23, /* Hot Plug Detection Register */
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CH7301_TCTL = 0x31, /* DVI Control Input Register */
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CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
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CH7301_TPD = 0x34, /* DVI PLL Divide Register */
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CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
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CH7301_TPF = 0x36, /* DVI PLL Filter Register */
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CH7301_TCT = 0x37, /* DVI Clock Test Register */
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CH7301_TSTP = 0x48, /* Test Pattern Register */
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CH7301_PM = 0x49, /* Power Management register */
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CH7301_VID = 0x4a, /* Version ID Register */
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CH7301_DID = 0x4b, /* Device ID Register */
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CH7301_DSP = 0x56, /* DVI Sync polarity Register */
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};
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#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
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static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
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{
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
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ihs_i2c_t *i2c = &fpga->i2c;
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while (in_le16(&fpga->extended_interrupt) & (1 << 12))
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;
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out_le16(&i2c->write_mailbox_ext, reg | (data << 8));
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out_le16(&i2c->write_mailbox, 0xc400 | (slave << 1));
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}
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static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
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{
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
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ihs_i2c_t *i2c = &fpga->i2c;
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unsigned int ctr = 0;
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while (in_le16(&fpga->extended_interrupt) & (1 << 12))
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;
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out_le16(&fpga->extended_interrupt, 1 << 14);
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out_le16(&i2c->write_mailbox_ext, reg);
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out_le16(&i2c->write_mailbox, 0xc000 | (slave << 1));
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while (!(in_le16(&fpga->extended_interrupt) & (1 << 14))) {
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udelay(100000);
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if (ctr++ > 5) {
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printf("iic receive timeout\n");
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break;
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}
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}
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return in_le16(&i2c->read_mailbox_ext) >> 8;
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}
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#endif
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#ifdef CONFIG_SYS_MPC92469AC
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static void mpc92469ac_calc_parameters(unsigned int fout,
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unsigned int *post_div, unsigned int *feedback_div)
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{
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unsigned int n = *post_div;
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unsigned int m = *feedback_div;
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unsigned int a;
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unsigned int b = 14745600 / 16;
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if (fout < 50169600)
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n = 8;
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else if (fout < 100339199)
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n = 4;
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else if (fout < 200678399)
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n = 2;
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else
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n = 1;
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a = fout * n + (b / 2); /* add b/2 for proper rounding */
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m = a / b;
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*post_div = n;
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*feedback_div = m;
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}
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static void mpc92469ac_set(unsigned screen, unsigned int fout)
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{
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
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unsigned int n;
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unsigned int m;
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unsigned int bitval = 0;
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mpc92469ac_calc_parameters(fout, &n, &m);
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switch (n) {
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case 1:
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bitval = 0x00;
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break;
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case 2:
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bitval = 0x01;
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break;
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case 4:
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bitval = 0x02;
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break;
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case 8:
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bitval = 0x03;
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break;
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}
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out_le16(&fpga->mpc3w_control, (bitval << 9) | m);
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}
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#endif
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#ifdef CONFIG_SYS_ICS8N3QV01
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static void ics8n3qv01_calc_parameters(unsigned int fout,
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unsigned int *_mint, unsigned int *_mfrac,
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unsigned int *_n)
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{
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unsigned int n;
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unsigned int foutiic;
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unsigned int fvcoiic;
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unsigned int mint;
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unsigned long long mfrac;
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n = 2550000000U / fout;
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if ((n & 1) && (n > 5))
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n -= 1;
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foutiic = fout - (fout / 10000);
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fvcoiic = foutiic * n;
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mint = fvcoiic / 114285000;
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if ((mint < 17) || (mint > 63))
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printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
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mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
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/ 114285000LL;
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*_mint = mint;
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*_mfrac = mfrac;
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*_n = n;
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}
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static void ics8n3qv01_set(unsigned screen, unsigned int fout)
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{
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unsigned int n;
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unsigned int mint;
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unsigned int mfrac;
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u8 reg0, reg4, reg8, reg12, reg18, reg20;
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ics8n3qv01_calc_parameters(fout, &mint, &mfrac, &n);
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reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
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reg0 |= (mint & 0x1f) << 1;
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reg0 |= (mfrac >> 17) & 0x01;
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fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
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reg4 = mfrac >> 9;
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fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
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reg8 = mfrac >> 1;
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fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
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reg12 = mfrac << 7;
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reg12 |= n & 0x7f;
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fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
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reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
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reg18 |= 0x20;
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fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
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reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
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reg20 |= mint & (1 << 5);
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fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
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}
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#endif
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static int osd_write_videomem(unsigned screen, unsigned offset,
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u16 *data, size_t charcount)
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{
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ihs_fpga_t *fpga =
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(ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
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unsigned int k;
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for (k = 0; k < charcount; ++k) {
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if (offset + k >= BUFSIZE)
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return -1;
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out_le16(&fpga->videomem + offset + k, data[k]);
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}
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return charcount;
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}
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static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned screen;
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for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
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unsigned x;
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unsigned y;
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unsigned charcount;
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unsigned len;
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u8 color;
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unsigned int k;
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u16 buf[BUFSIZE];
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char *text;
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int res;
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if (argc < 5) {
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cmd_usage(cmdtp);
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return 1;
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}
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x = simple_strtoul(argv[1], NULL, 16);
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y = simple_strtoul(argv[2], NULL, 16);
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color = simple_strtoul(argv[3], NULL, 16);
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text = argv[4];
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charcount = strlen(text);
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len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
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for (k = 0; k < len; ++k)
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buf[k] = (text[k] << 8) | color;
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res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len);
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if (res < 0)
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return res;
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}
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return 0;
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}
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int osd_probe(unsigned screen)
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{
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
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ihs_osd_t *osd = &fpga->osd;
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u16 version = in_le16(&osd->version);
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u16 features = in_le16(&osd->features);
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unsigned width;
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unsigned height;
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u8 value;
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width = ((features & 0x3f00) >> 8) + 1;
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height = (features & 0x001f) + 1;
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printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
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screen, version/100, version%100, width, height);
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#ifdef CONFIG_SYS_CH7301
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value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
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if (value != 0x17) {
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printf(" Probing CH7301 failed, DID %02x\n", value);
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return -1;
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}
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
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i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
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#endif
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#ifdef CONFIG_SYS_MPC92469AC
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mpc92469ac_set(screen, PIXCLK_640_480_60);
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#endif
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#ifdef CONFIG_SYS_ICS8N3QV01
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ics8n3qv01_set(screen, PIXCLK_640_480_60);
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#endif
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#ifdef CONFIG_SYS_SIL1178
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value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
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if (value != 0x06) {
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printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
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return -1;
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}
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/* magic initialization sequence adapted from datasheet */
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fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
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fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
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#endif
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out_le16(&fpga->videocontrol, 0x0002);
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out_le16(&osd->control, 0x0049);
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out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1));
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return 0;
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}
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int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned screen;
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for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
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unsigned x;
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unsigned y;
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unsigned k;
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u16 buffer[BASE_WIDTH];
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char *rp;
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u16 *wp = buffer;
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unsigned count = (argc > 4) ?
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simple_strtoul(argv[4], NULL, 16) : 1;
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if ((argc < 4) || (strlen(argv[3]) % 4)) {
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cmd_usage(cmdtp);
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return 1;
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}
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x = simple_strtoul(argv[1], NULL, 16);
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y = simple_strtoul(argv[2], NULL, 16);
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rp = argv[3];
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while (*rp) {
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char substr[5];
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memcpy(substr, rp, 4);
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substr[4] = 0;
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*wp = simple_strtoul(substr, NULL, 16);
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rp += 4;
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wp++;
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if (wp - buffer > BASE_WIDTH)
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break;
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}
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for (k = 0; k < count; ++k) {
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unsigned offset =
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y * BASE_WIDTH + x + k * (wp - buffer);
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osd_write_videomem(screen, offset, buffer,
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wp - buffer);
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}
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}
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return 0;
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}
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U_BOOT_CMD(
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osdw, 5, 0, osd_write,
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"write 16-bit hex encoded buffer to osd memory",
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"pos_x pos_y buffer count\n"
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);
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U_BOOT_CMD(
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osdp, 5, 0, osd_print,
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"write ASCII buffer to osd memory",
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"pos_x pos_y color text\n"
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);
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