200 lines
5.9 KiB
C
200 lines
5.9 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Change log:
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*
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* 20050101: Eran Liberty (liberty@freescale.com)
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* Initial file creating (porting from 85XX & 8260)
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*/
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#include <common.h>
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#include <mpc83xx.h>
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#include <ioports.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f (volatile immap_t * im)
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{
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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/* system performance tweaking */
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#ifdef CFG_ACR_PIPE_DEP
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/* Arbiter pipeline depth */
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im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT);
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#endif
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#ifdef CFG_SPCR_TSEC1EP
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/* TSEC1 Emergency priority */
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im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT);
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#endif
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#ifdef CFG_SPCR_TSEC2EP
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/* TSEC2 Emergency priority */
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im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT);
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#endif
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#ifdef CFG_SCCR_TSEC1CM
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/* TSEC1 clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT);
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#endif
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#ifdef CFG_SCCR_TSEC2CM
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/* TSEC2 & I2C1 clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT);
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#endif
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#ifdef CFG_ACR_RPTCNT
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/* Arbiter repeat count */
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im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT));
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#endif
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/* RSR - Reset Status Register - clear all status (4.6.1.3) */
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gd->reset_status = im->reset.rsr;
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im->reset.rsr = ~(RSR_RES);
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/*
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* RMR - Reset Mode Register
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* contains checkstop reset enable (4.6.1.4)
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*/
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im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
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/* LCRR - Clock Ratio Register (10.3.1.16) */
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im->lbus.lcrr = CFG_LCRR;
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/* Enable Time Base & Decrimenter ( so we will have udelay() )*/
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im->sysconf.spcr |= SPCR_TBEN;
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/* System General Purpose Register */
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#ifdef CFG_SICRH
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im->sysconf.sicrh = CFG_SICRH;
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#endif
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#ifdef CFG_SICRL
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im->sysconf.sicrl = CFG_SICRL;
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#endif
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/*
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* Memory Controller:
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*/
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/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
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* addresses - these have to be modified later when FLASH size
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* has been determined
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*/
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#if defined(CFG_BR0_PRELIM) \
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&& defined(CFG_OR0_PRELIM) \
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&& defined(CFG_LBLAWBAR0_PRELIM) \
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&& defined(CFG_LBLAWAR0_PRELIM)
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im->lbus.bank[0].br = CFG_BR0_PRELIM;
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im->lbus.bank[0].or = CFG_OR0_PRELIM;
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im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM;
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im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM;
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#else
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#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
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#endif
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#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
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im->lbus.bank[1].br = CFG_BR1_PRELIM;
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im->lbus.bank[1].or = CFG_OR1_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM)
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im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
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im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
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#endif
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#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
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im->lbus.bank[2].br = CFG_BR2_PRELIM;
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im->lbus.bank[2].or = CFG_OR2_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM)
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im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
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im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
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#endif
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#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
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im->lbus.bank[3].br = CFG_BR3_PRELIM;
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im->lbus.bank[3].or = CFG_OR3_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM)
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im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
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im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
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#endif
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#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
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im->lbus.bank[4].br = CFG_BR4_PRELIM;
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im->lbus.bank[4].or = CFG_OR4_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM)
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im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
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im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
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#endif
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#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
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im->lbus.bank[5].br = CFG_BR5_PRELIM;
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im->lbus.bank[5].or = CFG_OR5_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM)
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im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
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im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
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#endif
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#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
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im->lbus.bank[6].br = CFG_BR6_PRELIM;
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im->lbus.bank[6].or = CFG_OR6_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM)
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im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
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im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
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#endif
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#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
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im->lbus.bank[7].br = CFG_BR7_PRELIM;
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im->lbus.bank[7].or = CFG_OR7_PRELIM;
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#endif
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#if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM)
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im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
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im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
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#endif
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#ifdef CFG_GPIO1_PRELIM
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im->pgio[0].dir = CFG_GPIO1_DIR;
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im->pgio[0].dat = CFG_GPIO1_DAT;
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#endif
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#ifdef CFG_GPIO2_PRELIM
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im->pgio[1].dir = CFG_GPIO2_DIR;
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im->pgio[1].dat = CFG_GPIO2_DAT;
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#endif
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}
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/*
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* Initialize higher level parts of CPU like time base and timers.
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*/
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int cpu_init_r (void)
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{
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return 0;
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}
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