285 lines
6.4 KiB
C
285 lines
6.4 KiB
C
/*
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* Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
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* (C) Copyright 2002, 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <fsl_esdhc.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/fsl_law.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkcpu (void)
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{
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sys_info_t sysinfo;
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uint pvr, svr;
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uint fam;
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uint ver;
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uint major, minor;
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struct cpu_type *cpu;
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char buf1[32], buf2[32];
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#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#endif /* CONFIG_FSL_CORENET */
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#ifdef CONFIG_DDR_CLK_FREQ
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u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
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>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
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#else
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#ifdef CONFIG_FSL_CORENET
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u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
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>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
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#else
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u32 ddr_ratio = 0;
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#endif /* CONFIG_FSL_CORENET */
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#endif /* CONFIG_DDR_CLK_FREQ */
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int i;
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svr = get_svr();
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major = SVR_MAJ(svr);
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#ifdef CONFIG_MPC8536
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major &= 0x7; /* the msb of this nibble is a mfg code */
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#endif
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minor = SVR_MIN(svr);
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if (cpu_numcores() > 1) {
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#ifndef CONFIG_MP
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puts("Unicore software on multiprocessor system!!\n"
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"To enable mutlticore build define CONFIG_MP\n");
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#endif
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volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
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printf("CPU%d: ", pic->whoami);
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} else {
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puts("CPU: ");
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}
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cpu = gd->cpu;
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puts(cpu->name);
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if (IS_E_PROCESSOR(svr))
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puts("E");
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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pvr = get_pvr();
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fam = PVR_FAM(pvr);
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ver = PVR_VER(pvr);
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major = PVR_MAJ(pvr);
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minor = PVR_MIN(pvr);
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printf("Core: ");
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if (PVR_FAM(PVR_85xx)) {
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switch(PVR_MEM(pvr)) {
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case 0x1:
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case 0x2:
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puts("E500");
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break;
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case 0x3:
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puts("E500MC");
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break;
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case 0x4:
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puts("E5500");
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break;
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default:
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puts("Unknown");
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break;
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}
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} else {
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puts("Unknown");
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}
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
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get_sys_info(&sysinfo);
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puts("Clock Configuration:");
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for (i = 0; i < cpu_numcores(); i++) {
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if (!(i & 3))
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printf ("\n ");
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printf("CPU%d:%-4s MHz, ",
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i,strmhz(buf1, sysinfo.freqProcessor[i]));
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}
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printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
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#ifdef CONFIG_FSL_CORENET
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if (ddr_sync == 1) {
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printf(" DDR:%-4s MHz (%s MT/s data rate) "
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"(Synchronous), ",
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strmhz(buf1, sysinfo.freqDDRBus/2),
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strmhz(buf2, sysinfo.freqDDRBus));
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} else {
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printf(" DDR:%-4s MHz (%s MT/s data rate) "
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"(Asynchronous), ",
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strmhz(buf1, sysinfo.freqDDRBus/2),
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strmhz(buf2, sysinfo.freqDDRBus));
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}
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#else
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switch (ddr_ratio) {
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case 0x0:
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printf(" DDR:%-4s MHz (%s MT/s data rate), ",
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strmhz(buf1, sysinfo.freqDDRBus/2),
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strmhz(buf2, sysinfo.freqDDRBus));
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break;
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case 0x7:
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printf(" DDR:%-4s MHz (%s MT/s data rate) "
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"(Synchronous), ",
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strmhz(buf1, sysinfo.freqDDRBus/2),
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strmhz(buf2, sysinfo.freqDDRBus));
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break;
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default:
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printf(" DDR:%-4s MHz (%s MT/s data rate) "
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"(Asynchronous), ",
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strmhz(buf1, sysinfo.freqDDRBus/2),
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strmhz(buf2, sysinfo.freqDDRBus));
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break;
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}
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#endif
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if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
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printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
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} else {
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printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
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sysinfo.freqLocalBus);
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}
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#ifdef CONFIG_CPM2
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printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
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#endif
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#ifdef CONFIG_QE
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printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
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printf(" FMAN%d: %s MHz\n", i,
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strmhz(buf1, sysinfo.freqFMan[i]));
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}
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#endif
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#ifdef CONFIG_SYS_DPAA_PME
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printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
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#endif
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puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char * const argv[])
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{
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/* Everything after the first generation of PQ3 parts has RSTCR */
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#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
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defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
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unsigned long val, msr;
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/*
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* Initiate hard reset in debug control register DBCR0
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* Make sure MSR[DE] = 1. This only resets the core.
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*/
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msr = mfmsr ();
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msr |= MSR_DE;
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mtmsr (msr);
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val = mfspr(DBCR0);
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val |= 0x70000000;
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mtspr(DBCR0,val);
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#else
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */
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udelay(100);
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#endif
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return 1;
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}
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/*
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* Get timebase clock frequency
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*/
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unsigned long get_tbclk (void)
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{
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#ifdef CONFIG_FSL_CORENET
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return (gd->bus_clk + 8) / 16;
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#else
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return (gd->bus_clk + 4UL)/8UL;
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#endif
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}
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#if defined(CONFIG_WATCHDOG)
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void
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watchdog_reset(void)
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{
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int re_enable = disable_interrupts();
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reset_85xx_watchdog();
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if (re_enable) enable_interrupts();
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}
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void
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reset_85xx_watchdog(void)
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{
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/*
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* Clear TSR(WIS) bit by writing 1
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*/
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unsigned long val;
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val = mfspr(SPRN_TSR);
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val |= TSR_WIS;
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mtspr(SPRN_TSR, val);
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}
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#endif /* CONFIG_WATCHDOG */
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/*
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* Initializes on-chip MMC controllers.
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* to override, implement board_mmc_init()
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*/
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int cpu_mmc_init(bd_t *bis)
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{
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#ifdef CONFIG_FSL_ESDHC
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return fsl_esdhc_mmc_init(bis);
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#else
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return 0;
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#endif
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}
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/*
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* Print out the state of various machine registers.
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* Currently prints out LAWs, BR0/OR0, and TLBs
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*/
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void mpc85xx_reginfo(void)
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{
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print_tlbcam();
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print_laws();
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print_lbc_regs();
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}
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