348 lines
10 KiB
C
348 lines
10 KiB
C
/*
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* MPC8260 FCC Fast Ethernet
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*
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* Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
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*
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* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* MPC8260 FCC Fast Ethernet
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* Basic ET HW initialization and packet RX/TX routines
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*
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* This code will not perform the IO port configuration. This should be
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* done in the iop_conf_t structure specific for the board.
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*
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* TODO:
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* add a PHY driver to do the negotiation
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* reflect negotiation results in FPSMR
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* look for ways to configure the board specific stuff elsewhere, eg.
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* config_xxx.h or the board directory
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*/
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#include <common.h>
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#include <asm/cpm_8260.h>
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#include <mpc8260.h>
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#include <net.h>
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#include <command.h>
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#include <config.h>
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#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET)
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/*---------------------------------------------------------------------*/
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#if (CONFIG_ETHER_INDEX == 1)
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#define PROFF_ENET PROFF_FCC1
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#define CPM_CR_ENET_SBLOCK CPM_CR_FCC1_SBLOCK
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#define CPM_CR_ENET_SBLOCK CPM_CR_FCC1_SBLOCK
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#define CPM_CR_ENET_PAGE CPM_CR_FCC1_PAGE
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/*---------------------------------------------------------------------*/
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#elif (CONFIG_ETHER_INDEX == 2)
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#define PROFF_ENET PROFF_FCC2
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#define CPM_CR_ENET_SBLOCK CPM_CR_FCC2_SBLOCK
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#define CPM_CR_ENET_PAGE CPM_CR_FCC2_PAGE
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/*---------------------------------------------------------------------*/
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#elif (CONFIG_ETHER_INDEX == 3)
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#define PROFF_ENET PROFF_FCC3
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#define CPM_CR_ENET_SBLOCK CPM_CR_FCC3_SBLOCK
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#define CPM_CR_ENET_PAGE CPM_CR_FCC3_PAGE
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/*---------------------------------------------------------------------*/
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#else
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#error "FCC Ethernet not correctly defined"
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#endif
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/*---------------------------------------------------------------------*/
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/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
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#define PKT_MAXDMA_SIZE 1520
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/* The FCC stores dest/src/type, data, and checksum for receive packets. */
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#define PKT_MAXBUF_SIZE 1518
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#define PKT_MINBUF_SIZE 64
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/* Maximum input buffer size. Must be a multiple of 32. */
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#define PKT_MAXBLR_SIZE 1536
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#define TOUT_LOOP 1000000
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#define TX_BUF_CNT 2
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#ifdef __GNUC__
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static char txbuf[TX_BUF_CNT][PKT_MAXBLR_SIZE] __attribute__ ((aligned(8)));
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#else
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#error "txbuf must be 64-bit aligned"
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#endif
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static uint rxIdx; /* index of the current RX buffer */
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static uint txIdx; /* index of the current TX buffer */
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/*
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* FCC Ethernet Tx and Rx buffer descriptors.
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* Provide for Double Buffering
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* Note: PKTBUFSRX is defined in net.h
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*/
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typedef volatile struct rtxbd {
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cbd_t rxbd[PKTBUFSRX];
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cbd_t txbd[TX_BUF_CNT];
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} RTXBD;
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/* Good news: the FCC supports external BDs! */
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#ifdef __GNUC__
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static RTXBD rtx __attribute__ ((aligned(8)));
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#else
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#error "rtx must be 64-bit aligned"
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#endif
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int eth_send(volatile void *packet, int length)
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{
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int i;
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int result = 0;
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if (length <= 0) {
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printf("fec: bad packet size: %d\n", length);
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goto out;
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}
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for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
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if (i >= TOUT_LOOP) {
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printf("fec: tx buffer not ready\n");
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goto out;
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}
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}
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rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
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rtx.txbd[txIdx].cbd_datlen = length;
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rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
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BD_ENET_TX_WRAP);
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for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
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if (i >= TOUT_LOOP) {
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printf("fec: tx error\n");
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goto out;
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}
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}
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#ifdef ET_DEBUG
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printf("cycles: %d status: %04x\n", i, rtx.txbd[txIdx].cbd_sc);
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#endif
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/* return only status bits */
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result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
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out:
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return result;
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}
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int eth_rx(void)
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{
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int length;
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for (;;)
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{
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if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
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length = -1;
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break; /* nothing received - leave for() loop */
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}
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length = rtx.rxbd[rxIdx].cbd_datlen;
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if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
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printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
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}
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else {
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/* Pass the packet up to the protocol layers. */
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NetReceive(NetRxPackets[rxIdx], length - 4);
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}
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/* Give the buffer back to the FCC. */
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rtx.rxbd[rxIdx].cbd_datlen = 0;
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/* wrap around buffer index when necessary */
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if ((rxIdx + 1) >= PKTBUFSRX) {
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rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
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rxIdx = 0;
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}
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else {
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rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
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rxIdx++;
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}
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}
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return length;
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}
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int eth_init(bd_t *bis)
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{
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int i;
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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volatile cpm8260_t *cp = &(immr->im_cpm);
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fcc_enet_t *pram_ptr;
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unsigned long mem_addr;
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#if 0
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mii_discover_phy();
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#endif
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/* 28.9 - (1-2): ioports have been set up already */
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/* 28.9 - (3): connect FCC's tx and rx clocks */
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immr->im_cpmux.cmx_uar = 0;
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immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~CFG_CMXFCR_MASK) |
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CFG_CMXFCR_VALUE;
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/* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
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immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_gfmr =
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FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
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/* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet */
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immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
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/* 28.9 - (6): FDSR: Ethernet Syn */
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immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fdsr = 0xD555;
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/* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
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rxIdx = 0;
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txIdx = 0;
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/* Setup Receiver Buffer Descriptors */
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for (i = 0; i < PKTBUFSRX; i++)
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{
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rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
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rtx.rxbd[i].cbd_datlen = 0;
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rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
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}
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rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
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/* Setup Ethernet Transmitter Buffer Descriptors */
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for (i = 0; i < TX_BUF_CNT; i++)
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{
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rtx.txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
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rtx.txbd[i].cbd_datlen = 0;
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rtx.txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
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}
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rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
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/* 28.9 - (7): initialise parameter ram */
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pram_ptr = (fcc_enet_t *)&(immr->im_dprambase[PROFF_ENET]);
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/* clear whole structure to make sure all reserved fields are zero */
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memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
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/*
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* common Parameter RAM area
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*
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* Allocate space in the reserved FCC area of DPRAM for the
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* internal buffers. No one uses this space (yet), so we
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* can do this. Later, we will add resource management for
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* this area.
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*/
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mem_addr = CPM_FCC_SPECIAL_BASE + ((CONFIG_ETHER_INDEX-1) * 64);
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pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
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pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
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/*
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* Set maximum bytes per receive buffer.
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* It must be a multiple of 32.
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*/
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pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
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pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
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CFG_CPMFCR_RAMTYPE) << 24;
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pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
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pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
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CFG_CPMFCR_RAMTYPE) << 24;
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pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
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/* protocol-specific area */
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pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
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pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
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pram_ptr->fen_retlim = 15; /* Retry limit threshold */
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pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
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/*
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* Set Ethernet station address.
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*
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* This is supplied in the board information structure, so we
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* copy that into the controller.
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* So, far we have only been given one Ethernet address. We make
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* it unique by setting a few bits in the upper byte of the
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* non-static part of the address.
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*/
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#define ea bis->bi_enetaddr
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pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
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pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
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pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
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#undef ea
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pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
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/* pad pointer. use tiptr since we don't need a specific padding char */
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pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
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pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
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pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
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pram_ptr->fen_rfthr = 1;
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pram_ptr->fen_rfcnt = 1;
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#if 0
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printf("pram_ptr->fen_genfcc.fcc_rbase %08lx\n",
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pram_ptr->fen_genfcc.fcc_rbase);
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printf("pram_ptr->fen_genfcc.fcc_tbase %08lx\n",
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pram_ptr->fen_genfcc.fcc_tbase);
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#endif
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/* 28.9 - (8): clear out events in FCCE */
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immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fcce = ~0x0;
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/* 28.9 - (9): FCCM: mask all events */
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immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_fccm = 0;
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/* 28.9 - (10-12): we don't use ethernet interrupts */
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/* 28.9 - (13)
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*
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* Let's re-initialize the channel now. We have to do it later
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* than the manual describes because we have just now finished
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* the BD initialization.
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*/
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cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
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CPM_CR_ENET_SBLOCK,
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0x0c,
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CPM_CR_INIT_TRX) | CPM_CR_FLG;
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do {
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__asm__ __volatile__ ("eieio");
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} while (cp->cp_cpcr & CPM_CR_FLG);
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/* 28.9 - (14): enable tx/rx in gfmr */
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immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
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return 1;
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}
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void eth_halt(void)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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/* write GFMR: disable tx/rx */
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immr->im_fcc[CONFIG_ETHER_INDEX-1].fcc_gfmr &=
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~(FCC_GFMR_ENT | FCC_GFMR_ENR);
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}
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#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET */
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