490 lines
13 KiB
C
490 lines
13 KiB
C
/*
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* (C) Copyright 2006-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Rework by Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <linux/err.h>
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#include <asm/arch-mtk/vibra.h>
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/*
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* SPL has no malloc availble and below are definitions of some temporary
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* buffers in RAM for general purpose.
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*/
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#define RAM_BUF1 (CONFIG_SYS_SDRAM_BASE + 0x1000)
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#define RAM_BUF2 (RAM_BUF1 + 0x1000)
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#define RAM_BUF3 (RAM_BUF2 + 0x1000)
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/*
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* Macro which counts zeroes until first set bit.
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* This is used to avoid dividing, so no additional library is needed.
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* It's important as this file is compiled also in SPL and there is no need
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* to link additional library.
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*/
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#ifdef CONFIG_ARM926EJS
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#define COUNT_ZEROES(x) __builtin_ctz(x)
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#else
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#define COUNT_ZEROES(x) (ffs(x) - 1)
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#endif
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nand_info_t nand_info[1];
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#define CONFIG_SYS_NAND_READ_DELAY \
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{ volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
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/*
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* NAND command for small page NAND devices (512)
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*/
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static void nand_command(struct mtd_info *mtd, unsigned int cmd,
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int column, int page_addr)
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{
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struct nand_chip *chip = mtd->priv;
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int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
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if (chip->dev_ready)
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while (!chip->dev_ready(mtd))
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;
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else
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CONFIG_SYS_NAND_READ_DELAY;
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/* Begin command latch cycle */
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chip->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
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/* Serially input address */
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if (column != -1) {
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/* Adjust columns for 16 bit buswidth */
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if (chip->options & NAND_BUSWIDTH_16)
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column >>= 1;
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chip->cmd_ctrl(mtd, column, ctrl);
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ctrl &= ~NAND_CTRL_CHANGE;
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}
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if (page_addr != -1) {
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chip->cmd_ctrl(mtd, page_addr, ctrl);
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ctrl &= ~NAND_CTRL_CHANGE;
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chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
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/* One more address cycle for devices > 32MiB */
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if (chip->chipsize > (32 << 20))
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chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
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}
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chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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/*
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* Wait a while for the data to be ready
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*/
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if (chip->dev_ready)
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while (!chip->dev_ready(mtd))
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;
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else
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CONFIG_SYS_NAND_READ_DELAY;
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}
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/*
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* NAND command for large page NAND devices (2k)
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*/
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static void nand_command_lp(struct mtd_info *mtd, unsigned int cmd, int column,
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int page_addr)
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{
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struct nand_chip *chip = mtd->priv;
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if (chip->dev_ready)
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while (!chip->dev_ready(mtd))
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;
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else
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CONFIG_SYS_NAND_READ_DELAY;
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/* Emulate NAND_CMD_READOOB */
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if (cmd == NAND_CMD_READOOB) {
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page_addr += mtd->writesize;
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cmd = NAND_CMD_READ0;
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}
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/* Command latch cycle */
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chip->cmd_ctrl(mtd, cmd & 0xff,
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NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
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if (column != -1 || page_addr != -1) {
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int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
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/* Serially input address */
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if (column != -1) {
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/* Adjust columns for 16 bit buswidth */
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if (chip->options & NAND_BUSWIDTH_16)
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column >>= 1;
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chip->cmd_ctrl(mtd, column, ctrl);
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ctrl &= ~NAND_CTRL_CHANGE;
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chip->cmd_ctrl(mtd, column >> 8, ctrl);
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}
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if (page_addr != -1) {
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chip->cmd_ctrl(mtd, page_addr, ctrl);
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chip->cmd_ctrl(mtd, page_addr >> 8,
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NAND_NCE | NAND_ALE);
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/* One more address cycle for devices > 128MiB */
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if (chip->chipsize > (128 << 20))
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chip->cmd_ctrl(mtd, page_addr >> 16,
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NAND_NCE | NAND_ALE);
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}
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}
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chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
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NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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/*
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* Wait a while for the data to be ready
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*/
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if (chip->dev_ready)
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while (!chip->dev_ready(mtd))
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;
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else
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CONFIG_SYS_NAND_READ_DELAY;
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}
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static int nand_is_bad_block(struct mtd_info *mtd, int page_addr)
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{
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struct nand_chip *chip = mtd->priv;
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if ((page_addr & (mtd->erasesize - 1)) != 0)
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/*
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* Page address is not aligned to block address,
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* in this case there is no reason to check bad block.
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*/
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return 0;
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chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page_addr);
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chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
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return (chip->oob_poi[5] != 0xFF) ? 1: 0;
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}
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static int nand_read_page(struct mtd_info *mtd, int page_addr,
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unsigned char *dst)
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{
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struct nand_chip *chip = mtd->priv;
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uint8_t *ecc_calc;
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uint8_t *ecc_code;
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int i;
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int eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccsteps = chip->ecc.steps;
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uint32_t *eccpos = chip->ecc.layout->eccpos;
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uint8_t *p = dst;
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chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page_addr);
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/*
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* No malloc available for now, just use some temporary locations
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* in SDRAM.
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*/
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ecc_calc = (uint8_t *)RAM_BUF2;
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ecc_code = (uint8_t *)RAM_BUF3;
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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chip->ecc.hwctl(mtd, NAND_ECC_READ);
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chip->read_buf(mtd, p, eccsize);
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chip->ecc.calculate(mtd, p, &ecc_calc[i]);
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}
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chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
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/* Pick the ECC bytes out of the oob data */
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for (i = 0; i < chip->ecc.total; i++)
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ecc_code[i] = chip->oob_poi[eccpos[i]];
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eccsteps = chip->ecc.steps;
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p = dst;
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for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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/*
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* No chance to do something with the possible error message
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* from correct_data(). We just hope that all possible errors
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* are corrected by this routine.
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*/
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chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
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}
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return 0;
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}
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static void nand_load(struct mtd_info *mtd, unsigned int offset,
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unsigned int size, uint8_t *dst)
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{
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unsigned int page, end_page, pages_per_block;
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/*
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* Offset should be aligned to page and block size, otherwise
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* there will be no chance to detect bad block of start offset.
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*/
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page = offset >> COUNT_ZEROES(mtd->writesize);
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end_page = page + (size >> COUNT_ZEROES(mtd->writesize));
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/* If size is not aligned to page then read one more page */
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if (size & (mtd->writesize - 1))
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end_page++;
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pages_per_block = mtd->erasesize >> COUNT_ZEROES(mtd->writesize);
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while (page < end_page) {
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/* If this read is in new block, check for babd block*/
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if ((page & (pages_per_block - 1)) == 0) {
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if (nand_is_bad_block(mtd, page)) {
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/*
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* Bad block is detected.
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* Jump to next block and continue code loading.
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* In this case not full image will be loaded.
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*/
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page += pages_per_block;
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continue;
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}
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}
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nand_read_page(mtd, page, dst);
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page++;
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dst += mtd->writesize;
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}
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}
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#if defined(CONFIG_ARM)
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void board_init_f (ulong bootflag)
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{
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relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
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CONFIG_SYS_TEXT_BASE);
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}
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#endif
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/*
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* Get the flash and manufacturer id and lookup if the type is supported
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*/
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static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
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struct nand_chip *chip,
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int busw, int *maf_id)
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{
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const struct nand_flash_dev *type = NULL;
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int i, dev_id, maf_idx;
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int tmp_id, tmp_manf;
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/* Select the device */
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chip->select_chip(mtd, 0);
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/*
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* Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
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* after power-up
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*/
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chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
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/* Send the command for reading device ID */
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chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
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/* Read manufacturer and device IDs */
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*maf_id = chip->read_byte(mtd);
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dev_id = chip->read_byte(mtd);
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/* Try again to make sure, as some systems the bus-hold or other
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* interface concerns can cause random data which looks like a
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* possibly credible NAND flash to appear. If the two results do
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* not match, ignore the device completely.
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*/
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chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
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/* Read manufacturer and device IDs */
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tmp_manf = chip->read_byte(mtd);
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tmp_id = chip->read_byte(mtd);
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if (tmp_manf != *maf_id || tmp_id != dev_id)
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return ERR_PTR(-ENODEV);
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/* Lookup the flash id */
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for (i = 0; nand_flash_ids[i].name != NULL; i++) {
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if (dev_id == nand_flash_ids[i].id) {
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type = &nand_flash_ids[i];
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break;
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}
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}
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if (!type)
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return ERR_PTR(-ENODEV);
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if (!mtd->name)
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mtd->name = type->name;
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chip->chipsize = (uint64_t)type->chipsize << 20;
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/* Newer devices have all the information in additional id bytes */
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if (!type->pagesize) {
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int extid;
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/* The 3rd id byte holds MLC / multichip data */
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chip->cellinfo = chip->read_byte(mtd);
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/* The 4th id byte is the important one */
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extid = chip->read_byte(mtd);
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/* Calc pagesize */
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mtd->writesize = 1024 << (extid & 0x3);
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extid >>= 2;
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/* Calc oobsize */
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mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
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extid >>= 2;
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/* Calc blocksize. Blocksize is multiples of 64KiB */
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mtd->erasesize = (64 * 1024) << (extid & 0x03);
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extid >>= 2;
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/* Get buswidth information */
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busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
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} else {
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/*
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* Old devices have chip data hardcoded in the device id table
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*/
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mtd->erasesize = type->erasesize;
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mtd->writesize = type->pagesize;
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mtd->oobsize = mtd->writesize / 32;
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busw = type->options & NAND_BUSWIDTH_16;
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}
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/* Try to identify manufacturer */
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for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
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if (nand_manuf_ids[maf_idx].id == *maf_id)
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break;
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}
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/*
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* Check, if buswidth is correct. Hardware drivers should set
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* chip correct !
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*/
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if (busw != (chip->options & NAND_BUSWIDTH_16))
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return ERR_PTR(-EINVAL);
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/* Calculate the address shift from the page size */
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chip->page_shift = ffs(mtd->writesize) - 1;
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chip->bbt_erase_shift = chip->phys_erase_shift =
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ffs(mtd->erasesize) - 1;
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if (chip->chipsize & 0xffffffff)
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chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
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else
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chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
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/* Set the bad block position */
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chip->badblockpos = mtd->writesize > 512 ?
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NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
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/* Get chip options, preserve non chip based options */
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chip->options &= ~NAND_CHIPOPTIONS_MSK;
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chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
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/*
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* Set chip as a default. Board drivers can override it, if necessary
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*/
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chip->options |= NAND_NO_AUTOINCR;
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/* Check if chip is a not a samsung device. Do not clear the
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* options for chips which are not having an extended id.
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*/
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if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
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chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
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/* Do not replace user supplied command function ! */
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if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
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chip->cmdfunc = nand_command_lp;
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return type;
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}
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int nand_scan_ident(struct mtd_info *mtd, int maxchips,
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const struct nand_flash_dev *table)
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{
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int busw, nand_maf_id;
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struct nand_chip *chip = mtd->priv;
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const struct nand_flash_dev *type;
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/* Get buswidth to select the correct functions */
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busw = chip->options & NAND_BUSWIDTH_16;
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/* Read the flash type */
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type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
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if (IS_ERR(type)) {
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chip->select_chip(mtd, -1);
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return PTR_ERR(type);
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}
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/* Store the number of chips and calc total size for mtd */
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chip->numchips = 1;
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mtd->size = chip->chipsize;
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return 0;
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}
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/*
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* The main entry for NAND booting. It's necessary that SDRAM is already
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* configured and available since this code loads the main U-Boot image
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* from NAND into SDRAM and starts it from there.
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*/
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void nand_boot(void)
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{
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struct nand_chip chip;
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nand_info_t *mtd = nand_info;
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__attribute__((noreturn)) void (*uboot)(void);
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vibra_on();
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/*
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* Init board specific nand support
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*/
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mtd->priv = &chip;
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chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
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chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
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chip.dev_ready = NULL;
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chip.cmdfunc = nand_command;
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chip.options = 0;
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board_nand_init(&chip);
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chip.ecc.steps = mtd->writesize >> COUNT_ZEROES(chip.ecc.size);
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chip.oob_poi = (uint8_t *)RAM_BUF1;
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if (chip.select_chip)
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chip.select_chip(mtd, 0);
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/*
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* Load U-Boot image from NAND into RAM
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*/
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nand_load(mtd, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
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(uint8_t *)CONFIG_SYS_NAND_U_BOOT_DST);
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#ifdef CONFIG_NAND_ENV_DST
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nand_load(mtd, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uint8_t *)CONFIG_NAND_ENV_DST);
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#ifdef CONFIG_ENV_OFFSET_REDUND
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nand_load(mtd, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
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(uint8_t *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
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#endif
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#endif
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if (chip.select_chip)
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chip.select_chip(mtd, -1);
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vibra_off();
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/*
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* Jump to U-Boot image
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*/
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uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
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(*uboot)();
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}
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