244 lines
8.1 KiB
C
244 lines
8.1 KiB
C
/*
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* (C) 2010 by Tieto <www.tieto.com>
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* Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
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*
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef __MTK_SYSTEM_H_
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#define __MTK_SYSTEM_H_
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/*
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* Configuration block section (Clock, Power Down, Version and Reset
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*/
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/* Register definitions */
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#define MTK_CONFG_HW_VERSION (MTK_CONFG_BASE + 0x000)
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#define MTK_CONFG_FW_VERSION (MTK_CONFG_BASE + 0x004)
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#define MTK_CONFG_HW_CODE (MTK_CONFG_BASE + 0x008)
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#define MTK_CONFG_SLEEP_CON (MTK_CONFG_BASE + 0x114)
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#define MTK_CONFG_MCUCLK_CON (MTK_CONFG_BASE + 0x118)
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#define MTK_CONFG_DSPCLK_CON (MTK_CONFG_BASE + 0x11C)
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#define MTK_CONFG_IDN_SEL (MTK_CONFG_BASE + 0x200)
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#define MTK_CONFG_PDN_CON0 (MTK_CONFG_BASE + 0x300)
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#define MTK_CONFG_PDN_CON1 (MTK_CONFG_BASE + 0x304)
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#define MTK_CONFG_PDN_CON2 (MTK_CONFG_BASE + 0x308)
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#define MTK_CONFG_PDN_CON3 (MTK_CONFG_BASE + 0x30C)
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#define MTK_CONFG_PDN_SET0 (MTK_CONFG_BASE + 0x310)
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#define MTK_CONFG_PDN_SET1 (MTK_CONFG_BASE + 0x314)
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#define MTK_CONFG_PDN_SET2 (MTK_CONFG_BASE + 0x318)
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#define MTK_CONFG_PDN_SET3 (MTK_CONFG_BASE + 0x31C)
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#define MTK_CONFG_PDN_CLR0 (MTK_CONFG_BASE + 0x320)
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#define MTK_CONFG_PDN_CLR1 (MTK_CONFG_BASE + 0x324)
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#define MTK_CONFG_PDN_CLR2 (MTK_CONFG_BASE + 0x328)
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#define MTK_CONFG_PDN_CLR3 (MTK_CONFG_BASE + 0x32C)
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#define MTK_CONFG_PDN_CON4 (MTK_CONFG_BASE + 0x330)
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#define MTK_CONFG_PDN_SET4 (MTK_CONFG_BASE + 0x334)
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#define MTK_CONFG_PDN_CLR4 (MTK_CONFG_BASE + 0x338)
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/* CONFG_MCUCLK_CON bit fields definitions */
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#define MCUCLK_CON_AHBX8CLK_SHIFT (0)
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#define MCUCLK_CON_AHBX4CLK_SHIFT (4)
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#define MCUCLK_CON_ARMCLK_SHIFT (8)
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#define MCUCLK_CON_EMICLK_SHIFT (12)
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/* PDN_CON0 bit fields definitions */
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#define PDN_CON0_CON0_DMA (1 << 0)
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#define PDN_CON0_USB (1 << 1)
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#define PDN_CON0_GCU (1 << 2)
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#define PDN_CON0_WAVE (1 << 3)
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#define PDN_CON0_SEJ (1 << 4)
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#define PDN_CON0_IR (1 << 6)
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#define PDN_CON0_PWM3 (1 << 7)
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#define PDN_CON0_PWM (1 << 8)
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#define PDN_CON0_SIM2 (1 << 10)
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#define PDN_CON0_IRDBG1 (1 << 12)
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#define PDN_CON0_IRDBG2 (1 << 13)
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/* PDN_CON1 bit fields definitions */
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#define PDN_CON1_GPT (1 << 0)
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#define PDN_CON1_KP (1 << 1)
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#define PDN_CON1_GPIO (1 << 2)
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#define PDN_CON1_UART1 (1 << 3)
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#define PDN_CON1_SIM (1 << 4)
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#define PDN_CON1_PWM1 (1 << 5)
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#define PDN_CON1_LCD (1 << 7)
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#define PDN_CON1_UART2 (1 << 8)
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#define PDN_CON1_MSDC (1 << 9)
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#define PDN_CON1_TP (1 << 10)
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#define PDN_CON1_PWM2 (1 << 11)
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#define PDN_CON1_NFI (1 << 12)
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#define PDN_CON1_UART3 (1 << 14)
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#define PDN_CON1_IRDA (1 << 15)
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/* PDN_CON2 bit fields definitions */
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#define PDN_CON2_TDMA (1 << 0)
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#define PDN_CON2_RTC (1 << 1)
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#define PDN_CON2_BSI (1 << 2)
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#define PDN_CON2_BPI (1 << 3)
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#define PDN_CON2_AFC (1 << 4)
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#define PDN_CON2_APC (1 << 5)
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#define PDN_CON2_FCS (1 << 6)
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#define PDN_CON2_AUXAD (1 << 7)
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#define PDN_CON2_VAFE (1 << 8)
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#define PDN_CON2_BFE (1 << 9)
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#define PDN_CON2_GCC (1 << 10)
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#define PDN_CON2_DIV (1 << 11)
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#define PDN_CON2_AAFE (1 << 12)
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#define PDN_CON2_I2C (1 << 13)
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#define PDN_CON2_BBRX (1 << 14)
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#define PDN_CON2_GMSK (1 << 14)
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/*
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* Reset Generation Unit block section
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*/
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#define MTK_RGU_WDT_MODE (MTK_RGU_BASE + 0x00)
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#define MTK_RGU_WDT_LENGTH (MTK_RGU_BASE + 0x04)
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#define MTK_RGU_WDT_RESTART (MTK_RGU_BASE + 0x08)
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#define MTK_RGU_WDT_STA (MTK_RGU_BASE + 0x0C)
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#define MTK_RGU_SW_PERIPH_RSTN (MTK_RGU_BASE + 0x10)
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#define MTK_RGU_SW_DSP_RSTN (MTK_RGU_BASE + 0x14)
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#define MTK_RGU_WDT_RSTINTERVAL (MTK_RGU_BASE + 0x18)
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#define MTK_RGU_WDT_SWRST (MTK_RGU_BASE + 0x1C)
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#define WDT_MODE_KEY 0x2200
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#define WDT_LENGTH_KEY 0x0008
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#define WDT_RESTART_KEY 0x1971
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#define SW_PERIPH_RSTN_KEY 0x0037
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#define WDT_SWRST_KEY 0x1209
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/*
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* RTC block section
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*/
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/* RTC registers definition */
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#define MTK_RTC_BBPU (MTK_RTC_BASE + 0x00)
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#define MTK_RTC_IRQ_STA (MTK_RTC_BASE + 0x04)
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#define MTK_RTC_IRQ_EN (MTK_RTC_BASE + 0x08)
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#define MTK_RTC_CII_EN (MTK_RTC_BASE + 0x0C)
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#define MTK_RTC_AL_MASK (MTK_RTC_BASE + 0x10)
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#define MTK_RTC_TC_SEC (MTK_RTC_BASE + 0x14)
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#define MTK_RTC_TC_MIN (MTK_RTC_BASE + 0x18)
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#define MTK_RTC_TC_HOU (MTK_RTC_BASE + 0x1C)
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#define MTK_RTC_TC_DOM (MTK_RTC_BASE + 0x20)
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#define MTK_RTC_TC_DOW (MTK_RTC_BASE + 0x24)
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#define MTK_RTC_TC_MTH (MTK_RTC_BASE + 0x28)
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#define MTK_RTC_TC_YEA (MTK_RTC_BASE + 0x2C)
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#define MTK_RTC_AL_SEC (MTK_RTC_BASE + 0x30)
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#define MTK_RTC_AL_MIN (MTK_RTC_BASE + 0x34)
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#define MTK_RTC_AL_HOU (MTK_RTC_BASE + 0x38)
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#define MTK_RTC_AL_DOM (MTK_RTC_BASE + 0x3C)
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#define MTK_RTC_AL_DOW (MTK_RTC_BASE + 0x40)
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#define MTK_RTC_AL_MTH (MTK_RTC_BASE + 0x44)
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#define MTK_RTC_AL_YEA (MTK_RTC_BASE + 0x48)
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#define MTK_RTC_XOSCCALI (MTK_RTC_BASE + 0x4C)
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#define MTK_RTC_POWERKEY1 (MTK_RTC_BASE + 0x50)
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#define MTK_RTC_POWERKEY2 (MTK_RTC_BASE + 0x54)
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#define MTK_RTC_PDN1 (MTK_RTC_BASE + 0x58)
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#define MTK_RTC_PDN2 (MTK_RTC_BASE + 0x5C)
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#define MTK_RTC_SPAR1 (MTK_RTC_BASE + 0x64)
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#define MTK_RTC_DIFF (MTK_RTC_BASE + 0x6C)
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#define MTK_RTC_CALI (MTK_RTC_BASE + 0x70)
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#define MTK_RTC_WRTGR (MTK_RTC_BASE + 0x74)
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#define POWERKEY1_MAGIC 0xA357
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#define POWERKEY2_MAGIC 0x67D2
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/* RTC_BBPU bit fields definitions */
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#define RTC_BBPU_PWREN (1 << 0)
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#define RTC_BBPU_WRITE_EN (1 << 1)
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#define RTC_BBPU_BBPU (1 << 2)
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#define RTC_BBPU_AUTO (1 << 3)
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#define RTC_BBPU_CLRPKY (1 << 4)
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#define RTC_BBPU_RELOAD (1 << 5)
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#define RTC_BBPU_CBUSY (1 << 6)
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#define RTC_BBPU_DBING (1 << 7)
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#define RTC_BBPU_KEY_BBPU (1 << 8)
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/* RTC_BBPU write is only acceptable when KEY_BBPU=0x43 */
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#define BBPU_MAGIC 0x4300
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/*
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* PLL block section
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*/
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/* PLL registers definition */
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#define MTK_PLL_PLL (MTK_PLL_BASE + 0x00)
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#define MTK_PLL_PLL2 (MTK_PLL_BASE + 0x04)
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#define MTK_PLL_CLK_CON (MTK_PLL_BASE + 0x18)
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#define MTK_PLL_PDN_CON (MTK_PLL_BASE + 0x1C)
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/* MTK_PLL_PLL bit fields definitions */
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#define PLL_PLLVCOSEL (0 << 0)
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#define PLL_MPLLSEL_SYSCLK (1 << 3)
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#define PLL_MPLLSEL_PLL (2 << 3)
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#define PLL_DPLLSEL (1 << 5)
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#define PLL_UPLLSEL (1 << 6)
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#define PLL_RST (1 << 7)
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#define PLL_CALI (1 << 8)
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/* MTK_PLL_CLK_CON bit fields definitions */
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#define PLL_CLKSQ_DIV2_DSP (1 << 0)
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#define PLL_CLKSQ_DIV2_MCU (1 << 1)
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#define PLL_CLKSQ_PLD (1 << 2)
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#define PLL_SRCCLK (1 << 7)
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#define PLL_CLKSQ_TEST (1 << 15)
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/* MTK_PLL_PDN_CON bit fields definitions */
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#define PLL_PDN_CON_CLKSQ (1 << 11)
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#define PLL_PDN_CON_MCU_DIV2 (1 << 12)
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#define PLL_PDN_CON_PLL (1 << 13)
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#define PLL_PDN_CON_DSP_DIV2 (1 << 15)
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/* PMIC registry. */
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#define MTK_PMIC_CON0 0x83010800
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#define MTK_PMIC_CON1 0x83010804
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#define MTK_PMIC_CON2 0x83010808
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#define MTK_PMIC_CON3 0x8301080C
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#define MTK_PMIC_CON4 0x83010810
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#define MTK_PMIC_CON5 0x83010814
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#define MTK_PMIC_CON6 0x83010818
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#define MTK_PMIC_CON7 0x8301081C
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#define MTK_PMIC_CON8 0x83010820
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#define MTK_PMIC_CON9 0x83010824
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#define MTK_PMIC_CONA 0x83010828
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#define MTK_PMIC_CONB 0x8301082C
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#define MTK_PMIC_CONC 0x83010830
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#define MTK_PMIC_COND 0x83010834
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#define MTK_PMIC_CONE 0x83010838
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#define MTK_PMIC_CONF 0x8301083C
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#define MTK_PMIC_CONG 0x83010840
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/* MTK_PMIC_CON5 bit field definitions. */
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#define PMIC_CON5_VIBR_EN (1 << 0)
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#define PMIC_CON5_KPLED_EN (1 << 1)
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#define PMIC_CON5_RLED_EN (1 << 2)
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#define PMIC_CON5_GLED_EN (1 << 3)
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#define PMIC_CON5_BLED_EN (1 << 4)
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#define PMIC_CON5_INT_NODE_MUX (1 << 5)
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#define PMIC_CON5_VSIM_EN (1 << 8)
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#define PMIC_CON5_VSIM_SEL (1 << 9)
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#define PMIC_CON5_OVP (1 << 10)
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#define PMIC_CON5_CHRDET (1 << 11)
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#define PMIC_CON5_BAT_ON (1 << 12)
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#define PMIC_CON5_AC_DET (1 << 13)
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#define PMIC_CON5_CV (1 << 14)
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#define PMIC_CON5_CHRG_DIS (1 << 15)
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#endif
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