57 lines
1.8 KiB
C
57 lines
1.8 KiB
C
#ifndef _MTK_BFE_H
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#define _MTK_BFE_H
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/* MTK Baseband Front End */
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/* Chapter 10 of MT6235 Data Sheet */
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#define BFE_CON (MTK_BFE_BASE + 0x0000)
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#define BFE_STA (MTK_BFE_BASE + 0x0004)
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/* RX path */
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#define BFE_RX_CFG (MTK_BFE_BASE + 0x0010)
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#define BFE_RX_CON (MTK_BFE_BASE + 0x0014)
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#define BFE_RX_PM_CON (MTK_BFE_BASE + 0x0018)
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#define BFE_RX_FIR_CSID_CON (MTK_BFE_BASE + 0x001C)
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#define BFE_RX_RAM0_CS0 (MTK_BFE_BASE + 0x0070)
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#define BFE_RX_RAM1_CS0 (MTK_BFE_BASE + 0x0020)
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#define BFE_RX_HPWR_STS (MTK_BFE_BASE + 0x00B0)
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#define BFE_RX_BPWR_STS (MTK_BFE_BASE + 0x00B4)
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#define BFE_RX_RAM0_CS(n) (BFE_RX_RAM0_CS0 + 4 * n)
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#define BFE_RX_RAM1_CS(n) (BFE_RX_RAM0_CS1 + 4 * n)
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/* TX path */
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#define BFE_TX_CFG (MTK_BFE_BASE + 0x0060)
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#define BFE_TX_CON (MTK_BFE_BASE + 0x0064)
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#define BFE_TX_OFF (MTK_BFE_BASE + 0x0068)
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/* BFE_TX_CFG register fields */
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#define BFE_TX_CFG_APNDEN (1 << 0)
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#define BFE_TX_CFG_RPSEL_RAMP1 (0 << 1)
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#define BFE_TX_CFG_RPSEL_RAMP2 (1 << 1)
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#define BFE_TX_CFG_RPSEL_RAMP3 (3 << 1)
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#define BFE_TX_CFG_INTEN (1 << 3)
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#define BFE_TX_CFG_MDBYP (1 << 4)
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#define BFE_TX_CFG_SGEN (1 << 5)
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#define BFE_TX_CFG_NORMAL (0 << 6)
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#define BFE_TX_CFG_ALL0GEN (1 << 6)
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#define BFE_TX_CFG_ALL1GEN (2 << 6)
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#define BFE_TX_CFG_SW_QBCNT_SHIFT 8
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#define BFE_TX_CFG_GMSK_1TAP (0 << 13)
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#define BFE_TX_CFG_GMSK_0TAP (1 << 13)
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#define BFE_TX_CFG_GMSK_2TAP (2 << 13)
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/* BFE_TX_CON register fields */
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#define BFE_TX_CON_IQSWP (1 << 0)
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#define BFE_TX_CON_MDSEL1 (1 << 2)
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#define BFE_TX_CON_MDSEL2 (1 << 3)
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#define BFE_TX_CON_MDSEL3 (1 << 4)
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#define BFE_TX_CON_MDSEL4 (1 << 5)
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#define BFE_TX_CON_PHSEL_SHIFT 8
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#define BFE_TX_CON_GMSK_0QB (0 << 12)
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#define BFE_TX_CON_GMSK_1QB (1 << 12)
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#define BFE_TX_CON_GMSK_2QB (2 << 12)
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#define BFE_TX_CON_GMSK_3QB (3 << 12)
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#endif /* _MTK_BFE_H */
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