f62fb99941
A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. However, '*(.rodata*)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: *(.text) . = ALIGN(16); *(.rodata) *(.rodata.str1.4) *(.eh_frame) I change this to: *(.text) . = ALIGN(16); *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org> |
||
|---|---|---|
| .. | ||
| Makefile | ||
| README.txt | ||
| config.mk | ||
| flash.c | ||
| host_bridge.c | ||
| init.S | ||
| jse.c | ||
| jse_priv.h | ||
| sdram.c | ||
| u-boot.lds | ||
README.txt
JSE Configuration Details Memory Bank 0 -- Flash chip --------------------------- 0xfff00000 - 0xffffffff The flash chip is really only 512Kbytes, but the high address bit of the 1Meg region is ignored, so the flash is replicated through the region. Thus, this is consistent with a flash base address 0xfff80000. The placement at the end is to be consistent with reset behavior, where the processor itself initially uses this bus to load the branch vector and start running. On-Chip Memory -------------- 0xf4000000 - 0xf4000fff The 405GPr includes a 4K on-chip memory that can be placed however software chooses. I choose to place the memory at this address, to keep it out of the cachable areas. Memory Bank 1 -- SystemACE Controller ------------------------------------- 0xf0000000 - 0xf00fffff The SystemACE chip is along on peripheral bank CS#1. We don't need much space, but 1Meg is the smallest we can configure the chip to allocate. We need it far away from the flash region, because this region is set to be non-cached. Internal Peripherals -------------------- 0xef600300 - 0xef6008ff These are scattered various peripherals internal to the PPC405GPr chip. SDRAM ----- 0x00000000 - 0x07ffffff (128 MBytes)