185 lines
5.6 KiB
C
185 lines
5.6 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined(CONFIG_440)
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#include <ppc4xx.h>
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#include <ppc440.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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typedef struct region {
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unsigned long base;
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unsigned long size;
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unsigned long tlb_word2_i_value;
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} region_t;
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static int add_tlb_entry(unsigned long base_addr,
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unsigned long tlb_word0_size_value,
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unsigned long tlb_word2_i_value)
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{
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int i;
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unsigned long tlb_word0_value;
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unsigned long tlb_word1_value;
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unsigned long tlb_word2_value;
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/* First, find the index of a TLB entry not being used */
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for (i=0; i<PPC4XX_TLB_SIZE; i++) {
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tlb_word0_value = mftlb1(i);
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if ((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_DISABLE)
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break;
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}
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if (i >= PPC4XX_TLB_SIZE)
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return -1;
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/* Second, create the TLB entry */
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tlb_word0_value = TLB_WORD0_EPN_ENCODE(base_addr) | TLB_WORD0_V_ENABLE |
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TLB_WORD0_TS_0 | tlb_word0_size_value;
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tlb_word1_value = TLB_WORD1_RPN_ENCODE(base_addr) | TLB_WORD1_ERPN_ENCODE(0);
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tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
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TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
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TLB_WORD2_W_DISABLE | tlb_word2_i_value |
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TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
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TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
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TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
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TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
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TLB_WORD2_SR_ENABLE;
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/* Wait for all memory accesses to complete */
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sync();
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/* Third, add the TLB entries */
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mttlb1(i, tlb_word0_value);
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mttlb2(i, tlb_word1_value);
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mttlb3(i, tlb_word2_value);
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/* Execute an ISYNC instruction so that the new TLB entry takes effect */
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asm("isync");
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return 0;
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}
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static void program_tlb_addr(unsigned long base_addr, unsigned long mem_size,
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unsigned long tlb_word2_i_value)
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{
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int rc;
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int tlb_i;
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tlb_i = tlb_word2_i_value;
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while (mem_size != 0) {
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rc = 0;
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/* Add the TLB entries in to map the region. */
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if (((base_addr & TLB_256MB_ALIGN_MASK) == base_addr) &&
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(mem_size >= TLB_256MB_SIZE)) {
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/* Add a 256MB TLB entry */
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if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
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mem_size -= TLB_256MB_SIZE;
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base_addr += TLB_256MB_SIZE;
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}
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} else if (((base_addr & TLB_16MB_ALIGN_MASK) == base_addr) &&
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(mem_size >= TLB_16MB_SIZE)) {
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/* Add a 16MB TLB entry */
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if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
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mem_size -= TLB_16MB_SIZE;
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base_addr += TLB_16MB_SIZE;
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}
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} else if (((base_addr & TLB_1MB_ALIGN_MASK) == base_addr) &&
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(mem_size >= TLB_1MB_SIZE)) {
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/* Add a 1MB TLB entry */
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if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
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mem_size -= TLB_1MB_SIZE;
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base_addr += TLB_1MB_SIZE;
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}
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} else if (((base_addr & TLB_256KB_ALIGN_MASK) == base_addr) &&
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(mem_size >= TLB_256KB_SIZE)) {
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/* Add a 256KB TLB entry */
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if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
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mem_size -= TLB_256KB_SIZE;
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base_addr += TLB_256KB_SIZE;
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}
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} else if (((base_addr & TLB_64KB_ALIGN_MASK) == base_addr) &&
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(mem_size >= TLB_64KB_SIZE)) {
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/* Add a 64KB TLB entry */
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if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
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mem_size -= TLB_64KB_SIZE;
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base_addr += TLB_64KB_SIZE;
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}
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} else if (((base_addr & TLB_16KB_ALIGN_MASK) == base_addr) &&
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(mem_size >= TLB_16KB_SIZE)) {
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/* Add a 16KB TLB entry */
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if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
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mem_size -= TLB_16KB_SIZE;
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base_addr += TLB_16KB_SIZE;
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}
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} else if (((base_addr & TLB_4KB_ALIGN_MASK) == base_addr) &&
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(mem_size >= TLB_4KB_SIZE)) {
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/* Add a 4KB TLB entry */
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if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
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mem_size -= TLB_4KB_SIZE;
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base_addr += TLB_4KB_SIZE;
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}
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} else if (((base_addr & TLB_1KB_ALIGN_MASK) == base_addr) &&
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(mem_size >= TLB_1KB_SIZE)) {
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/* Add a 1KB TLB entry */
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if ((rc = add_tlb_entry(base_addr, TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
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mem_size -= TLB_1KB_SIZE;
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base_addr += TLB_1KB_SIZE;
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}
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} else {
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printf("ERROR: no TLB size exists for the base address 0x%0X.\n",
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base_addr);
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}
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if (rc != 0)
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printf("ERROR: no TLB entries available for the base addr 0x%0X.\n",
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base_addr);
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}
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return;
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}
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/*
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* Program one (or multiple) TLB entries for one memory region
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*
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* Common usage for boards with SDRAM DIMM modules to dynamically
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* configure the TLB's for the SDRAM
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*/
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void program_tlb(u32 start, u32 size)
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{
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region_t region_array;
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region_array.base = start;
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region_array.size = size;
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region_array.tlb_word2_i_value = TLB_WORD2_I_ENABLE; /* disable cache (for now) */
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/* Call the routine to add in the tlb entries for the memory regions */
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program_tlb_addr(region_array.base, region_array.size,
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region_array.tlb_word2_i_value);
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return;
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}
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#endif /* CONFIG_440 */
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