Commit Graph

8 Commits

Author SHA1 Message Date
Jean-Christophe PLAGNIOL-VILLARD 6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Stefan Roese b002144e1d ppc4xx: Fix printf format warnings now visible with the updated format check
This patch fixes ppc4xx related printf format warning. Those warnings are
now visible since patch dc4b0b38d4
[Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is
really helpful.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-10 09:58:06 +02:00
Becky Bruce 9973e3c614 Change initdram() return type to phys_size_t
This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory.  phys_size_t is defined as an unsigned long on almost
all current platforms.

This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram).  It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.

Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-12 08:50:18 +02:00
Stefan Roese cab99d6f32 ppc4xx: Fix compilation warning in denali_spd_ddr2.c
Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-29 14:44:54 +02:00
Stefan Roese 85ad184b3b ppc4xx: Complete remove bogus dflush()
Since the current dflush() implementation is know to have some problems
(as seem on lwmon5 ECC init) this patch removes it completely and replaces
it by using clean_dcache_range().

Tested on Katmai with ECC DIMM.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-29 13:57:07 +02:00
Larry Johnson eb14ebe813 ppc4xx: Add CFG_MEM_TOP_HIDE to Denali SPD-based SDRAM setup
Signed-off-by: Larry Johnson <lrj@acm.org>
2008-03-31 12:20:59 +02:00
Larry Johnson 29e3500cbc ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD code
Signed-off-by: Larry Johnson <lrj@acm.org>
2008-02-14 07:42:32 +01:00
Larry Johnson aba19604d8 Add 440EPx DDR2 SPD DIMM support
This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM
controller.  It should also work on the 440GRx.  It is based on the DDR2
SPD code for the 440EP/440EPx, but makes no provision for DDR1 support.

This code has been tested on prototype Korat boards with three Kingston
DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC
(two ranks).  The Korat board has a single DIMM socket, but support has
been provided (though not tested) for boards with two DIMM sockets.

Signed-off-by: Larry Johnson <lrj@acm.org>
2007-12-27 19:35:36 +01:00