Commit Graph

8 Commits

Author SHA1 Message Date
Wolfgang Denk d1a24f0618 Minor Coding Style Cleanup.
Signed-off-by: Wolfgang Denk <>
2011-02-02 22:36:10 +01:00
York Sun e1fd16b6f5 mpc85xx: Enable unique mode registers and dynamic ODT for DDR3
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version
(major, minor, errata) to determine if unique mode registers are available.
If true, always use unique mode registers. Dynamic ODT is enabled if needed.
The table is documented in doc/README.fsl-ddr. This function may also need
to be extend for future other platforms if such a feature exists.

Enable address parity and RCW by default for RDIMMs.

Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for
quad-rank RDIMMs.

Use a formula to calculate rodt_on for timing_cfg_5.

Signed-off-by: York Sun <>
Signed-off-by: Kumar Gala <>
2011-01-19 22:58:23 -06:00
York Sun 47df8f03f4 mpc8xxx: Enable ECC on/off control in hwconfig
Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file,
ECC can be turned on/off by this switch. If this switch is omitted, it is ON by

Updated hwconfig calls to use local buffer.

Syntax is

Signed-off-by: York Sun <>
Signed-off-by: Kumar Gala <>
2011-01-19 22:58:23 -06:00
York Sun ebbe11dd36 Add memory test feature for mpc85xx POST.
The memory test is performed after DDR initialization when U-boot stills runs
in flash and cache. On recent mpc85xx platforms, the total memory can be more
than 2GB. To cover whole memory, it needs be mapped 2GB at a time using a
sliding TLB window. After the testing, DDR is remapped with up to 2GB memory
from the lowest address as normal.

If memory test fails, DDR DIMM SPD and DDR controller registers are dumped for
further debugging.

Signed-off-by: York Sun <>
Signed-off-by: Kumar Gala <>
2010-10-20 02:28:00 -05:00
york 7fd101c97b powerpc/8xxx: Enabled address hashing for 85xx
For 85xx silicon which supports address hashing, it can be activated by

Signed-off-by: York Sun <>
2010-07-26 13:16:09 -05:00
york 076bff8f47 powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4
Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual
rank with 512MB each rank.

Also check dimm size and rank size for memory controller interleaving

Signed-off-by: York Sun <>
2010-07-26 13:16:09 -05:00
Kumar Gala 79e4e6480b powerpc/8xxx: Enabled hwconfig for memory interleaving
Replace environmental variables memctl_intlv_ctl and ba_intlv_ctl with
hwconfig parameters. The syntax is

    setenv hwconfig "fsl_ddr:ctlr_intlv=<mode>,bank_intlv=<mode>"

The mode values for memory controller interleaving are

The mode values for bank interleaving are

Signed-off-by: York Sun <>
2010-07-26 13:16:08 -05:00
Haiying Wang c9ffd839b1 Check DDR interleaving mode
* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting

Signed-off-by: Haiying Wang <>
2008-10-18 21:54:05 +02:00