Commit Graph

15 Commits

Author SHA1 Message Date
Yuri Tikhonov 46bc0a9387 Fix backlight in the lwmon5 POST.
Backlight was switched on even when temperature was too low.

Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
2008-03-18 22:24:48 +01:00
Yuri Tikhonov 0f009f781b Add support for the lwmon5 board reset via GPIO58.
Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
2008-03-18 22:24:48 +01:00
Yuri Tikhonov 8f15d4addd The patch adds new POST tests for the Lwmon5 board. These are:
* External Watchdog test;
* dsPIC tests;
* FPGA test;
* GDC test;
* Sysmon tests.

Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
2008-03-18 22:24:47 +01:00
Anatolij Gustschin d610a60730 ppc4xx: Rework Lime support for lwmon5
Rework Lime support for lwmon5 using new video driver

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-01-11 15:51:42 +01:00
Stefan Roese 54fd6c93c2 ppc4xx: lwmon5: Change PHY reset sequence for PHY MDIO address latching
Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-13 08:18:20 +01:00
Stefan Roese c25dd8fc25 ppc4xx: Add support for 2nd I2C EEPROM on lwmon5 board
This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5
board. Now the "eeprom" command can be used to read/write from/to this
device. Additionally a new command was added "eepromwp" to en-/disable
the write-protect of this 2nd EEPROM.

The 1st EEPROM is not affected by this write-protect command.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-23 11:02:37 +02:00
Stefan Roese 3ad6387873 ppc4xx: Add matrix kbd support to lwmon5 board (440EPx based)
This patch adds support for the matrix keyboard on the lwmon5 board.
Since the implementation in the dsPCI is kind of compatible with the
"old" lwmon board, most of the code is copied from the lwmon
board directory.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-21 16:27:57 +02:00
Anatolij Gustschin b66091de6c ppc4xx: lwmon5: Update Lime initialization
Change Lime SDRAM initialization to now support 100MHz and
133MHz (if enabled). Also the framebuffer is initialized to
display a blue rectangle with a white border.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-26 15:08:01 +02:00
Stefan Roese 9f24a808f1 ppc4xx: lwmon5: Support for 128 MByte NOR FLASH added
The used Intel NOR FLASH chips have internally two dies, and are now
treated as two seperate chips.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-24 09:52:52 +02:00
Stefan Roese aedf5bde17 ppc4xx: Fix lwmon5 interrupt controller setup (polarity, trigger...)
As suggested by Hakan Eryigit, here an updated setup for the lwmon5
interrupt controller.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-24 07:44:12 +02:00
Pavel Kolesnikov 531e3e8b83 POST: Add ECC POST for the lwmon5 board
This patch adds ECC Post test for the Lwmon5 board based
on PPC440EPx to U-Boot.

Signed-off-by: Pavel Kolesnikov <concord@emcraft.com>
Acked-by: Yuri Tikhonov <yur@emcraft.com>
Acked-by: Stefan Roese <sr@denx.de>
2007-07-20 15:03:03 +02:00
Stefan Roese 04e6c38b76 ppc4xx: Update lwmon5 board
- Add optional ECC generation routine to preserve existing
  RAM values. This is needed for the Linux log-buffer support
- Add optional DDR2 setup with CL=4
- GPIO50 not used anymore
- Lime register setup added

Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-04 10:06:30 +02:00
Stefan Roese 466fff1a7b ppc4xx: Add pci_pre_init() for 405 boards
This patch removes the CFG_PCI_PRE_INIT option completely, since
it's not needed anymore with the patch from Matthias Fuchs with
the "weak" pci_pre_init() implementation.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-25 15:57:39 +02:00
Wolfgang Denk 83b4cfa3d6 Coding style cleanup. Refresh CHANGELOG. 2007-06-20 18:14:24 +02:00
Stefan Roese b765ffb773 [ppc4xx] Add initial lwmon5 board support
This patch adds initial support for the Liebherr lwmon5 board euqipped
with an AMCC 440EPx PowerPC.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-15 08:18:01 +02:00