Commit Graph

17 Commits

Author SHA1 Message Date
Andy Fleming 3a79013e2a Define tsec flag values in config files
The tsec_info structure and array has a "flags" field for each
ethernet controller.  This field is the only reason there are
settings.  Switch to defining TSECn_FLAGS for each controller
in the config header, and we can greatly simplify the array, and
also simplify the addition of future boards.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-08-16 12:12:49 +02:00
Jon Loeliger 659e2f6736 include/configs/[J-O]*: Cleanup BOOTP and lingering CFG_CMD_*.
Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h
used to be included but CONFIG_BOOTP_MASK was not defined.

Remove lingering references to CFG_CMD_* symbols.

Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-10 09:10:49 -05:00
Jon Loeliger 8ea5499afd include/configs: Use new CONFIG_CMD_* in 83xx board config files.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-07-05 11:04:05 +02:00
Kim Phillips 255a3577c8 Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx
For all practical u-boot purposes, TSECs don't differ throughout the
mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-05-17 00:07:21 +02:00
Kumar Gala 4feab4de7b mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode
The config value for:
* CFG_ACR_PIPE_DEP
* CFG_ACR_RPTCNT
* CFG_SPCR_TSEC1EP
* CFG_SPCR_TSEC2EP
* CFG_SCCR_TSEC1CM
* CFG_SCCR_TSEC2CM

Were not being used when setting the appropriate register

Added:
* CFG_SCCR_USBMPHCM
* CFG_SCCR_USBDRCM
* CFG_SCCR_PCICM
* CFG_SCCR_ENCCM

To allow full config of the SCCR.

Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349
that were just bogus.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-03-02 14:08:26 -06:00
Kim Phillips 22d71a71f5 mpc83xx: add command line editing by default 2007-03-02 11:05:54 -06:00
Xie Xiaobo 8d172c0f0d mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDS
MPC8349E rev3.1 have new spridr,and PVR value,
The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM.

Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
2007-03-02 11:05:54 -06:00
Timur Tabi be5e61815d mpc83xx: Update 83xx to use fsl_i2c.c
Update the 83xx tree to use I2C support in drivers/fsl_i2c.c.  Delete
cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
Added multiple I2C bus support to fsl_i2c.c.

Signed-off-by: Timur Tabi <timur@freescale.com>
2006-11-03 19:42:23 -06:00
Timur Tabi d239d74b1c mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR
Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
tree matches the other 8xxx trees.

Signed-off-by: Timur Tabi <timur@freescale.com>
2006-11-03 19:42:23 -06:00
Kim Phillips bf0b542d67 mpc83xx: add OF_FLAT_TREE bits to 83xx boards
add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and
STDOUT_PATH configuration bits to mpc8349emds,
mpc8349itx, and mpc8360emds board code.

redo environment to use bootm with the fdtaddr
for booting ARCH=powerpc kernels by default,
and provide default fdtaddr values.
2006-11-03 19:42:22 -06:00
Ben Warren b24f119d67 Multi-bus I2C implementation of MPC834x
Hello,

Attached is a patch implementing multiple I2C buses on the MPC834x CPU
family and the MPC8349EMDS board in particular.
This patch requires Patch 1 (Add support for multiple I2C buses).
Testing was performed on a 533MHz board.

/*** Note: This patch replaces ticket DNX#2006083042000027 ***/

Signed-off-by: Ben Warren <bwarren@qstreams.com>

CHANGELOG:
        Implemented driver-level code to support two I2C buses on the
MPC834x CPU family and the MPC8349EMDS board.  Available I2C bus speeds
are 50kHz, 100kHz and 400kHz on each bus.

regards,
Ben
2006-11-03 19:42:19 -06:00
Wolfgang Denk 977b50f868 Minor cleanup. 2006-05-10 17:43:20 +02:00
Kumar Gala 8fe9bf61ef Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port:
- Removed MPC8349ADS port
  - Added PCI support to MPC8349ADS
  - reworked memory map to allow mapping of all regions with BATs
  Patch by Kumar Gala 20 Apr 2006

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2006-04-20 13:45:32 -05:00
Wolfgang Denk cf48eb9abd Some code cleanup 2006-04-16 10:51:58 +02:00
Rafal Jaworowski dc9e499c62 Support for DDR with 32-data path. Addotional notes on injecting
multiple-bit errors.
2006-03-16 17:46:46 +01:00
Marian Balakowicz d326f4a242 Add command for handling DDR ECC registers on MPC8349EE MDS board. 2006-03-16 15:19:35 +01:00
Marian Balakowicz 991425fe05 Add initial support for MPC8349E MDS board. 2006-03-14 16:24:38 +01:00