Commit Graph

109 Commits

Author SHA1 Message Date
Magnus Lilja d08e5ca301 MX31: Add NAND SPL boot support to i.MX31 PDK board.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2009-07-06 21:53:18 +02:00
Magnus Lilja 40c642bc19 MX31: Add NAND SPL for i.MX31.
This patch adds the NAND SPL framework needed to boot i.MX31 boards
from NAND.

It has been tested on a i.MX31 PDK board with large page NAND. Small
page NANDs should work as well, but this has not been tested.

Note: The i.MX31 NFC uses a non-standard layout for large page NANDs,
whether this is compatible with a particular setup depends on how
the NAND device is programmed by the flash programmer (e.g. JTAG
debugger).

The patch is based on the work by Maxim Artamonov.

Signed-off-by: Maxim Artamonov <scn1874@yandex.ru>
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2009-06-21 16:18:12 +02:00
Detlev Zundel 792a09eb9d Fix e-mail address of Gary Jennejohn.
Signed-off-by: Detlev Zundel <dzu@denx.de>
2009-05-15 22:11:59 +02:00
Trent Piepho f62fb99941 Fix all linker script to handle all rodata sections
A recent gcc added a new unaligned rodata section called '.rodata.str1.1',
which needs to be added the the linker script.  Instead of just adding this
one section, we use a wildcard ".rodata*" to get all rodata linker section
gcc has now and might add in the future.

However, '*(.rodata*)' by itself will result in sub-optimal section
ordering.  The sections will be sorted by object file, which causes extra
padding between the unaligned rodata.str.1.1 of one object file and the
aligned rodata of the next object file.  This is easy to fix by using the
SORT_BY_ALIGNMENT command.

This patch has not be tested one most of the boards modified.  Some boards
have a linker script that looks something like this:

*(.text)
. = ALIGN(16);
*(.rodata)
*(.rodata.str1.4)
*(.eh_frame)

I change this to:

*(.text)
. = ALIGN(16);
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))

This means the start of rodata will no longer be 16 bytes aligned.
However, the boundary between text and rodata/eh_frame is still aligned to
16 bytes, which is what I think the real purpose of the ALIGN call is.

Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
2009-03-20 22:39:12 +01:00
Wolfgang Denk 4b00d1aa82 SIMPC8313 board: fix out of tree building.
Fix typo in makefile which broke out of tree builds.

Also use expolicit "rm" instead of "ln -sf" which is known to be
unreliable.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-03-09 10:51:39 +01:00
Wolfgang Denk c1b7c70083 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2009-01-28 23:14:22 +01:00
Kim Phillips 2b6fd5c77d mpc83xx: fix undefined reference to `flush_cache' error in simpc8313 build
extend commit c70564e6b1
"NAND: Fix cache and memory inconsistency issue" to add the cache.o dependency
to the simpc8313 build and fix this:

...Large Page NAND...Configuring for SIMPC8313 board...
nand_boot_fsl_elbc.o: In function `nand_boot':
nand_spl/board/sheldon/simpc8313/nand_boot_fsl_elbc.c:150: undefined reference to `flush_cache'
make[1]: *** [/home/r1aaha/git/u-boot-mpc83xx/nand_spl/u-boot-spl] Error 1
make: *** [nand_spl] Error 2

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-28 10:00:56 +01:00
Stefan Roese de832a9941 nand_spl: Fix compile problem with board_nand_init() prototype
This patch removes the now obsolete and additionally wrongly defined
board_nand_init() prototype from nand_spl/nand_boot.c.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-26 13:39:17 -06:00
Kim Phillips 833d94bcdc Merge branch 'next' 2009-01-23 17:48:24 -06:00
Ron Madrid 5bb907a492 mpc83xx: New board support for SIMPC8313
This patch will create a new board, SIMPC8313, from Sheldon Instruments.  This
board boots from NAND devices and is configureable for either large or small
page devices.  The board supports non-soldered DDR2, one ethernet port, a
Marvell 88E1118 PHY, and PCI host support.  The board also has a FPGA connected
to the eLBC providing glue logic to a TMS320C67xx DSP.

Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-01-23 11:31:18 -06:00
Dave Liu c70564e6b1 NAND: Fix cache and memory inconsistency issue
We load the secondary stage u-boot image from NAND to
system memory by nand_load, but we did not flush d-cache
to memory, nor invalidate i-cache before we jump to RAM.
When the system has cache enabled and the TLB/page attribute
of system memory is cacheable, it will cause issues.

- 83xx family is using the d-cache lock, so all of d-cache
  access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial
  cache lock. you will see the issue.

This patch fixes the cache issue.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-01-23 10:32:50 -06:00
Selvamuthukumar 9b827cf172 Align end of bss by 4 bytes
Most of the bss initialization loop increments 4 bytes
at a time. And the loop end is checked for an 'equal'
condition. Make the bss end address aligned by 4, so
that the loop will end as expected.

Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-11-18 23:13:16 +01:00
Haiying Wang 4e190b03aa Make Freescale local bus registers available for both 83xx and 85xx.
- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
  can be shared by both 83xx and 85xx
- Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
  files which use lbus83xx_t.
- Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
  85xx can share them.

Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-10-29 11:12:53 -05:00
Jean-Christophe PLAGNIOL-VILLARD 6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Guennadi Liakhovetski 11edcfe260 ARM: Add support for S3C6400 based SMDK6400 board
SMDK6400 can only boot U-Boot from NAND-flash. This patch adds a nand_spl
driver for it too. The board can also boot from the NOR flash, but due to
hardware limitations it can only address 64KiB on it, which is not enough
for U-Boot. Based on the original sources by Samsung for U-Boot 1.1.6.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
2008-08-31 00:39:47 +02:00
Scott Wood 8d765456c1 NAND: Remove delay from nand_boot_fsl_elbc.c.
It was for debugging purposes, and shouldn't have been left in.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-08-21 13:44:17 -05:00
Wolfgang Denk 4b0708093e Coding Style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-08-14 14:41:06 +02:00
Guennadi Liakhovetski aa646643b6 nand_spl: Support page-aligned read in nand_load, use chipselect
Supporting page-aligned reads doesn't incure any sinificant overhead, just
a small change in the algorithm. Also replace in_8 with readb, since there
is no in_8 on ARM.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-08-12 11:31:32 -05:00
Scott Wood 4f32d7760a NAND boot: Update large page support for current API.
Also, remove the ctrl variable in favor of passing the constants
directly, and remove redundant (u8) casts.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-08-12 11:31:31 -05:00
Scott Wood e4c0950854 NAND boot: MPC8313ERDB support
Note that with older board revisions, NAND boot may only work after a
power-on reset, and not after a warm reset.  I don't have a newer board
to test on; if you have a board with a 33MHz crystal, please let me know
if it works after a warm reset.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-08-12 11:31:31 -05:00
Stefan Roese c568f77acd NAND: Update nand_spl driver to match updated nand subsystem
This patch changes the NAND booting driver nand_spl/nand_boot.c to match
the new infrastructure from the updated NAND subsystem. This NAND
subsystem was recently synced again with the Linux 2.6.22 MTD/NAND
subsystem.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-12 11:31:23 -05:00
Scott Wood 2dacb734ba NAND: $(obj)-qualify ecc.h in kilauea NAND boot Makefile.
This fixes building out-of-tree.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-07-30 00:37:08 +02:00
Becky Bruce 9973e3c614 Change initdram() return type to phys_size_t
This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory.  phys_size_t is defined as an unsigned long on almost
all current platforms.

This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram).  It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.

Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-12 08:50:18 +02:00
Stefan Roese 63a0afa0c3 ppc4xx: Fix problem with SDRAM init in bamboo NAND booting port
This patch fixes a problem spotted by Eugene O'Brian (thanks Eugene)
introduced by the commit:

ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S

With this patch SDRAM will get initialized again and booting from NAND
is working again.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
2008-06-04 21:34:12 +02:00
Kenneth Johansson 2918eb9d42 Remove shell variable UNDEF_SYM.
UNDEF_SYM is a shell variable in the main Makefile used to force the
linker to add all u-boot commands to the final image. It has no use here.

Signed-off-by: Kenneth Johansson <kenneth@southpole.se>
2008-06-03 20:36:18 +02:00
Stefan Roese ec724f883e ppc4xx: Change Kilauea to use the common DDR2 init function
This patch changes the kilauea and kilauea_nand (for NAND booting)
board port to not use a board specific DDR2 init routine anymore. Now
the common code from cpu/ppc4xx is used.

Thanks to Grant Erickson for all his basic work on this 405EX early
bootup.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-03 20:22:03 +02:00
Stefan Roese 64852d09e0 ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S
This patch consolidates the 405 and 440 parts of the NAND booting code
selected via CONFIG_NAND_SPL. Now common code is used to initialize the
SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc.
Only *after* running from this location, nand_boot() is called.

Please note that the initsdram() call is now moved from nand_boot.c
to start.S. I experienced problems with some boards like Kilauea
(405EX), which don't have internal SRAM (OCM) and relocation needs to
be done to SDRAM before the NAND controller can get accessed. When
initdram() is called later on in nand_boot(), this can lead to problems
with variables in the bss sections like nand_ecc_pos[].

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
2008-06-03 20:21:49 +02:00
Stefan Roese fdd1247a66 ppc4xx: Individual handling of ddr2_fixed.c for canyonlands_nand build
Canyonlands has a file ddr2_fixed.c which needs special treatment when
building in separate directory. It has to be linked to build directory
otherwise it is not seen.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-05-14 12:26:16 +02:00
Stefan Roese 4f27098e5b ppc4xx: Adapt Canyonlands fixed DDR2 setup to new DIMM module
This patch changes the Canyonlands/Glacier fixed DDR2 controller setup
used for NAND booting to match the values needed for the new 512MB
DIMM modules shipped with the productions boards:

Crucial: CT6464AC667.8FB

Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-30 14:51:36 +02:00
Wolfgang Denk 926662762e Merge branch 'master' of git://www.denx.de/git/u-boot-nand-flash 2008-04-25 11:10:17 +02:00
Stefan Roese 499e7831e1 ppc4xx: Change Canyonlands to support booting from 2k page NAND devices
Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-18 16:30:49 +02:00
Stefan Roese 5e182dce04 ppc4xx: Adjust Canyonlands fixed DDR2 setup (NAND booting) to 512MB SODIMM
Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-18 16:30:39 +02:00
Stefan Roese 46f373838e nand_spl: Update nand_spl to support 2k page size NAND devices
This patch adds support for booting from 2k page sized NAND device
(e.g. Micron 29F2G08AAC).

Tested on AMCC Canyonlands.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-18 16:12:46 +02:00
Stefan Roese 71665ebf88 ppc4xx: Add Canyonlands NAND booting support
460EX doesn't support a fixed bootstrap option to boot from 512 byte page
NAND devices. The only bootstrap option for NAND booting is option F for
2k page devices. So to boot from a 512 bype page device, the I2C bootstrap
EEPROM needs to be programmed accordingly.

This patch adds basic NAND booting support for the AMCC Canyonlands aval
board and also adds support to the "bootstrap" command, to enable NAND
booting I2C setting.

Tested with 512 byte page NAND device (32MByte) on Canyonlands.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:05 +01:00
Wolfgang Denk 64134f0112 Fix linker scripts: add NOLOAD atribute to .bss/.sbss sections
With recent toolchain versions, some boards would not build because
or errors like this one (here for ocotea board when building with
ELDK 4.2 beta):
ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab]

For many boards, the .bss section is big enough that it wraps around
at the end of the address space (0xFFFFFFFF), so the problem will not
be visible unless you use a 64 bit tool chain for development. On
some boards however, changes to the code size (due to different
optimizations) we bail out with section overlaps like above.

The fix is to add the NOLOAD attribute to the .bss and .sbss
sections, telling the linker that .bss does not consume any space in
the image.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-01-12 20:31:39 +01:00
Marcel Ziswiler 10c7382bc5 fix various comments
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2008-01-09 21:50:47 +01:00
Marcel Ziswiler 7817cb2083 fix comments with new drivers organization
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2008-01-09 21:48:49 +01:00
Stefan Roese fe9c26b330 ppc4xx: Fix Sequoia NAND booting target
The Sequoia NAND booting target now uses the recently extracted
cpu/ppc4xx/denali_data_eye.c file too.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-04 12:00:01 +01:00
Stefan Roese fb83a65c60 ppc4xx: Fix compilation problem of kilauea/haleakala nand booting target
Use correct link to nand_ecc now located in drivers/mtd/nand/ for the
platforms mentioned above.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-28 06:06:04 +01:00
Stefan Roese 9caeaadf50 Merge commit 'u-boot/master' into for-1.3.1
Conflicts:

	drivers/rtc/Makefile
2007-12-11 11:34:54 +01:00
Jean-Christophe PLAGNIOL-VILLARD 59829cc189 drivers/mtd : move mtd drivers to drivers/mtd
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2007-11-25 23:28:52 +01:00
Stefan Roese 3d6cb3b24a ppc4xx: Add AMCC Kilauea/Haleakala NAND booting support
This patch adds NAND booting support for the AMCC 405EX(r) eval boards.
Again, only one image supports both targets.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-03 12:08:28 +01:00
Stefan Roese 5d96d40d3f ppc4xx: Fix acadia_nand build problem
Since the cache handling functions were moved from start.S into cache.S
the acadia NAND booting Makfile needs to be adapted accordingly.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Eugene O'Brien 9f798766aa ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAM
This patch also adds a note to the fixed DDR setup for Bamboo NAND booting:

Note:
As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
modules are still plugged in. So it is recommended to remove the DIMM
modules while using the NAND booting code with the fixed SDRAM setup!

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Grzegorz Bernacki 6c2f4f388e [ppc4xx] Individual handling of sdram.c for bamboo_nand build
Bamboo has a file sdram.c which needs special treatment when building in
separate directory. It has to be linked to build directory otherwise it is
not seen.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-09-11 12:57:52 +02:00
Stefan Roese df8a24cdd3 [ppc4xx] Fix problem with NAND booting on AMCC Acadia
The latest changes showed a problem with the location of the NAND-SPL
image in the OCM and the init-data area (incl. cache). This patch
fixes this problem.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-19 16:42:31 +02:00
Stefan Roese c440bfe6d6 ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board
This patch adds NAND booting support for the AMCC Acadia eval board.

Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.

I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:

=> bootstrap 267 nor	;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand	;to configure the board for 267MHz NNAND booting

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-06 11:42:13 +02:00
Stefan Roese f3679aa13d Merge with /home/stefan/git/u-boot/bamboo-nand 2007-06-01 16:15:34 +02:00
Stefan Roese 9d9096043e ppc4xx: Update Sequoia NAND booting support with ECC
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01 15:29:04 +02:00
Stefan Roese cf959c7d66 ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval board
This patch adds NAND booting support for the AMCC Bamboo eval board.
Since the NAND-SPL boot image is limited to 4kbytes, this version
only supports the onboard 64MBytes of DDR. The DIMM modules can't be
supported, since the setup code for I2C DIMM autodetection and
configuration is too big for this NAND bootloader.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01 15:27:11 +02:00
Stefan Roese 42be56f53c NAND: Add ECC support to NAND booting support in nand_spl/nand_boot.c
The U-Boot NAND booting support is now extended to support ECC
upon loading of the NAND U-Boot image.

Tested on AMCC Sequoia (440EPx) and Bamboo (440EP).

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01 15:23:04 +02:00
Stefan Roese f544ff6656 ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND booting
Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
for the 4k NAND boot image so define bus_frequency to 133MHz here
which is save for the refresh counter setup.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-05-05 08:29:01 +02:00
Stefan Roese 07b7b0037a [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setup
As provided by the AMCC applications team, this patch optimizes the
DDR2 setup for 166MHz bus speed. The values provided are also save
to use on a "normal" 133MHz PLB bus system. Only the refresh counter
setup has to be adjusted as done in this patch.

For this the NAND booting version had to include the "speed.c" file
from the cpu/ppc4xx directory. With this addition the NAND SPL image
will just fit into the 4kbytes of program space. gcc version 4.x as
provided with ELDK 4.x is needed to generate this optimized code.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-06 07:47:04 +01:00
Stefan Roese 0238898382 [PATCH] Add DDR2 optimization code for Sequoia (440EPx) board
This code will optimize the DDR2 controller setup on a board specific
basis.

Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-05 10:38:05 +01:00
Marian Balakowicz 8318fbf8cc Fix sequoia separate object direcory building problems. 2006-10-23 22:17:05 +02:00
Wolfgang Denk 511d0c72b8 Coding style cleanup 2006-10-09 00:42:01 +02:00
Stefan Roese d12ae80889 Add NAND environment support for PPC440EPx Sequoia NAND boot config
Patch by Stefan Roese, 12 Sep 2006
2006-09-12 20:19:10 +02:00
Stefan Roese a73c8dbb43 Update NAND boot documentation
Patch by Stefan Roese, 12 Sep 2006
2006-09-12 08:49:07 +02:00
Stefan Roese 887e2ec9ec Add support for AMCC Sequoia PPC440EPx eval board
- Add support for PPC440EPx & PPC440GRx
- Add support for PPC440EP(x)/GR(x) NAND controller
  in cpu/ppc4xx directory
- Add NAND boot functionality for Sequoia board,
  please see doc/README.nand-boot-ppc440 for details
- This Sequoia NAND image doesn't support environment
  in NAND for now. This will be added in a short while.
Patch by Stefan Roese, 07 Sep 2006
2006-09-07 11:51:23 +02:00