Commit Graph

57 Commits

Author SHA1 Message Date
Thomas Chou df8f125261 altera_spi: add spi_set_speed
Added this for mmc_spi driver. Though altera spi core does not
support programmable speed. It is fixed when configured in
sopc-builder.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2011-02-08 08:29:53 -05:00
Wolfgang Denk 4bfa18fb99 Merge branch 'master' of git://git.denx.de/u-boot-sh 2011-02-04 20:38:27 +01:00
Yoshihiro Shimoda 6639562e6a spi: add support SuperH SPI module
SH7757 has SPI module. This patch supports it.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2011-02-02 16:38:41 +09:00
Stefano Babic ac87c17d34 SPI: mxc_spi: replace fixed offsets with structures
This patch cleans driver code replacing all accesses
to registers with fixed offsets with a corresponding
structure.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-02-02 00:54:43 +01:00
Anatolij Gustschin afaa9f65c2 SPI: mxc_spi: add SPI clock calculation and setup to the driver
The MXC SPI driver didn't calculate the SPI clock up to
now and just used highest possible divider 512 for DATA
RATE in the control register. This results in very low
transfer rates.

The patch adds code to calculate and setup the SPI clock
frequency for transfers.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-02-02 00:54:43 +01:00
Anatolij Gustschin dff0109496 SPI: mxc_spi: fix swapping bug and add missing swapping in unaligned rx case
We need to shift only one time in each cycle in the swapping loop
for unaligned tx case. Currently two byte shift operations are
performed in each loop cycle causing zero gaps in the transmited
data, so not all data scheduled for transmition is actually
transmited.

The proper swapping in unaligned rx case is missing, so add it
as we need to put the received data into the rx buffer in the
correct byte order.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
2011-02-02 00:54:43 +01:00
Stefano Babic c9d59c7fbe SPI: mxc_spi: add support for i.MX35 processor
Signed-off-by: Stefano Babic <sbabic@denx.de>
2011-02-02 00:54:43 +01:00
Dirk Behme 53736baaff OMAP3: SPI driver
CC: Ruslan N. Araslanov <byaaka@yandex.ru>
Signed-off-by: Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-12-11 11:01:00 -05:00
Sebastien Carlier 6d8962e814 Switch from archive libraries to partial linking
Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils.  As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".

This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.

The name of each former library archive is preserved except for
extensions which change from ".a" to ".o".  This commit updates
references accordingly where needed, in particular in some linker
scripts.

This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols.  Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.

Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
2010-11-17 21:02:18 +01:00
Wolfgang Denk e67f462864 Merge branch 'master' of git://git.denx.de/u-boot-imx 2010-10-11 10:19:04 +02:00
Mike Frysinger 6f070e1867 Blackfin: bfin_spi: add optional DMA support
This moves the last piece from the old spi_flash driver to the new SPI
framework -- optional DMA RX support.  This typically cuts speeds by ~40%
at the cost of additional ~300 bytes.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-10-02 16:00:36 -04:00
Stefano Babic 2f721d1733 MXC: Fix byte-ordering in SPI driver for i.MX31/i.MX51
The actual SPI driver for i.MX31 and i.MX51 controller
use a wrong byte ordering, because it is supposed
to work only with Freescale's devices, as the Power
Controllers (PMIC). The driver is not suitable for
general purposes, because the buffers passed to spi_xfer
must be 32-bit aligned, as it is used mainly to send
integer to PMIC devices.

The patch drops any kind of limitation and makes the
driver useful with devices controlled sending commands
composed by single bytes (or by a odd number of bytes), such as
spi flash, sensor, etc.

Because the byte ordering is changed,
any current driver using this controller must be adapted, too.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-09-30 14:42:14 +02:00
Stefano Babic 9f481e95ba MXC: Correct SPI_CPOL setting in SPI driver
The handling of the SPI_CPOL bit inside the SPI
driver was wrong. As reported by the manual,
the meaning of the SSPOL inside the
configuration register is the same as reported
by SPI specification (0 if low in idle, 1 is high
on idle). The driver inverts this logic.

Because this patch sets the logic as specified, it is required
to clear the CPOL bit in the configuration file to adapt
to the correct logic.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: David Jander <david.jander@protonic.nl>
2010-09-30 14:42:13 +02:00
Stefano Babic c4ea142424 Use common function to set GPIOs for MX3 and MX5
The patch adds support for setting gpios to the
MX51 processor and change name to the corresponding
functions for MX31. In this way, it is possible to get rid
of nasty #ifdef switches related to the processor type.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-09-29 11:24:30 +02:00
Mike Frysinger 55fed6fd0b Blackfin: bfin_spi: use same gpio cs define as Linux
Linux uses an offset of 8 to switch from hardware cs to a gpio cs,
so have u-boot use the same value.  Also make sure it is public
for boards to access.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-21 18:22:14 -04:00
Reinhard Meyer f09d3b2896 AT91/AVR32: atmel_spi.c: flush RDR before next SPI transaction
Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
2010-09-03 11:22:25 +02:00
Wolfgang Denk 93502a5e0a Merge branch 'master' of ../master 2010-07-15 22:48:46 +02:00
Mike Frysinger 37a4b75d4c Blackfin: bfin_spi: support gpios as chip selects
Rather than only support the pins dedicated as chip selects, utilize the
gpio framework to support any gpio pin.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-13 17:50:50 -04:00
Mike Frysinger f3732edf46 Blackfin: bfin_spi: convert to portmux framework
Rather than bang MMRs directly, use the new portmux framework to handle
the details.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-07-13 17:50:50 -04:00
Nick Thompson dce6538f5d Davinci: SPI: add the missing v2 patch changes
Two Indentation fixes.

Catch requests for full-duplex transfers when driver configured for
half-duplex operation only.

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-07-05 20:00:40 -04:00
Nick Thompson 77436d6696 Davinci: SPI performance enhancements
The following restructuring and optimisations increase the SPI
read performance from 1.3MiB/s (on da850) to 2.87MiB/s (on da830):

Remove continual revaluation of driver state from the core of the
copy loop. State can not change during the copy loop, so it is
possible to move these evaluations to before the copy loop.

Cost is more code space as loop variants are required for each set
of possible configurations. The loops are simpler however, so the
extra is only 128bytes on da830 with CONFIG_SPI_HALF_DUPLEX
defined.

Unrolling the first copy loop iteration allows the TX buffer to be
pre-loaded reducing SPI clock starvation.

Unrolling the last copy loop iteration removes testing for the
final loop iteration every time round the loop.

Using the RX buffer empty flag as a transfer throttle allows the
assumption that it is always safe to write to the TX buffer, so
polling of TX buffer full flag can be removed.

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-22 11:06:01 -04:00
Wolfgang Denk 399b09331f Merge branch 'master' of git://git.denx.de/u-boot-arm 2010-06-17 21:06:16 +02:00
Delio Brignoli 9268236529 DaVinci: Improve DaVinci SPI speed.
I have updated this patch based on the comments [1] by Wolfgang Denk and
removed unused variables.
[1][http://lists.denx.de/pipermail/u-boot/2010-May/071728.html]

Reduce the number of reads per byte transferred on the BUF register from 2 to 1 and
take advantage of the TX buffer in the SPI module. On LogicPD OMAP-L138 EVM,
SPI read throughput goes up from ~0.8Mbyte/s to ~1.3Mbyte/s. Tested with a 2Mbyte image file.
Remove unused variables in the spi_xfer() function.

Signed-off-by: Delio Brignoli <dbrignoli@audioscience.com>
Tested-by: Ben Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-06-08 10:07:19 -05:00
Thomas Chou 661ba14051 spi: add altera spi controller support
This patch adds the driver of altera spi controller, which is
used as epcs/spi flash controller. It also works with mmc_spi
driver.

This driver support more than one spi bus, with base list declared
#define CONFIG_SYS_ALTERA_SPI_LIST { BASE_0,BASE_1,... }

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Tested-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2010-05-28 10:56:03 -04:00
Stefano Babic d205ddcfc5 SPI: added support for MX51 to mxc_spi
This patch add SPI support for the MX51 processor.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-05-05 09:48:41 +02:00
Stefan Roese a47a12becf Move arch/ppc to arch/powerpc
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.

Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
2010-04-21 23:42:38 +02:00
Peter Tyser 8d1f268204 ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2010-04-13 09:13:16 +02:00
Wolfgang Denk 93910edb59 Prepare v2010.03-rc1
Coding style cleanup, update CHANGELOG.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2010-03-12 23:06:04 +01:00
Jens Scharsig 0cf0b93161 convert common files to new SoC access
* add's a warning to all files, which need update to new SoC access
 * convert common files in cpu/../at91 and a lot of drivers to use
   c stucture SoC access

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
2010-02-12 12:31:55 -06:00
Magnus Lilja eff536befd SPI: Fix 32 bit transfers in mxc_spi.c
Commit f9b6a1575d,  "i.MX31: fix SPI
driver for shorter than 32 bit" broke 32 bit transfers. This patch
makes single 32 bit transfer work again.

Transfer lengths that are known not to work will abort and print
an error message.

Tested on i.MX31 Litekit and i.MX31 PDK using 32 bit transfers to
the MC13783/ATLAS chip (using the 'date' command).

Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
2010-02-12 12:31:54 -06:00
Sekhar Nori 8ed5885693 TI DaVinci: Driver for the davinci SPI controller
This adds a driver for the SPI controller found on davinci
based SoCs from Texas Instruments.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2010-02-12 12:31:53 -06:00
Cliff Cai 581d92eefc Blackfin: bfin_spi: round up clock divider
If the requested clock cannot be exactly obtained, round it up so that we
err on the side of slightly slower rather than slightly faster.

Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Cliff Cai 17ebd5bf33 Blackfin: bfin_spi: let boards control idle value
Some SPI devices like to see high idle values rather than low.

Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-01-17 09:17:27 -05:00
Remy Bohmer 41dfd8a603 Add support for CS2 dataflash for Atmel-SPI.
The only missing chipselect line support is CS2, and I need it on
CS2...

Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-11-23 23:43:37 +01:00
TsiChung Liew dec61c7851 Coldfire: Consolidate DSPI driver
Unify both MCF5227x and MCF5445x DSPI driver in CPU to
driver/spi folder for common use.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
2009-07-14 09:46:09 -05:00
Wolfgang Denk a48ecc969f Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
	drivers/spi/Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-07-07 22:22:05 +02:00
Prafulla Wadaskar 5710de4580 spi: Add Marvell Kirkwood SPI driver
This patch adds a SPI driver for the Marvell Kirkwood SoC's.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2009-06-26 00:59:09 +02:00
Grzegorz Bernacki 6325b7780d mpc52xx: Add SPI driver.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2009-06-14 23:01:38 +02:00
Mike Frysinger 7d6900ebe1 Blackfin: spi: fix pin handling of SPI0 SSEL4
CS4 on SPI0 has a dedicated PH8 pin which needs to be enabled as a
peripheral in order to work.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-05-29 17:11:33 -04:00
Jean-Christophe PLAGNIOL-VILLARD dc39ae9513 at91sam9/at91cap: improve clock framework
calculate dynamically the clock rate and pllb setting for usb

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-04-16 21:30:44 +02:00
Todor I Mollov d04371a116 Blackfin: spi: make cs deassert function deterministic
Blackfin SPI driver was not driving the SPI chip-select high before
putting the chip-select signals into tri-state mode.  This is probably
something that slipped by unnoticed in most designs.  If the signals are
put directly into a tri-state mode, then the board is relying on the
pull-up resistors to pull up the chip-select before the next transaction.
Most of the time this is fine, except when you have two transactions that
follow each other very closely, such as the flash erase and read status
register commands.  In this case I was seeing a 500ns separation between
the transactions.  In my setup, with a 10kOhm pull-up, it would meet
timing spec about half the time and resulted in intermittent errors.  (A
stronger pull up would fix this, but our design is targeted for low power
consumption and a 3.3kOhm @ 3.3v is 3.3mW of needless power consumption.)
I modified the spi_cs_deactivate() function in bfin_spi.c to drive the
chip-selects high before putting them into tri-state.  For me, this
resulted in a rise time of 5ns instead of the previous rise time of about
1us, and fully satisfied the timing spec of the chip.

Signed-off-by: Todor I Mollov <tmollov@ucsd.edu>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-04-06 03:49:31 -04:00
Jean-Christophe PLAGNIOL-VILLARD 4758ebdd53 at91: move dataflash spi driver to drivers/spi
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-04-04 20:42:22 +02:00
Mike Frysinger bc72f50a65 Blackfin: add BF538/BF539 SPI portmux handling
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-04-02 06:42:18 -04:00
Sonic Zhang 974473caa7 Blackfin: spi: there is no PORTJ_FER MMR on BF537
Since the PORTJ on the BF537 is peripheral-only (no GPIO functionality),
then there is no PORTJ_FER register for us to worry about.

Signed-off-by: Sonic Zhang <Sonic.Zhang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-03-23 15:14:52 -04:00
Guennadi Liakhovetski fc7a93c84f i.MX31: support GPIO as a chip-select in the mxc_spi driver
Some SPI devices have special requirements on chip-select handling.
With this patch we can use a GPIO as a chip-select and strictly follow
the SPI_XFER_BEGIN and SPI_XFER_END flags.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-02-24 09:48:33 +01:00
Guennadi Liakhovetski f9b6a1575d i.MX31: fix SPI driver for shorter than 32 bit
Fix setting the SPI Control register, 8 and 16-bit transfers
and a wrong pointer in the free routine in the mxc_spi driver.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-02-24 09:39:44 +01:00
Mike Frysinger 400f5778f3 Blackfin: add driver for on-chip SPI controller
This fills out the SPI backend for the Blackfin on-chip SPI peripheral.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-02-02 12:24:30 -05:00
Jean-Christophe PLAGNIOL-VILLARD 6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Jean-Christophe PLAGNIOL-VILLARD e831403599 soft_spi: move to drivers/spi
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-08-29 12:25:02 +02:00
Ben Warren f8cc312bbe Move conditional compilation of MPC8XXX SPI driver to Makefile
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-07-01 21:02:11 +02:00