Commit Graph

5 Commits

Author SHA1 Message Date
Mike Frysinger 8ef583a035 miiphy: convert to linux/mii.h
The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-01-09 18:06:50 +01:00
Prafulla Wadaskar 32e7f239dd net: phy: mv88e61xx.c : fixed build warning
following build warning was observed

mv88e61xx.c: In function ‘mv88e61xx_busychk’:
mv88e61xx.c:208: warning: dereferencing type-punned pointer will break strict-aliasing rules

This patch fixes the same
Patch tested for rd6281a board build

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-10-04 22:30:46 -07:00
Prafulla Wadaskar 08c2df33f1 net: phy: bugfixes: mv88E61xx compiler warnings fixed
1. mv88E61xx driver compiler warnings fixed
2. idstr if-else statements changed to switch() construct
   and added default case too.
   This fixed idstr may be uninitialized warning

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-10 14:53:52 -07:00
Prafulla Wadaskar 443ce4ac9d net: phy: bugfixes: mv88E61xx multichip addressing support
With these fixes, this driver works properly for multi chip
addressging mode

Bugfixes:
1. Build error fixed for function mv88e61xx_busychk_multic-fixed
2. PHY dev address error detection- fixed
3. wrong busy bit was refered in function mv88e61xx_busychk -fixed
4. invalid data read ptr was refered for RD_PHY in case of
	multichip addressing mode -fixed

The Multichip Address mode is tested with RD6281A board having
MV88E6165 switch on it

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-07-22 22:53:45 -07:00
Prafulla Wadaskar 6f51deb7f2 Marvell MV88E61XX Switch Driver support
Chips supported:-
1. 88E6161 6 port gbe swtich with 5 integrated PHYs
2. 88E6165 6 port gbe swtich with 5 integrated PHYs
2. 88E6132 3 port gbe swtich with 2 integrated PHYs
Platform specific configuration supported for:-
default or router port vlan configuration
led_init configuration
mdip/n polarity reversal configuration

Note: This driver is supported and tested against
kirkwood egiga interface

Contributors:
Yotam Admon <yotam@marvell.com>
Michael Blostein <michaelbl@marvell.com

Reviewed by: Ronen Shitrit <rshitrit@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-06-15 00:13:54 -07:00