ppc/85xx: Fix misc L2 cache enabling bug
We need loop-check the flash clear lock and enable bit for L2 cache. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -102,18 +102,22 @@ __secondary_start_page:
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#ifdef CONFIG_BACKSIDE_L2_CACHE
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#ifdef CONFIG_BACKSIDE_L2_CACHE
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/* Enable/invalidate the L2 cache */
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/* Enable/invalidate the L2 cache */
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msync
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msync
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lis r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
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lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
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ori r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
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ori r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
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mtspr SPRN_L2CSR0,r3
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mtspr SPRN_L2CSR0,r2
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1:
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1:
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mfspr r3,SPRN_L2CSR0
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mfspr r3,SPRN_L2CSR0
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andis. r1,r3,L2CSR0_L2FI@h
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and. r1,r3,r2
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bne 1b
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bne 1b
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lis r3,CONFIG_SYS_INIT_L2CSR0@h
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lis r3,CONFIG_SYS_INIT_L2CSR0@h
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ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
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ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
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mtspr SPRN_L2CSR0,r3
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mtspr SPRN_L2CSR0,r3
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isync
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isync
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2:
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mfspr r3,SPRN_L2CSR0
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andis. r1,r3,L2CSR0_L2E@h
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beq 2b
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#endif
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#endif
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#define EPAPR_MAGIC (0x45504150)
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#define EPAPR_MAGIC (0x45504150)
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