SDRAM now working for delta board, but there are still aliasing problems,
we only see 64MB.
This commit is contained in:
Markus Klotzbcher
Markus Klotzbcher
parent
48b6242aa1
commit
ff3c2a9478
1
Makefile
1
Makefile
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@ -1838,6 +1838,7 @@ clean:
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rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image
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rm -f board/trab/trab_fkt board/voiceblue/eeprom
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rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds
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rm -f u-boot.objdump-*
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clobber: clean
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find . -type f \( -name .depend \
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@ -1,4 +1,5 @@
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#TEXT_BASE = 0x0
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#TEXT_BASE = 0xa1700000
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#TEXT_BASE = 0xa3080000
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TEXT_BASE = 0xa3008000
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#TEXT_BASE = 0xa3008000
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TEXT_BASE = 0x9ffe0000
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@ -49,20 +49,6 @@ DRAM_SIZE: .long CFG_DRAM_SIZE
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bls 0b
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.endm
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#define SDRAM_CMD_NOP 0x40000000
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.macro do_nop_cmd num
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ldr r2, =MDMRS
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ldr r3, =SDRAM_CMD_NOP
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ldr r4, =0x0
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loop:
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str r3, [r2]
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add r4, r4, #1
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cmp r4, \num
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bls loop
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.endm
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/*
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* Memory setup
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*/
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@ -96,7 +82,7 @@ lowlevel_init:
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/* clocks to settle. Only necessary after hard reset... */
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/* FIXME: can be optimized later */
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/* ---------------------------------------------------------------- */
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wait #300
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; wait #300
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mem_init:
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@ -138,7 +124,7 @@ mem_init:
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/* Set MDMRS */
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ldr r0, =MDMRS
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ldr r1, =0x60000023
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ldr r1, =0x60000033
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str r1, [r0]
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wait #300
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@ -269,13 +255,11 @@ mem_init:
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#endif /* NEW_SDRAM_INIT */
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#ifndef CFG_SKIP_DRAM_SCRUB
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/* scrub/init SDRAM if enabled/present */
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/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
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/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
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/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */
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ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */
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ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */
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mov r0, #0 /* scrub with 0x0000:0000 */
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ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */
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ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */
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mov r0, #0 /* scrub with 0x0000:0000 */
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mov r1, #0
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mov r2, #0
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mov r3, #0
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@ -284,10 +268,11 @@ mem_init:
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mov r6, #0
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mov r7, #0
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10: /* fastScrubLoop */
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subs r9, r9, #32 // 32 bytes/line
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subs r9, r9, #32 /* 8 words/line */
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stmia r8!, {r0-r7}
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beq 15f
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b 10b
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#endif /* CFG_SKIP_DRAM_SCRUB */
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15:
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/* Mask all interrupts */
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@ -143,14 +143,14 @@
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x8000000 /* 128 MB */
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#define PHYS_SDRAM_2 0x88000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x8000000 /* 128 MB */
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#define PHYS_SDRAM_3 0x90000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x8000000 /* 128 MB */
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#define PHYS_SDRAM_4 0x98000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x8000000 /* 128 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
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@ -158,8 +158,10 @@
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#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
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#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
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#define CFG_DRAM_BASE 0xa0000000
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#define CFG_DRAM_SIZE 0x04000000
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#define CFG_DRAM_BASE 0x80000000 /* at CS0 */
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#define CFG_DRAM_SIZE 0x20000000 /* 512 MB Ram */
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#define CFG_SKIP_DRAM_SCRUB 1
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#define CFG_FLASH_BASE PHYS_FLASH_1
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@ -120,8 +120,8 @@
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_DEVICE_NULLDEV 1
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#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#define CFG_MEMTEST_START 0x9c000000 /* memtest works on */
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#define CFG_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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