Blackfin: rewrite cache handling functions
Take the cache flush functions from the kernel as they use hardware loops in order to get optimal performance. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
84c5f0dc47
commit
fdce83c108
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@ -1,5 +1,10 @@
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/* cache.S - low level cache handling routines
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* Copyright (C) 2003-2007 Analog Devices Inc.
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/*
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* Blackfin cache control code
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*
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* Copyright 2003-2008 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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@ -8,54 +13,75 @@
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#include <asm/blackfin.h>
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.text
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.align 2
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ENTRY(_blackfin_icache_flush_range)
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R2 = -32;
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R2 = R0 & R2;
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P0 = R2;
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P1 = R1;
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CSYNC;
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/* Since all L1 caches work the same way, we use the same method for flushing
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* them. Only the actual flush instruction differs. We write this in asm as
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* GCC can be hard to coax into writing nice hardware loops.
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*
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* Also, we assume the following register setup:
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* R0 = start address
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* R1 = end address
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*/
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.macro do_flush flushins:req optflushins optnopins label
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R2 = -L1_CACHE_BYTES;
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/* start = (start & -L1_CACHE_BYTES) */
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R0 = R0 & R2;
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/* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
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R1 += -1;
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R1 = R1 & R2;
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R1 += L1_CACHE_BYTES;
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/* count = (end - start) >> L1_CACHE_SHIFT */
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R2 = R1 - R0;
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R2 >>= L1_CACHE_SHIFT;
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P1 = R2;
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.ifnb \label
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\label :
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.endif
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P0 = R0;
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LSETUP (1f, 2f) LC1 = P1;
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1:
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IFLUSH[P0++];
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CC = P0 < P1(iu);
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IF CC JUMP 1b(bp);
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IFLUSH[P0];
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SSYNC;
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.ifnb \optflushins
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\optflushins [P0];
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.endif
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#if ANOMALY_05000443
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.ifb \optnopins
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2:
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.endif
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\flushins [P0++];
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.ifnb \optnopins
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2: \optnopins;
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.endif
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#else
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2: \flushins [P0++];
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#endif
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RTS;
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.endm
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/* Invalidate all instruction cache lines assocoiated with this memory area */
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ENTRY(_blackfin_icache_flush_range)
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do_flush IFLUSH, , nop
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ENDPROC(_blackfin_icache_flush_range)
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ENTRY(_blackfin_dcache_flush_range)
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R2 = -32;
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R2 = R0 & R2;
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P0 = R2;
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P1 = R1;
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CSYNC;
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1:
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FLUSH[P0++];
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CC = P0 < P1(iu);
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IF CC JUMP 1b(bp);
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FLUSH[P0];
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SSYNC;
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RTS;
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ENDPROC(_blackfin_dcache_flush_range)
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/* Flush all cache lines assocoiated with this area of memory. */
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ENTRY(_blackfin_icache_dcache_flush_range)
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do_flush FLUSH, IFLUSH
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ENDPROC(_blackfin_icache_dcache_flush_range)
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/* Throw away all D-cached data in specified region without any obligation to
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* write them back. Since the Blackfin ISA does not have an "invalidate"
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* instruction, we use flush/invalidate. Perhaps as a speed optimization we
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* could bang on the DTEST MMRs ...
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*/
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ENTRY(_blackfin_dcache_flush_invalidate_range)
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R2 = -32;
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R2 = R0 & R2;
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P0 = R2;
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P1 = R1;
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CSYNC;
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1:
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FLUSHINV[P0++];
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CC = P0 < P1(iu);
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IF CC JUMP 1b(bp);
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/*
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* If the data crosses a cache line, then we'll be pointing to
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* the last cache line, but won't have flushed/invalidated it yet, so do
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* one more.
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*/
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FLUSHINV[P0];
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SSYNC;
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RTS;
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do_flush FLUSHINV
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ENDPROC(_blackfin_dcache_flush_invalidate_range)
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/* Flush all data cache lines assocoiated with this memory area */
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ENTRY(_blackfin_dcache_flush_range)
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do_flush FLUSH, , , .Ldfr
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ENDPROC(_blackfin_dcache_flush_range)
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@ -43,6 +43,9 @@
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#define SCLK_TO_MSEC(sclk) ((MSEC_PER_SEC * ((sclk) / USEC_PER_MSEC)) / (BFIN_SCLK / USEC_PER_MSEC))
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#define MSEC_TO_SCLK(msec) ((((BFIN_SCLK / USEC_PER_MSEC) * (msec)) / MSEC_PER_SEC) * USEC_PER_MSEC)
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#define L1_CACHE_SHIFT 5
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#include <asm/linkage.h>
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#ifndef __ASSEMBLY__
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@ -60,6 +63,7 @@ extern u_long get_sclk(void);
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extern void blackfin_icache_flush_range(const void *, const void *);
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extern void blackfin_dcache_flush_range(const void *, const void *);
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extern void blackfin_icache_dcache_flush_range(const void *, const void *);
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extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
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/* Use DMA to move data from on chip to external memory. While this is
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@ -15,15 +15,25 @@
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void flush_cache(unsigned long addr, unsigned long size)
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{
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void *start_addr, *end_addr;
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int istatus, dstatus;
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/* no need to flush stuff in on chip memory (L1/L2/etc...) */
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if (addr >= 0xE0000000)
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return;
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if (icache_status())
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blackfin_icache_flush_range((void *)addr, (void *)(addr + size));
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start_addr = (void *)addr;
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end_addr = (void *)(addr + size);
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istatus = icache_status();
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dstatus = dcache_status();
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if (dcache_status())
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blackfin_dcache_flush_range((void *)addr, (void *)(addr + size));
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if (istatus) {
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if (dstatus)
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blackfin_icache_dcache_flush_range(start_addr, end_addr);
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else
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blackfin_icache_flush_range(start_addr, end_addr);
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} else if (dstatus)
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blackfin_dcache_flush_range(start_addr, end_addr);
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}
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void icache_enable(void)
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