Merge with /home/wd/git/u-boot/master
This commit is contained in:
Wolfgang Denk
commit
fc43de0d4a
10
CHANGELOG
10
CHANGELOG
|
|
@ -2,6 +2,16 @@
|
|||
Changes since U-Boot 1.1.4:
|
||||
======================================================================
|
||||
|
||||
* Extended README entry on coding style
|
||||
|
||||
* Added another example showing simple interrupt interception.
|
||||
|
||||
* Added simple_strtoul(), getenv() and setenv() to the exported functions.
|
||||
Also bumped up ABI version to reflect this change.
|
||||
|
||||
* Added interrupt handling capabilities for mpc5xxx processors.
|
||||
Also added Linux like BUG() macros.
|
||||
|
||||
* Coding Style cleanup.
|
||||
Patch by Stefano Babic, 31 Aug 2006
|
||||
|
||||
|
|
|
|||
|
|
@ -318,6 +318,11 @@ Rune Torgersen <runet@innovsys.com>
|
|||
|
||||
MPC8266ADS MPC8266
|
||||
|
||||
|
||||
David Updegraff <dave@cray.com>
|
||||
|
||||
CRAYL1 PPC4xx
|
||||
|
||||
Josef Wagner <Wagner@Microsys.de>
|
||||
|
||||
CPC45 MPC8245
|
||||
|
|
@ -347,7 +352,6 @@ Unknown / orphaned boards:
|
|||
RPXClassic MPC8xx
|
||||
RPXlite MPC8xx
|
||||
|
||||
CRAYL1 PPC4xx
|
||||
ERIC PPC4xx
|
||||
|
||||
MOUSSE MPC824x
|
||||
|
|
|
|||
17
README
17
README
|
|
@ -3469,12 +3469,19 @@ Coding Standards:
|
|||
-----------------
|
||||
|
||||
All contributions to U-Boot should conform to the Linux kernel
|
||||
coding style; see the file "Documentation/CodingStyle" in your Linux
|
||||
kernel source directory.
|
||||
coding style; see the file "Documentation/CodingStyle" and the script
|
||||
"scripts/Lindent" in your Linux kernel source directory. In sources
|
||||
originating from U-Boot a style corresponding to "Lindent -pcs" (adding
|
||||
spaces before parameters to function calls) is actually used.
|
||||
|
||||
Please note that U-Boot is implemented in C (and to some small parts
|
||||
in Assembler); no C++ is used, so please do not use C++ style
|
||||
comments (//) in your code.
|
||||
Source files originating from a different project (for example the
|
||||
MTD subsystem) are generally exempt from these guidelines and are not
|
||||
reformated to ease subsequent migration to newer versions of those
|
||||
sources.
|
||||
|
||||
Please note that U-Boot is implemented in C (and to some small parts in
|
||||
Assembler); no C++ is used, so please do not use C++ style comments (//)
|
||||
in your code.
|
||||
|
||||
Please also stick to the following formatting rules:
|
||||
- remove any trailing white space
|
||||
|
|
|
|||
|
|
@ -23,8 +23,11 @@ void jumptable_init (void)
|
|||
gd->jt[XF_get_version] = (void *) get_version;
|
||||
gd->jt[XF_malloc] = (void *) malloc;
|
||||
gd->jt[XF_free] = (void *) free;
|
||||
gd->jt[XF_get_timer] = (void *)get_timer;
|
||||
gd->jt[XF_udelay] = (void *)udelay;
|
||||
gd->jt[XF_getenv] = (void *) getenv;
|
||||
gd->jt[XF_setenv] = (void *) setenv;
|
||||
gd->jt[XF_get_timer] = (void *) get_timer;
|
||||
gd->jt[XF_simple_strtoul] = (void *) simple_strtoul;
|
||||
gd->jt[XF_udelay] = (void *) udelay;
|
||||
#if defined(CONFIG_I386) || defined(CONFIG_PPC)
|
||||
gd->jt[XF_install_hdlr] = (void *) irq_install_handler;
|
||||
gd->jt[XF_free_hdlr] = (void *) irq_free_handler;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,7 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Detlev Zundel, DENX Software Engineering, dzu@denx.de
|
||||
*
|
||||
* (C) Copyright -2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
|
|
@ -24,18 +27,212 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* interrupts.c - just enough support for the decrementer/timer
|
||||
/* this section was ripped out of arch/ppc/syslib/mpc52xx_pic.c in the
|
||||
* Linux 2.6 source with the following copyright.
|
||||
*
|
||||
* Based on (well, mostly copied from) the code from the 2.4 kernel by
|
||||
* Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
|
||||
*
|
||||
* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
|
||||
* Copyright (C) 2003 Montavista Software, Inc
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <command.h>
|
||||
|
||||
int interrupt_init_cpu (ulong *decrementer_count)
|
||||
struct irq_action {
|
||||
interrupt_handler_t *handler;
|
||||
void *arg;
|
||||
ulong count;
|
||||
};
|
||||
|
||||
static struct irq_action irq_handlers[NR_IRQS];
|
||||
|
||||
static struct mpc5xxx_intr *intr;
|
||||
static struct mpc5xxx_sdma *sdma;
|
||||
|
||||
static void mpc5xxx_ic_disable(unsigned int irq)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (irq == MPC5XXX_IRQ0) {
|
||||
val = in_be32(&intr->ctrl);
|
||||
val &= ~(1 << 11);
|
||||
out_be32(&intr->ctrl, val);
|
||||
} else if (irq < MPC5XXX_IRQ1) {
|
||||
BUG();
|
||||
} else if (irq <= MPC5XXX_IRQ3) {
|
||||
val = in_be32(&intr->ctrl);
|
||||
val &= ~(1 << (10 - (irq - MPC5XXX_IRQ1)));
|
||||
out_be32(&intr->ctrl, val);
|
||||
} else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
|
||||
val = in_be32(&intr->main_mask);
|
||||
val |= 1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE));
|
||||
out_be32(&intr->main_mask, val);
|
||||
} else if (irq < MPC5XXX_PERP_IRQ_BASE) {
|
||||
val = in_be32(&sdma->IntMask);
|
||||
val |= 1 << (irq - MPC5XXX_SDMA_IRQ_BASE);
|
||||
out_be32(&sdma->IntMask, val);
|
||||
} else {
|
||||
val = in_be32(&intr->per_mask);
|
||||
val |= 1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE));
|
||||
out_be32(&intr->per_mask, val);
|
||||
}
|
||||
}
|
||||
|
||||
static void mpc5xxx_ic_enable(unsigned int irq)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (irq == MPC5XXX_IRQ0) {
|
||||
val = in_be32(&intr->ctrl);
|
||||
val |= 1 << 11;
|
||||
out_be32(&intr->ctrl, val);
|
||||
} else if (irq < MPC5XXX_IRQ1) {
|
||||
BUG();
|
||||
} else if (irq <= MPC5XXX_IRQ3) {
|
||||
val = in_be32(&intr->ctrl);
|
||||
val |= 1 << (10 - (irq - MPC5XXX_IRQ1));
|
||||
out_be32(&intr->ctrl, val);
|
||||
} else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
|
||||
val = in_be32(&intr->main_mask);
|
||||
val &= ~(1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE)));
|
||||
out_be32(&intr->main_mask, val);
|
||||
} else if (irq < MPC5XXX_PERP_IRQ_BASE) {
|
||||
val = in_be32(&sdma->IntMask);
|
||||
val &= ~(1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
|
||||
out_be32(&sdma->IntMask, val);
|
||||
} else {
|
||||
val = in_be32(&intr->per_mask);
|
||||
val &= ~(1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE)));
|
||||
out_be32(&intr->per_mask, val);
|
||||
}
|
||||
}
|
||||
|
||||
static void mpc5xxx_ic_ack(unsigned int irq)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* Only some irqs are reset here, others in interrupting hardware.
|
||||
*/
|
||||
|
||||
switch (irq) {
|
||||
case MPC5XXX_IRQ0:
|
||||
val = in_be32(&intr->ctrl);
|
||||
val |= 0x08000000;
|
||||
out_be32(&intr->ctrl, val);
|
||||
break;
|
||||
case MPC5XXX_CCS_IRQ:
|
||||
val = in_be32(&intr->enc_status);
|
||||
val |= 0x00000400;
|
||||
out_be32(&intr->enc_status, val);
|
||||
break;
|
||||
case MPC5XXX_IRQ1:
|
||||
val = in_be32(&intr->ctrl);
|
||||
val |= 0x04000000;
|
||||
out_be32(&intr->ctrl, val);
|
||||
break;
|
||||
case MPC5XXX_IRQ2:
|
||||
val = in_be32(&intr->ctrl);
|
||||
val |= 0x02000000;
|
||||
out_be32(&intr->ctrl, val);
|
||||
break;
|
||||
case MPC5XXX_IRQ3:
|
||||
val = in_be32(&intr->ctrl);
|
||||
val |= 0x01000000;
|
||||
out_be32(&intr->ctrl, val);
|
||||
break;
|
||||
default:
|
||||
if (irq >= MPC5XXX_SDMA_IRQ_BASE
|
||||
&& irq < (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)) {
|
||||
out_be32(&sdma->IntPend,
|
||||
1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void mpc5xxx_ic_disable_and_ack(unsigned int irq)
|
||||
{
|
||||
mpc5xxx_ic_disable(irq);
|
||||
mpc5xxx_ic_ack(irq);
|
||||
}
|
||||
|
||||
static void mpc5xxx_ic_end(unsigned int irq)
|
||||
{
|
||||
mpc5xxx_ic_enable(irq);
|
||||
}
|
||||
|
||||
void mpc5xxx_init_irq(void)
|
||||
{
|
||||
u32 intr_ctrl;
|
||||
|
||||
/* Remap the necessary zones */
|
||||
intr = (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
|
||||
sdma = (struct mpc5xxx_sdma *)(MPC5XXX_SDMA);
|
||||
|
||||
/* Disable all interrupt sources. */
|
||||
out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
|
||||
out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
|
||||
out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
|
||||
out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
|
||||
intr_ctrl = in_be32(&intr->ctrl);
|
||||
intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
|
||||
0x00ff0000 | /* IRQ 0-3 level sensitive low active */
|
||||
0x00001000 | /* MEE master external enable */
|
||||
0x00000000 | /* 0 means disable IRQ 0-3 */
|
||||
0x00000001; /* CEb route critical normally */
|
||||
out_be32(&intr->ctrl, intr_ctrl);
|
||||
|
||||
/* Zero a bunch of the priority settings. */
|
||||
out_be32(&intr->per_pri1, 0);
|
||||
out_be32(&intr->per_pri2, 0);
|
||||
out_be32(&intr->per_pri3, 0);
|
||||
out_be32(&intr->main_pri1, 0);
|
||||
out_be32(&intr->main_pri2, 0);
|
||||
}
|
||||
|
||||
int mpc5xxx_get_irq(struct pt_regs *regs)
|
||||
{
|
||||
u32 status;
|
||||
int irq = -1;
|
||||
|
||||
status = in_be32(&intr->enc_status);
|
||||
|
||||
if (status & 0x00000400) { /* critical */
|
||||
irq = (status >> 8) & 0x3;
|
||||
if (irq == 2) /* high priority peripheral */
|
||||
goto peripheral;
|
||||
irq += MPC5XXX_CRIT_IRQ_BASE;
|
||||
} else if (status & 0x00200000) { /* main */
|
||||
irq = (status >> 16) & 0x1f;
|
||||
if (irq == 4) /* low priority peripheral */
|
||||
goto peripheral;
|
||||
irq += MPC5XXX_MAIN_IRQ_BASE;
|
||||
} else if (status & 0x20000000) { /* peripheral */
|
||||
peripheral:
|
||||
irq = (status >> 24) & 0x1f;
|
||||
if (irq == 0) { /* bestcomm */
|
||||
status = in_be32(&sdma->IntPend);
|
||||
irq = ffs(status) + MPC5XXX_SDMA_IRQ_BASE - 1;
|
||||
} else
|
||||
irq += MPC5XXX_PERP_IRQ_BASE;
|
||||
}
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
int interrupt_init_cpu(ulong * decrementer_count)
|
||||
{
|
||||
*decrementer_count = get_tbclk() / CFG_HZ;
|
||||
|
||||
mpc5xxx_init_irq();
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
|
@ -44,14 +241,32 @@ int interrupt_init_cpu (ulong *decrementer_count)
|
|||
/*
|
||||
* Handle external interrupts
|
||||
*/
|
||||
void
|
||||
external_interrupt(struct pt_regs *regs)
|
||||
void external_interrupt(struct pt_regs *regs)
|
||||
{
|
||||
puts("external_interrupt (oops!)\n");
|
||||
int irq, unmask = 1;
|
||||
|
||||
irq = mpc5xxx_get_irq(regs);
|
||||
|
||||
mpc5xxx_ic_disable_and_ack(irq);
|
||||
|
||||
enable_interrupts();
|
||||
|
||||
if (irq_handlers[irq].handler != NULL)
|
||||
(*irq_handlers[irq].handler) (irq_handlers[irq].arg);
|
||||
else {
|
||||
printf("\nBogus External Interrupt IRQ %d\n", irq);
|
||||
/*
|
||||
* turn off the bogus interrupt, otherwise it
|
||||
* might repeat forever
|
||||
*/
|
||||
unmask = 0;
|
||||
}
|
||||
|
||||
if (unmask)
|
||||
mpc5xxx_ic_end(irq);
|
||||
}
|
||||
|
||||
void
|
||||
timer_interrupt_cpu (struct pt_regs *regs)
|
||||
void timer_interrupt_cpu(struct pt_regs *regs)
|
||||
{
|
||||
/* nothing to do here */
|
||||
return;
|
||||
|
|
@ -63,22 +278,69 @@ timer_interrupt_cpu (struct pt_regs *regs)
|
|||
* Install and free a interrupt handler.
|
||||
*/
|
||||
|
||||
void
|
||||
irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
|
||||
void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
|
||||
{
|
||||
if (irq < 0 || irq >= NR_IRQS) {
|
||||
printf("irq_install_handler: bad irq number %d\n", irq);
|
||||
return;
|
||||
}
|
||||
|
||||
if (irq_handlers[irq].handler != NULL)
|
||||
printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
|
||||
(ulong) handler, (ulong) irq_handlers[irq].handler);
|
||||
|
||||
irq_handlers[irq].handler = handler;
|
||||
irq_handlers[irq].arg = arg;
|
||||
|
||||
mpc5xxx_ic_enable(irq);
|
||||
}
|
||||
|
||||
void
|
||||
irq_free_handler(int vec)
|
||||
void irq_free_handler(int irq)
|
||||
{
|
||||
if (irq < 0 || irq >= NR_IRQS) {
|
||||
printf("irq_free_handler: bad irq number %d\n", irq);
|
||||
return;
|
||||
}
|
||||
|
||||
mpc5xxx_ic_disable(irq);
|
||||
|
||||
irq_handlers[irq].handler = NULL;
|
||||
irq_handlers[irq].arg = NULL;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
|
||||
void
|
||||
do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
|
||||
void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
|
||||
{
|
||||
puts("IRQ related functions are unimplemented currently.\n");
|
||||
int irq, re_enable;
|
||||
u32 intr_ctrl;
|
||||
char *irq_config[] = { "level sensitive, active high",
|
||||
"edge sensitive, rising active edge",
|
||||
"edge sensitive, falling active edge",
|
||||
"level sensitive, active low"
|
||||
};
|
||||
|
||||
re_enable = disable_interrupts();
|
||||
|
||||
intr_ctrl = in_be32(&intr->ctrl);
|
||||
printf("Interrupt configuration:\n");
|
||||
|
||||
for (irq = 0; irq <= 3; irq++) {
|
||||
printf("IRQ%d: %s\n", irq,
|
||||
irq_config[(intr_ctrl >> (22 - 2 * irq)) & 0x3]);
|
||||
}
|
||||
|
||||
puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n");
|
||||
|
||||
for (irq = 0; irq < NR_IRQS; irq++)
|
||||
if (irq_handlers[irq].handler != NULL)
|
||||
printf("%02d %08lx %08lx %ld\n", irq,
|
||||
(ulong) irq_handlers[irq].handler,
|
||||
(ulong) irq_handlers[irq].arg,
|
||||
irq_handlers[irq].count);
|
||||
|
||||
if (re_enable)
|
||||
enable_interrupts();
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -94,6 +94,12 @@ SREC += mem_to_mem_idma2intr.srec
|
|||
BIN += mem_to_mem_idma2intr.bin mem_to_mem_idma2intr
|
||||
endif
|
||||
|
||||
# Demo for 52xx IRQs
|
||||
ifeq ($(CPU),mpc5xxx)
|
||||
SREC += interrupt.srec
|
||||
BIN += interrupt.bin interrupt
|
||||
endif
|
||||
|
||||
# Utility for resetting i82559 EEPROM
|
||||
ifeq ($(BOARD),oxc)
|
||||
SREC += eepro100_eeprom.srec
|
||||
|
|
|
|||
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* This is a very simple standalone application demonstrating
|
||||
* catching IRQs on the MPC52xx architecture.
|
||||
*
|
||||
* The interrupt to be intercepted can be specified as an argument
|
||||
* to the application. Specifying nothing will intercept IRQ1 on the
|
||||
* MPC5200 platform. On the CR825 carrier board from MicroSys this
|
||||
* maps to the ABORT switch :)
|
||||
*
|
||||
* Note that the specified vector is only a logical number specified
|
||||
* by the respective header file.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <exports.h>
|
||||
#include <config.h>
|
||||
|
||||
#if defined(CONFIG_MPC5xxx)
|
||||
#define DFL_IRQ MPC5XXX_IRQ1
|
||||
#else
|
||||
#define DFL_IRQ 0
|
||||
#endif
|
||||
|
||||
static void irq_handler (void *arg);
|
||||
|
||||
int interrupt (int argc, char *argv[])
|
||||
{
|
||||
int c, irq = -1;
|
||||
|
||||
app_startup (argv);
|
||||
|
||||
if (argc > 1)
|
||||
irq = simple_strtoul (argv[1], NULL, 0);
|
||||
if ((irq < 0) || (irq > NR_IRQS))
|
||||
irq = DFL_IRQ;
|
||||
|
||||
printf ("Installing handler for irq vector %d and doing busy wait\n",
|
||||
irq);
|
||||
printf ("Press 'q' to quit\n");
|
||||
|
||||
/* Install interrupt handler */
|
||||
install_hdlr (irq, irq_handler, NULL);
|
||||
while ((c = getc ()) != 'q') {
|
||||
printf ("Ok, ok, I am still alive!\n");
|
||||
}
|
||||
|
||||
free_hdlr (irq);
|
||||
printf ("\nInterrupt handler has been uninstalled\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Handler for interrupt
|
||||
*/
|
||||
static void irq_handler (void *arg)
|
||||
{
|
||||
/* just for demonstration */
|
||||
printf ("+");
|
||||
}
|
||||
|
|
@ -12,6 +12,9 @@ EXPORT_FUNC(udelay)
|
|||
EXPORT_FUNC(get_timer)
|
||||
EXPORT_FUNC(vprintf)
|
||||
EXPORT_FUNC(do_reset)
|
||||
EXPORT_FUNC(getenv)
|
||||
EXPORT_FUNC(setenv)
|
||||
EXPORT_FUNC(simple_strtoul)
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
|
||||
EXPORT_FUNC(i2c_write)
|
||||
EXPORT_FUNC(i2c_read)
|
||||
|
|
|
|||
|
|
@ -109,6 +109,12 @@ typedef volatile unsigned char vu_char;
|
|||
#define debugX(level,fmt,args...)
|
||||
#endif /* DEBUG */
|
||||
|
||||
#define BUG() do { \
|
||||
printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
|
||||
panic("BUG!"); \
|
||||
} while (0)
|
||||
#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
|
||||
|
||||
typedef void (interrupt_handler_t)(void *);
|
||||
|
||||
#include <asm/u-boot.h> /* boot information for Linux kernel */
|
||||
|
|
|
|||
|
|
@ -20,6 +20,9 @@ void udelay(unsigned long);
|
|||
unsigned long get_timer(unsigned long);
|
||||
void vprintf(const char *, va_list);
|
||||
void do_reset (void);
|
||||
unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
|
||||
char *getenv (char *name);
|
||||
void setenv (char *varname, char *varvalue);
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
|
||||
int i2c_write (uchar, uint, int , uchar* , int);
|
||||
int i2c_read (uchar, uint, int , uchar* , int);
|
||||
|
|
@ -37,7 +40,7 @@ enum {
|
|||
XF_MAX
|
||||
};
|
||||
|
||||
#define XF_VERSION 2
|
||||
#define XF_VERSION 3
|
||||
|
||||
#if defined(CONFIG_I386)
|
||||
extern gd_t *global_data;
|
||||
|
|
|
|||
|
|
@ -232,6 +232,65 @@
|
|||
#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
|
||||
#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
|
||||
|
||||
#define NR_IRQS 64
|
||||
|
||||
/* IRQ mapping - these are our logical IRQ numbers */
|
||||
#define MPC5XXX_CRIT_IRQ_NUM 4
|
||||
#define MPC5XXX_MAIN_IRQ_NUM 17
|
||||
#define MPC5XXX_SDMA_IRQ_NUM 17
|
||||
#define MPC5XXX_PERP_IRQ_NUM 23
|
||||
|
||||
#define MPC5XXX_CRIT_IRQ_BASE 1
|
||||
#define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
|
||||
#define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
|
||||
#define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
|
||||
|
||||
#define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0)
|
||||
#define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1)
|
||||
#define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2)
|
||||
#define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3)
|
||||
|
||||
#define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1)
|
||||
#define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2)
|
||||
#define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3)
|
||||
#define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5)
|
||||
#define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6)
|
||||
#define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7)
|
||||
#define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8)
|
||||
#define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9)
|
||||
#define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10)
|
||||
#define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11)
|
||||
#define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12)
|
||||
#define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13)
|
||||
#define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14)
|
||||
#define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15)
|
||||
#define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16)
|
||||
|
||||
#define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0)
|
||||
#define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1)
|
||||
#define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2)
|
||||
#define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3)
|
||||
#define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
|
||||
#define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4)
|
||||
#define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5)
|
||||
#define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6)
|
||||
#define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7)
|
||||
#define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8)
|
||||
#define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9)
|
||||
#define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10)
|
||||
#define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11)
|
||||
#define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12)
|
||||
#define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13)
|
||||
#define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14)
|
||||
#define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15)
|
||||
#define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16)
|
||||
#define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17)
|
||||
#define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18)
|
||||
#define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19)
|
||||
#define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20)
|
||||
#define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21)
|
||||
#define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22)
|
||||
|
||||
/* General Purpose Timers registers */
|
||||
#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
|
||||
#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
|
||||
|
|
|
|||
Loading…
Reference in New Issue