Marvell RD6281A Board support
This is Marvell's 88F6281_A0 based reference design board This patch is tested for- 1. Boot from DRAM/NAND flash/NFS 2. File transfer using tftp and loadb 3. NAND flash read/write/erase Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Prafulla Wadaskar
Jean-Christophe PLAGNIOL-VILLARD
parent
2906e6d654
commit
fbc8365ad7
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@ -688,6 +688,7 @@ Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
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Prafulla Wadaskar <prafulla@marvell.com>
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mv88f6281gtw_ge ARM926EJS (Kirkwood SoC)
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rd6281a ARM926EJS (Kirkwood SoC)
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sheevaplug ARM926EJS (Kirkwood SoC)
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Richard Woodruff <r-woodruff2@ti.com>
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1
MAKEALL
1
MAKEALL
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@ -522,6 +522,7 @@ LIST_ARM9=" \
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omap1610inn \
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omap5912osk \
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omap730p2 \
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rd6281a \
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sbc2410x \
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scb9328 \
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sheevaplug \
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3
Makefile
3
Makefile
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@ -2961,6 +2961,9 @@ omap730p2_cs3boot_config : unconfig
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fi;
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@$(MKCONFIG) -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap
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rd6281a_config: unconfig
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@$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood
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sbc2410x_config: unconfig
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@$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0
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@ -0,0 +1,51 @@
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#
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := rd6281a.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,25 @@
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#
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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TEXT_BASE = 0x00600000
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@ -0,0 +1,179 @@
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/kirkwood.h>
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#include <asm/arch/mpp.h>
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#include "rd6281a.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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kw_config_gpio(RD6281A_OE_VAL_LOW,
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RD6281A_OE_VAL_HIGH,
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RD6281A_OE_LOW, RD6281A_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_GPO,
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_SD_CLK,
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MPP13_SD_CMD,
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MPP14_SD_D0,
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MPP15_SD_D1,
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MPP16_SD_D2,
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MPP17_SD_D3,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_GE1_0,
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MPP21_GE1_1,
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MPP22_GE1_2,
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MPP23_GE1_3,
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MPP24_GE1_4,
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MPP25_GE1_5,
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MPP26_GE1_6,
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MPP27_GE1_7,
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MPP28_GPIO,
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MPP29_GPIO,
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MPP30_GE1_10,
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MPP31_GE1_11,
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MPP32_GE1_12,
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MPP33_GE1_13,
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MPP34_GE1_14,
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MPP35_GPIO,
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MPP36_AUDIO_SPDIFI,
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MPP37_AUDIO_SPDIFO,
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MPP38_GPIO,
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MPP39_TDM_SPI_CS0,
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MPP40_TDM_SPI_SCK,
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MPP41_TDM_SPI_MISO,
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MPP42_TDM_SPI_MOSI,
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MPP43_TDM_CODEC_INTn,
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MPP44_GPIO,
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MPP45_TDM_PCLK,
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MPP46_TDM_FS,
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MPP47_TDM_DRX,
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MPP48_TDM_DTX,
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MPP49_GPIO,
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0
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};
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kirkwood_mpp_conf(kwmpp_config);
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/*
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* arch number of board
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*/
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gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
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return 0;
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}
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int dram_init(void)
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{
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = kw_sdram_bar(i);
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gd->bd->bi_dram[i].size = kw_sdram_bs(i);
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}
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return 0;
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}
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void mv_phy_88e1116_init(char *name)
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{
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u16 reg;
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u16 devadr;
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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printf("Err..%s could not read PHY dev address\n",
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__FUNCTION__);
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return;
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}
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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if (miiphy_read (name, devadr, PHY_BMCR, ®) != 0) {
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printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
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return;
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}
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if (miiphy_write (name, devadr, PHY_BMCR, reg | 0x8000) != 0) {
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printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
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return;
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}
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printf("88E1116 Initialized on %s\n", name);
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}
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/* Configure and enable Switch and PHY */
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void reset_phy(void)
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{
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/* configure and initialize switch */
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struct mv88e61xx_config swcfg = {
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.name = "egiga0",
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.vlancfg = MV88E61XX_VLANCFG_ROUTER,
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.rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
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.led_init = MV88E61XX_LED_INIT_EN,
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.portstate = MV88E61XX_PORTSTT_FORWARDING,
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.cpuport = (1 << 5),
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.ports_enabled = 0x3f,
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};
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mv88e61xx_switch_initialize(&swcfg);
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/* configure and initialize PHY */
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mv_phy_88e1116_init("egiga1");
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}
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@ -0,0 +1,41 @@
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef __RD6281A_H
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#define __RD6281A_H
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#define RD6281A_OE_LOW (~(1 << 7))
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#define RD6281A_OE_HIGH (~(1 << 2 | 1 << 12))
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#define RD6281A_OE_VAL_LOW (0)
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#define RD6281A_OE_VAL_HIGH (1 << 12)
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/* PHY related */
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#define MV88E1116_LED_FCTRL_REG 10
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#define MV88E1116_CPRSP_CR3_REG 21
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#define MV88E1116_MAC_CTRL_REG 21
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#define MV88E1116_PGADR_REG 22
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
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#endif /* __RD6281A_H */
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@ -0,0 +1,198 @@
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
|
||||
*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
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* MA 02110-1301 USA
|
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*/
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#ifndef _CONFIG_RD6281A_H
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#define _CONFIG_RD6281A_H
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/*
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* Version number information
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*/
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#define CONFIG_IDENT_STRING "\nMarvell-RD6281A"
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_MARVELL 1
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#define CONFIG_ARM926EJS 1 /* Basic Architecture */
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#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
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#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
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#define CONFIG_KW88F6281 1 /* SOC Name */
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#define CONFIG_MACH_RD6281A /* Machine type */
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#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
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#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
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#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
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#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
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/*
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* CLKs configurations
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*/
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#define CONFIG_SYS_HZ 1000
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
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#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
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/*
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* Serial Port configuration
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* The following definitions let you select what serial you want to use
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* for your console driver.
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*/
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#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
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115200,230400, 460800, 921600 }
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/* auto boot */
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#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
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#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
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#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
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+sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
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/*
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||||
* Commands configuration
|
||||
*/
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||||
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
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#include <config_cmd_default.h>
|
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#define CONFIG_CMD_AUTOSCRIPT
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_PING
|
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#define CONFIG_CMD_USB
|
||||
|
||||
/*
|
||||
* NAND configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NAND
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||||
#define CONFIG_NAND_KIRKWOOD
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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||||
#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */
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||||
#define NAND_ALLOW_ERASE_ALL 1
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||||
#endif
|
||||
|
||||
/*
|
||||
* Environment variables configurations
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
|
||||
#else
|
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
|
||||
#endif
|
||||
/*
|
||||
* max 4k env size is enough, but in case of nand
|
||||
* it has to be rounded to sector size
|
||||
*/
|
||||
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
|
||||
#define CONFIG_ENV_ADDR 0x40000
|
||||
#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
|
||||
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
|
||||
"${x_bootcmd_usb}; bootm 0x6400000;"
|
||||
|
||||
#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \
|
||||
"3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
|
||||
"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
|
||||
"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
|
||||
"x_bootcmd_usb=usb start\0" \
|
||||
"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
|
||||
/* size in bytes reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
|
||||
/*
|
||||
* Other required minimal configurations
|
||||
*/
|
||||
#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
|
||||
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
|
||||
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
|
||||
#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
|
||||
#define CONFIG_NR_DRAM_BANKS 4
|
||||
#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
|
||||
/*
|
||||
* Ethernet Driver configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */
|
||||
#define CONFIG_NET_MULTI /* specify more that one ports available */
|
||||
#define CONFIG_MII /* expose smi ove miiphy interface */
|
||||
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
|
||||
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
|
||||
#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
|
||||
#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
|
||||
#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */
|
||||
#define CONFIG_PHY_BASE_ADR 0x0A
|
||||
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
|
||||
#define CONFIG_RESET_PHY_R /* use reset_phy() to init switch and PHY */
|
||||
#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
/*
|
||||
* USB/EHCI
|
||||
*/
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
|
||||
#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
#endif /* CONFIG_CMD_USB */
|
||||
|
||||
#endif /* _CONFIG_RD6281A_H */
|
||||
Loading…
Reference in New Issue