AX88180: switch to common mii.h header
No compiled code change here, just drop the local PHY defines in favor of the common standard ones. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This commit is contained in:
Mike Frysinger
Ben Warren
parent
141ab7a52c
commit
f9abdfe0f2
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@ -41,6 +41,7 @@
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#include <command.h>
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#include <net.h>
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#include <malloc.h>
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#include <linux/mii.h>
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#include "ax88180.h"
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/*
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@ -112,10 +113,10 @@ static int ax88180_phy_reset (struct eth_device *dev)
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{
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unsigned short delay_cnt = 500;
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ax88180_mdio_write (dev, BMCR, (PHY_RESET | AUTONEG_EN));
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ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE));
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/* Wait for the reset to complete, or time out (500 ms) */
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while (ax88180_mdio_read (dev, BMCR) & PHY_RESET) {
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while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) {
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udelay (1000);
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if (--delay_cnt == 0) {
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printf ("Failed to reset PHY!\n");
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@ -265,10 +266,10 @@ static int ax88180_phy_initial (struct eth_device *dev)
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#endif
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{
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priv->PhyAddr = phyaddr;
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priv->PhyID0 = ax88180_mdio_read(dev, PHYIDR0);
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priv->PhyID0 = ax88180_mdio_read(dev, MII_PHYSID1);
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switch (priv->PhyID0) {
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case MARVELL_88E1111_PHYIDR0:
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case MARVELL_88E1111_PHYSID0:
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debug("ax88180: Found Marvell 88E1111 PHY."
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" (PHY Addr=0x%x)\n", priv->PhyAddr);
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@ -282,7 +283,7 @@ static int ax88180_phy_initial (struct eth_device *dev)
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return 1;
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case CICADA_CIS8201_PHYIDR0:
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case CICADA_CIS8201_PHYSID0:
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debug("ax88180: Found CICADA CIS8201 PHY"
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" chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
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@ -321,20 +322,20 @@ static void ax88180_media_config (struct eth_device *dev)
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/* Waiting 2 seconds for PHY link stable */
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for (i = 0; i < 20000; i++) {
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bmsr_val = ax88180_mdio_read (dev, BMSR);
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if (bmsr_val & LINKOK) {
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bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
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if (bmsr_val & BMSR_LSTATUS) {
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break;
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}
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udelay (100);
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}
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bmsr_val = ax88180_mdio_read (dev, BMSR);
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bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
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debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val);
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if (bmsr_val & LINKOK) {
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bmcr_val = ax88180_mdio_read (dev, BMCR);
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if (bmsr_val & BMSR_LSTATUS) {
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bmcr_val = ax88180_mdio_read (dev, MII_BMCR);
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if (bmcr_val & AUTONEG_EN) {
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if (bmcr_val & BMCR_ANENABLE) {
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/*
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* Waiting for Auto-negotiation completion, this may
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@ -343,8 +344,8 @@ static void ax88180_media_config (struct eth_device *dev)
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debug ("ax88180: Auto-negotiation is "
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"enabled. Waiting for NWay completion..\n");
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for (i = 0; i < 50000; i++) {
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bmsr_val = ax88180_mdio_read (dev, BMSR);
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if (bmsr_val & AUTONEG_COMPLETE) {
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bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
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if (bmsr_val & BMSR_ANEGCOMPLETE) {
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break;
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}
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udelay (100);
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@ -357,10 +358,10 @@ static void ax88180_media_config (struct eth_device *dev)
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/* Get real media mode here */
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switch (priv->PhyID0) {
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case MARVELL_88E1111_PHYIDR0:
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case MARVELL_88E1111_PHYSID0:
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RealMediaMode = get_MarvellPHY_media_mode(dev);
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break;
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case CICADA_CIS8201_PHYIDR0:
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case CICADA_CIS8201_PHYSID0:
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RealMediaMode = get_CicadaPHY_media_mode(dev);
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break;
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default:
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@ -63,9 +63,9 @@ struct ax88180_private {
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/* Max Rx Jumbo size is 15K Bytes */
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#define MAX_RX_SIZE 0x3C00
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#define MARVELL_88E1111_PHYIDR0 0x0141
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#define MARVELL_88E1111_PHYSID0 0x0141
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#define CICADA_CIS8201_PHYIDR0 0x000F
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#define CICADA_CIS8201_PHYSID0 0x000F
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#define MEDIA_AUTO 0
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#define MEDIA_1000FULL 1
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@ -276,50 +276,6 @@ struct ax88180_private {
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#define SOFTRST_NORMAL 0x00000003
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#define SOFTRST_RESET_MAC 0x00000002
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/* External PHY Register Definition */
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#define BMCR 0x0000
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#define LINE_SPEED_MSB 0x0040
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#define DUPLEX_MODE 0x0100
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#define RESTART_AUTONEG 0x0200
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#define POWER_DOWN 0x0800
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#define AUTONEG_EN 0x1000
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#define LINE_SPEED_LSB 0x2000
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#define PHY_RESET 0x8000
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#define MEDIAMODE_MASK (LINE_SPEED_MSB | LINE_SPEED_LSB |\
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DUPLEX_MODE)
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#define BMCR_SPEED_1000 LINE_SPEED_MSB
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#define BMCR_SPEED_100 LINE_SPEED_LSB
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#define BMCR_SPEED_10 0x0000
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#define BMCR_1000FULL (BMCR_SPEED_1000 | DUPLEX_MODE)
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#define BMCR_100FULL (BMCR_SPEED_100 | DUPLEX_MODE)
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#define BMCR_100HALF BMCR_SPEED_100
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#define BMCR_10FULL DUPLEX_MODE
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#define BMCR_10HALF 0x0000
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#define BMSR 0x0001
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#define LINKOK 0x0004
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#define AUTONEG_ENABLE_STS 0x0008
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#define AUTONEG_COMPLETE 0x0020
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#define PHYIDR0 0x0002
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#define PHYIDR1 0x0003
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#define ANAR 0x0004
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#define ANAR_PAUSE 0x0400
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#define ANAR_100FULL 0x0100
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#define ANAR_100HALF 0x0080
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#define ANAR_10FULL 0x0040
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#define ANAR_10HALF 0x0020
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#define ANAR_8023BIT 0x0001
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#define ANLPAR 0x0005
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#define ANER 0x0006
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#define AUX_1000_CTRL 0x0009
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#define ENABLE_1000HALF 0x0100
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#define ENABLE_1000FULL 0x0200
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#define DEFAULT_AUX_1000_CTRL (ENABLE_1000HALF | ENABLE_1000FULL)
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#define AUX_1000_STATUS 0x000A
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#define LP_1000HALF 0x0400
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#define LP_1000FULL 0x0800
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/* Marvell 88E1111 Gigabit PHY Register Definition */
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#define M88_SSR 0x0011
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#define SSR_SPEED_MASK 0xC000
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