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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

This commit is contained in:
Wolfgang Denk 2008-12-30 23:30:47 +01:00
parent 22bab87db1 d9011f9b75
commit f85cd46918
59 changed files with 3668 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
MAINTAINERS
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@ -411,6 +411,10 @@ Rune Torgersen <runet@innovsys.com>
MPC8266ADS MPC8266
Peter Tyser <ptyser@xes-inc.com>
XPEDITE5200 MPC8548
XPEDITE5370 MPC8572
David Updegraff <dave@cray.com>

2
MAKEALL
View File

@ -385,6 +385,8 @@ LIST_85xx=" \
TQM8548 \
TQM8555 \
TQM8560 \
XPEDITE5200 \
XPEDITE5370 \
"
#########################################################################

8
Makefile
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@ -228,6 +228,7 @@ LIBS += drivers/bios_emulator/libatibiosemu.a
LIBS += drivers/block/libblock.a
LIBS += drivers/dma/libdma.a
LIBS += drivers/fpga/libfpga.a
LIBS += drivers/gpio/libgpio.a
LIBS += drivers/hwmon/libhwmon.a
LIBS += drivers/i2c/libi2c.a
LIBS += drivers/input/libinput.a
@ -407,6 +408,7 @@ TAG_SUBDIRS += disk
TAG_SUBDIRS += common
TAG_SUBDIRS += drivers/bios_emulator
TAG_SUBDIRS += drivers/block
TAG_SUBDIRS += drivers/gpio
TAG_SUBDIRS += drivers/hwmon
TAG_SUBDIRS += drivers/i2c
TAG_SUBDIRS += drivers/input
@ -2461,6 +2463,12 @@ TQM8560_config: unconfig
echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
XPEDITE5200_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5200 xes
XPEDITE5370_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes
#########################################################################
## MPC86xx Systems
#########################################################################

9
README
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@ -621,6 +621,8 @@ The following options need to be configured:
CONFIG_CMD_MII * MII utility commands
CONFIG_CMD_NAND * NAND support
CONFIG_CMD_NET bootp, tftpboot, rarpboot
CONFIG_CMD_PCA953X * PCA953x I2C gpio commands
CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
CONFIG_CMD_PCI * pciinfo
CONFIG_CMD_PCMCIA * PCMCIA support
CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network
@ -698,6 +700,13 @@ The following options need to be configured:
Note that if the RTC uses I2C, then the I2C interface
must also be configured. See I2C Support, below.
- GPIO Support:
CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO
CONFIG_PCA953X_INFO - enable pca953x info command
Note that if the GPIO device uses I2C, then the I2C interface
must also be configured. See I2C Support, below.
- Timestamp Support:
When CONFIG_TIMESTAMP is selected, the timestamp

2
board/freescale/mpc8540ads/mpc8540ads.c
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@ -133,7 +133,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

2
board/freescale/mpc8541cds/mpc8541cds.c
View File

@ -308,7 +308,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

2
board/freescale/mpc8548cds/mpc8548cds.c
View File

@ -125,7 +125,7 @@ local_bus_init(void)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & 0x0f) * 2;
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;

2
board/freescale/mpc8555cds/mpc8555cds.c
View File

@ -308,7 +308,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

2
board/freescale/mpc8560ads/mpc8560ads.c
View File

@ -337,7 +337,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

2
board/freescale/mpc8568mds/mpc8568mds.c
View File

@ -188,7 +188,7 @@ local_bus_init(void)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & 0x0f) * 2;
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;

2
board/mpc8540eval/mpc8540eval.c
View File

@ -101,7 +101,7 @@ phys_size_t initdram (int board_type)
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) {
lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;

2
board/pm854/pm854.c
View File

@ -150,7 +150,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

2
board/pm856/pm856.c
View File

@ -306,7 +306,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

2
board/sbc8548/sbc8548.c
View File

@ -126,7 +126,7 @@ local_bus_init(void)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & 0x0f) * 2;
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;

2
board/socrates/socrates.c
View File

@ -156,7 +156,7 @@ void local_bus_init (void)
uint lcrr = CONFIG_SYS_LBC_LCRR;
get_sys_info (&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;
/* Disable PLL bypass for Local Bus Clock >= 66 MHz */

2
board/tqc/tqm85xx/tqm85xx.c
View File

@ -361,7 +361,7 @@ uint get_lbc_clock (void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
sys_info_t sys_info;
ulong clkdiv = lbc->lcrr & 0x0f;
ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
get_sys_info (&sys_info);

57
board/xes/common/Makefile Normal file
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@ -0,0 +1,57 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)board/$(VENDOR)/common)
endif
LIB = $(obj)lib$(VENDOR).a
COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o
COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o
COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o
COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

65
board/xes/common/actl_nand.c Normal file
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@ -0,0 +1,65 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* This driver support NAND devices which have address lines
* connected as ALE and CLE inputs.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <nand.h>
#include <asm/io.h>
/*
* Hardware specific access to control-lines
*/
static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
{
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
IO_ADDR_W = (ulong)this->IO_ADDR_W;
IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
CONFIG_SYS_NAND_ACTL_ALE |
CONFIG_SYS_NAND_ACTL_NCE);
if (ctrl & NAND_CLE)
IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
if (ctrl & NAND_NCE)
IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
this->IO_ADDR_W = (void *)IO_ADDR_W;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
int board_nand_init(struct nand_chip *nand)
{
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = nand_addr_hwcontrol;
nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
return 0;
}

51
board/xes/common/fsl_8572_clk.c Normal file
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@ -0,0 +1,51 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
/*
* Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
*/
unsigned long get_board_sys_clk(ulong dummy)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 gpporcr = gur->gpporcr;
if (gpporcr & 0x10000)
return 66666666;
else
return 50000000;
}
/*
* Return DDR input clock - synchronous with SYSCLK or 66 MHz
*/
unsigned long get_board_ddr_clk(ulong dummy)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
if (ddr_ratio == 0x7)
return get_board_sys_clk(dummy);
return 66666666;
}

93
board/xes/common/fsl_85xx_ddr.c Normal file
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@ -0,0 +1,93 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/mmu.h>
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Initialize and enable DDR ECC */
ddr_enable_ecc(dram_size);
#endif
return dram_size;
}
#if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1)
void board_add_ram_info(int use_default)
{
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
#endif
puts(" (");
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
/* Print interleaving information */
if (ddr1->cs0_config & 0x20000000) {
switch ((ddr1->cs0_config >> 24) & 0xf) {
case 0:
puts("cache line");
break;
case 1:
puts("page");
break;
case 2:
puts("bank");
break;
case 3:
puts("super-bank");
break;
default:
puts("invalid");
break;
}
} else {
puts("no");
}
puts(" interleaving");
#endif
#if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC)
puts(", ");
#endif
#if defined(CONFIG_DDR_ECC)
puts("ECC enabled");
#endif
puts(")");
}
#endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */

379
board/xes/common/fsl_85xx_pci.c Normal file
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@ -0,0 +1,379 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
* Copyright 2007-2008 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <libfdt.h>
#include <fdt_support.h>
extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
extern void fsl_pci_config_unlock(struct pci_controller *hose);
extern void fsl_pci_init(struct pci_controller *hose);
int first_free_busno = 0;
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif
#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif
#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif
#ifdef CONFIG_MPC8572
/* Correlate host/agent POR bits to usable info. Table 4-14 */
struct host_agent_cfg_t {
uchar pcie_root[3];
uchar rio_host;
} host_agent_cfg[8] = {
{{0, 0, 0}, 0},
{{0, 1, 1}, 1},
{{1, 0, 1}, 0},
{{1, 1, 0}, 1},
{{0, 0, 1}, 0},
{{0, 1, 0}, 1},
{{1, 0, 0}, 0},
{{1, 1, 1}, 1}
};
/* Correlate port width POR bits to usable info. Table 4-15 */
struct io_port_cfg_t {
uchar pcie_width[3];
uchar rio_width;
} io_port_cfg[16] = {
{{0, 0, 0}, 0},
{{0, 0, 0}, 0},
{{4, 0, 0}, 0},
{{4, 4, 0}, 0},
{{0, 0, 0}, 0},
{{0, 0, 0}, 0},
{{0, 0, 0}, 4},
{{4, 2, 2}, 0},
{{0, 0, 0}, 0},
{{0, 0, 0}, 0},
{{0, 0, 0}, 0},
{{4, 0, 0}, 4},
{{4, 0, 0}, 4},
{{0, 0, 0}, 4},
{{0, 0, 0}, 4},
{{8, 0, 0}, 0},
};
#elif defined CONFIG_MPC8548
/* Correlate host/agent POR bits to usable info. Table 4-12 */
struct host_agent_cfg_t {
uchar pci_host[2];
uchar pcie_root[1];
uchar rio_host;
} host_agent_cfg[8] = {
{{1, 1}, {0}, 0},
{{1, 1}, {1}, 0},
{{1, 1}, {0}, 1},
{{0, 0}, {0}, 0}, /* reserved */
{{0, 1}, {1}, 0},
{{1, 1}, {1}, 0},
{{0, 1}, {1}, 1},
{{1, 1}, {1}, 1}
};
/* Correlate port width POR bits to usable info. Table 4-13 */
struct io_port_cfg_t {
uchar pcie_width[1];
uchar rio_width;
} io_port_cfg[8] = {
{{0}, 0},
{{0}, 0},
{{0}, 0},
{{4}, 4},
{{4}, 4},
{{0}, 4},
{{0}, 4},
{{8}, 0},
};
#endif
void pci_init_board(void)
{
struct pci_controller *hose;
volatile ccsr_fsl_pci_t *pci;
int width;
int host;
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
struct pci_region *r;
#ifdef CONFIG_PCI1
uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD);
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1;
uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
width = 0; /* Silence compiler warning... */
io_sel &= 0xf; /* Silence compiler warning... */
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
hose = &pci1_hose;
host = host_agent_cfg[host_agent].pci_host[0];
r = hose->regions;
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
pci_32 ? 32 : 64,
pcix ? "PCIX" : "PCI",
pci_spd_norm ? ">=" : "<=",
pcix ? freq * 2 : freq,
host ? "host" : "agent",
pci_arb ? "arbiter" : "external-arbiter");
/* inbound */
r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
(int)&pci->cfg_data);
fsl_pci_init(hose);
/* Unlock inbound PCI configuration cycles */
if (!host)
fsl_pci_config_unlock(hose);
first_free_busno = hose->last_busno + 1;
printf(" PCI1 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
} else {
printf(" PCI1: disabled\n");
}
#elif defined CONFIG_MPC8548
/* PCI1 not present on MPC8572 */
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif
#ifdef CONFIG_PCIE1
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
hose = &pcie1_hose;
host = host_agent_cfg[host_agent].pcie_root[0];
width = io_port_cfg[io_sel].pcie_width[0];
r = hose->regions;
if (width && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
printf("\n PCIE1 connected as %s (x%d)",
host ? "Root Complex" : "End Point", width);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;
debug(" with errors. Clearing. Now 0x%08x",
pci->pme_msg_det);
}
printf("\n");
/* inbound */
r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
(int) &pci->cfg_data);
fsl_pci_init(hose);
/* Unlock inbound PCI configuration cycles */
if (!host)
fsl_pci_config_unlock(hose);
first_free_busno = hose->last_busno + 1;
printf(" PCIE1 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
}
#else
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCIE2
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
hose = &pcie2_hose;
host = host_agent_cfg[host_agent].pcie_root[1];
width = io_port_cfg[io_sel].pcie_width[1];
r = hose->regions;
if (width && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
printf("\n PCIE2 connected as %s (x%d)",
host ? "Root Complex" : "End Point", width);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;
debug(" with errors. Clearing. Now 0x%08x",
pci->pme_msg_det);
}
printf("\n");
/* inbound */
r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
(int)&pci->cfg_data);
fsl_pci_init(hose);
/* Unlock inbound PCI configuration cycles */
if (!host)
fsl_pci_config_unlock(hose);
first_free_busno = hose->last_busno + 1;
printf(" PCIE2 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
}
#else
gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
#endif /* CONFIG_PCIE2 */
#ifdef CONFIG_PCIE3
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
hose = &pcie3_hose;
host = host_agent_cfg[host_agent].pcie_root[2];
width = io_port_cfg[io_sel].pcie_width[2];
r = hose->regions;
if (width && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
printf("\n PCIE3 connected as %s (x%d)",
host ? "Root Complex" : "End Point", width);
if (pci->pme_msg_det) {
pci->pme_msg_det = 0xffffffff;
debug(" with errors. Clearing. Now 0x%08x",
pci->pme_msg_det);
}
printf("\n");
/* inbound */
r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BASE,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
(int)&pci->cfg_data);
fsl_pci_init(hose);
/* Unlock inbound PCI configuration cycles */
if (!host)
fsl_pci_config_unlock(hose);
first_free_busno = hose->last_busno + 1;
printf(" PCIE3 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
}
#else
gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
#endif /* CONFIG_PCIE3 */
}
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose);
void ft_board_pci_setup(void *blob, bd_t *bd)
{
/* TODO - make node name (eg pci0) dynamic */
#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE2
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
#ifdef CONFIG_PCIE3
ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
#endif
}
#endif /* CONFIG_OF_BOARD_SETUP */

55
board/xes/xpedite5200/Makefile Normal file
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#
# Copyright 2008 Extreme Engineering Solutions, Inc.
# Copyright 2004 Freescale Semiconductor.
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

34
board/xes/xpedite5200/config.mk Normal file
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#
# Copyright 2008 Extreme Engineering Solutions, Inc.
# Copyright 2004, 2007 Freescale Semiconductor.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# xpedite5200 board
#
ifndef TEXT_BASE
TEXT_BASE = 0xfff80000
endif
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
PLATFORM_CPPFLAGS += -mrelocatable

91
board/xes/xpedite5200/ddr.c Normal file
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/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
static void
get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
{
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
/* We use soldered memory, but use an SPD EEPROM to describe it.
* The SPD has an unspecified dimm type, but the DDR2 initialization
* code requires a specific type to be specified. This sets the type
* as a standard unregistered SO-DIMM. */
if (spd->dimm_type == 0) {
spd->dimm_type = 0x4;
((uchar *)spd)[63] += 0x4;
}
}
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num)
{
unsigned int i;
if (ctrl_num) {
printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
return;
}
for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
}
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
* - number of chips on bus
* - position of slot
* - DDR1 vs. DDR2?
* - ???
*
* This needs to be determined on a board-by-board basis.
* 0110 3/4 cycle late
* 0111 7/8 cycle late
*/
popts->clk_adjust = 7;
/*
* Factors to consider for CPO:
* - frequency
* - ddr1 vs. ddr2
*/
popts->cpo_override = 9;
/*
* Factors to consider for write data delay:
* - number of DIMMs
*
* 1 = 1/4 clock delay
* 2 = 1/2 clock delay
* 3 = 3/4 clock delay
* 4 = 1 clock delay
* 5 = 5/4 clock delay
* 6 = 3/2 clock delay
*/
popts->write_data_delay = 3;
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
}

51
board/xes/xpedite5200/law.c Normal file
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/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
/*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
struct law_entry law_table[] = {
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#if CONFIG_SYS_PCI1_MEM_PHYS
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1),
#endif
#if CONFIG_SYS_PCI2_MEM_PHYS
SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

85
board/xes/xpedite5200/tlb.c Normal file
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/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* W**G* - NOR flashes */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
/* *I*G* - NAND flash */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1M, 1),
#if CONFIG_PCI1
/* *I*G* - PCI MEM */
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
#endif
#if CONFIG_PCI2
/* *I*G* - PCI MEM */
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
#endif
#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
/* *I*G* - PCI IO */
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_16M, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

145
board/xes/xpedite5200/u-boot.lds Normal file
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/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
* Copyright 2004, 2007-2008 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
*(.text)
*(.got1)
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} :text = 0xffff
. = ADDR(.text) + 0x80000;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
} :bss
. = ALIGN(4);
_end = . ;
PROVIDE (end = .);
}

125
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/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
* Copyright 2004, 2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <pca953x.h>
extern void ft_board_pci_setup(void *blob, bd_t *bd);
int checkboard(void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
char *s;
printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME);
printf(" ");
s = getenv("board_rev");
if (s)
printf("Rev %s, ", s);
s = getenv("serial#");
if (s)
printf("Serial# %s, ", s);
s = getenv("board_cfg");
if (s)
printf("Cfg %s", s);
printf("\n");
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
ecm->eedr = 0xffffffff; /* Clear ecm errors */
ecm->eeer = 0xffffffff; /* Enable ecm errors */
return 0;
}
static void flash_cs_fixup(void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
int flash_sel;
/*
* Print boot dev and swap flash flash chip selects if booted from 2nd
* flash. Swapping chip selects presents user with a common memory
* map regardless of which flash was booted from.
*/
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
CONFIG_SYS_PCA953X_FLASH_PASS_CS));
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
lbc->br0 = CONFIG_SYS_BR1_PRELIM;
lbc->or0 = CONFIG_SYS_OR1_PRELIM;
lbc->br1 = CONFIG_SYS_BR0_PRELIM;
lbc->or1 = CONFIG_SYS_OR0_PRELIM;
}
}
int board_early_init_r(void)
{
/* Initialize PCA9557 devices */
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
/*
* Remap NOR flash region to caching-inhibited
* so that flash can be erased/programmed properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* Invalidate existing TLB entry for NOR flash */
disable_tlb(0);
set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_256M, 1);
flash_cs_fixup();
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
ft_board_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
}
#endif

45
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#
# Copyright 2008 Extreme Engineering Solutions, Inc.
# Copyright 2007 Freescale Semiconductor, Inc.
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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board/xes/xpedite5370/config.mk Normal file
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#
# Copyright 2008 Extreme Engineering Solutions, Inc.
# Copyright 2007-2008 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# xpedite5370 board
#
ifndef TEXT_BASE
TEXT_BASE = 0xfff80000
endif
PLATFORM_RELFLAGS += -mrelocatable
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8572=1

270
board/xes/xpedite5370/ddr.c Normal file
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/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
* Copyright 2008 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
{
i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
sizeof(ddr2_spd_eeprom_t));
}
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num)
{
unsigned int i;
unsigned int i2c_address = 0;
for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
if (ctrl_num == 0)
i2c_address = SPD_EEPROM_ADDRESS1;
if (ctrl_num == 1)
i2c_address = SPD_EEPROM_ADDRESS2;
get_spd(&(ctrl_dimms_spd[i]), i2c_address);
}
}
/*
* There are four board-specific SDRAM timing parameters which must be
* calculated based on the particular PCB artwork. These are:
* 1.) CPO (Read Capture Delay)
* - TIMING_CFG_2 register
* Source: Calculation based on board trace lengths and
* chip-specific internal delays.
* 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
* - TIMING_CFG_2 register
* Source: Calculation based on board trace lengths.
* Unless clock and DQ lanes are very different
* lengths (>2"), this should be set to the nominal value
* of 1/2 clock delay.
* 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
* - DDR_SDRAM_CLK_CNTL register
* Source: Signal Integrity Simulations
* 4.) 2T Timing on Addr/Ctl
* - TIMING_CFG_2 register
* Source: Signal Integrity Simulations
* Usually only needed with heavy load/very high speed (>DDR2-800)
*
* ====== XPedite5370 DDR2-600 read delay calculations ======
*
* See Freescale's App Note AN2583 as refrence. This document also
* contains the chip-specific delays for 8548E, 8572, etc.
*
* For MPC8572E
* Minimum chip delay (Ch 0): 1.372ns
* Maximum chip delay (Ch 0): 2.914ns
* Minimum chip delay (Ch 1): 1.220ns
* Maximum chip delay (Ch 1): 2.595ns
*
* CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
*
* Minimum delay calc (Ch 0):
* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
* 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps
* = 3808ps
* = 3.808ns
*
* Maximum delay calc (Ch 0):
* clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
* 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps
* = 6240ps
* = 6.240ns
*
* Minimum delay calc (Ch 1):
* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
* 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps
* = 3288ps
* = 3.288ns
*
* Maximum delay calc (Ch 1):
* clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
* 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps
* = 5536ps
* = 5.536ns
*
* Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
* This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
* Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
* This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
*
*
* ====== XPedite5370 DDR2-800 read delay calculations ======
*
* See Freescale's App Note AN2583 as refrence. This document also
* contains the chip-specific delays for 8548E, 8572, etc.
*
* For MPC8572E
* Minimum chip delay (Ch 0): 1.372ns
* Maximum chip delay (Ch 0): 2.914ns
* Minimum chip delay (Ch 1): 1.220ns
* Maximum chip delay (Ch 1): 2.595ns
*
* CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
*
* Minimum delay calc (Ch 0):
* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
* 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps
* = 3341ps
* = 3.341ns
*
* Maximum delay calc (Ch 0):
* clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
* 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps
* = 5673ps
* = 5.673ns
*
* Minimum delay calc (Ch 1):
* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
* 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps
* = 2822ps
* = 2.822ns
*
* Maximum delay calc (Ch 1):
* clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
* 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps
* = 4968ps
* = 4.968ns
*
* Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
* This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
* Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
* This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
*
* Write latency (WR_DATA_DELAY) is calculated by doing the following:
*
* The DDR SDRAM specification requires DQS be received no sooner than
* 75% of an SDRAM clock period—and no later than 125% of a clock
* period—from the capturing clock edge of the command/address at the
* SDRAM.
*
* Based on the above tracelengths, the following are calculated:
* Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
* Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
* Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns
* Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns
*
* Difference in arrival time CLK vs. DQS:
* Ch. 0 0.072ns
* Ch. 1 0.138ns
*
* Both of these values are much less than 25% of the clock
* period at DDR2-600 or DDR2-800, so no additional delay is needed over
* the 1/2 cycle which normally aligns the first DQS transition
* exactly WL (CAS latency minus one cycle) after the CAS strobe.
* See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
* terminology corresponds to exactly one clock period delay after
* the CAS strobe. (due to the fact that the "delay" is referenced
* from the *falling* edge of the CLK, just after the rising edge
* which the CAS strobe is latched on.
*/
typedef struct board_memctl_options {
uint16_t datarate_mhz_low;
uint16_t datarate_mhz_high;
uint8_t clk_adjust;
uint8_t cpo_override;
uint8_t write_data_delay;
} board_memctl_options_t;
static struct board_memctl_options bopts_ctrl[][2] = {
{
/* Controller 0 */
{
/* DDR2 600/667 */
.datarate_mhz_low = 500,
.datarate_mhz_high = 750,
.clk_adjust = 5,
.cpo_override = 8,
.write_data_delay = 2,
},
{
/* DDR2 800 */
.datarate_mhz_low = 750,
.datarate_mhz_high = 850,
.clk_adjust = 5,
.cpo_override = 9,
.write_data_delay = 2,
},
},
{
/* Controller 1 */
{
/* DDR2 600/667 */
.datarate_mhz_low = 500,
.datarate_mhz_high = 750,
.clk_adjust = 5,
.cpo_override = 7,
.write_data_delay = 2,
},
{
/* DDR2 800 */
.datarate_mhz_low = 750,
.datarate_mhz_high = 850,
.clk_adjust = 5,
.cpo_override = 8,
.write_data_delay = 2,
},
},
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
sys_info_t sysinfo;
int i;
unsigned int datarate;
get_sys_info(&sysinfo);
datarate = sysinfo.freqDDRBus / 1000 / 1000;
for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
if ((bopts[i].datarate_mhz_low <= datarate) &&
(bopts[i].datarate_mhz_high >= datarate)) {
debug("controller %d:\n", ctrl_num);
debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
debug(" cpo = %d\n", bopts[i].cpo_override);
debug(" write_data_delay = %d\n",
bopts[i].write_data_delay);
popts->clk_adjust = bopts[i].clk_adjust;
popts->cpo_override = bopts[i].cpo_override;
popts->write_data_delay = bopts[i].write_data_delay;
}
}
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
}

54
board/xes/xpedite5370/law.c Normal file
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/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
/*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
#endif
#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
#endif
#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

94
board/xes/xpedite5370/tlb.c Normal file
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/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* W**G* - NOR flashes */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_256M, 1),
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
/* *I*G* - NAND flash */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1M, 1),
#ifdef CONFIG_PCIE1
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
#endif
#ifdef CONFIG_PCIE2
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
#endif
#ifdef CONFIG_PCIE3
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
#endif
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

145
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/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
* Copyright 2007-2008 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
PHDRS
{
text PT_LOAD;
bss PT_LOAD;
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
*(.text)
*(.got1)
} :text
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
} :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
} :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
} :text = 0xffff
. = ADDR(.text) + 0x80000;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
} :bss
. = ALIGN(4);
_end = . ;
PROVIDE (end = .);
}

128
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/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <pca953x.h>
DECLARE_GLOBAL_DATA_PTR;
extern void ft_board_pci_setup(void *blob, bd_t *bd);
int checkboard(void)
{
char *s;
printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
printf(" ");
s = getenv("board_rev");
if (s)
printf("Rev %s, ", s);
s = getenv("serial#");
if (s)
printf("Serial# %s, ", s);
s = getenv("board_cfg");
if (s)
printf("Cfg %s", s);
printf("\n");
return 0;
}
static void flash_cs_fixup(void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
int flash_sel;
/*
* Print boot dev and swap flash flash chip selects if booted from 2nd
* flash. Swapping chip selects presents user with a common memory
* map regardless of which flash was booted from.
*/
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
lbc->br0 = CONFIG_SYS_BR1_PRELIM;
lbc->or0 = CONFIG_SYS_OR1_PRELIM;
lbc->br1 = CONFIG_SYS_BR0_PRELIM;
lbc->or1 = CONFIG_SYS_OR0_PRELIM;
}
}
int board_early_init_r(void)
{
/* Initialize PCA9557 devices */
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
/*
* Remap NOR flash region to caching-inhibited
* so that flash can be erased/programmed properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* Invalidate existing TLB entry for NOR flash */
disable_tlb(0);
set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_256M, 1);
flash_cs_fixup();
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
ft_board_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
}
#endif
#ifdef CONFIG_MP
extern void cpu_mp_lmb_reserve(struct lmb *lmb);
void board_lmb_reserve(struct lmb *lmb)
{
cpu_mp_lmb_reserve(lmb);
}
#endif

31
cpu/mpc85xx/cpu.c
View File

@ -77,8 +77,6 @@ struct cpu_type *identify_cpu(u32 ver)
int checkcpu (void)
{
sys_info_t sysinfo;
uint lcrr; /* local bus clock ratio register */
uint clkdiv; /* clock divider portion of lcrr */
uint pvr, svr;
uint fam;
uint ver;
@ -165,30 +163,11 @@ int checkcpu (void)
break;
}
#if defined(CONFIG_SYS_LBC_LCRR)
lcrr = CONFIG_SYS_LBC_LCRR;
#else
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
lcrr = lbc->lcrr;
}
#endif
clkdiv = lcrr & 0x0f;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
/*
* Yes, the entire PQ38 family use the same
* bit-representation for twice the clock divider values.
*/
clkdiv *= 2;
#endif
printf("LBC:%-4s MHz\n",
strmhz(buf1, sysinfo.freqSystemBus / clkdiv));
} else {
printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
}
if (sysinfo.freqLocalBus > LCRR_CLKDIV)
printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
else
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
sysinfo.freqLocalBus);
#ifdef CONFIG_CPM2
printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));

8
cpu/mpc85xx/fdt.c
View File

@ -28,11 +28,12 @@
#include <fdt_support.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
extern void ft_qe_setup(void *blob);
#ifdef CONFIG_MP
#include "mp.h"
DECLARE_GLOBAL_DATA_PTR;
void ft_fixup_cpu(void *blob, u64 memory_limit)
{
@ -231,6 +232,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
"clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
"bus-frequency", gd->lbc_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,elbc",
"bus-frequency", gd->lbc_clk, 1);
#ifdef CONFIG_QE
ft_qe_setup(blob);
#endif

1
cpu/mpc85xx/release.S
View File

@ -157,6 +157,7 @@ __secondary_start_page:
mfspr r0,SPRN_PIR
stw r0,ENTRY_PIR(r10)
mtspr IVPR,r12
/*
* Coming here, we know the cpu has one TLB mapping in TLB1[0]
* which maps 0xfffff000-0xffffffff one-to-one. We set up a

27
cpu/mpc85xx/speed.c
View File

@ -28,6 +28,7 @@
#include <common.h>
#include <ppc_asm.tmpl>
#include <asm/processor.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -37,6 +38,7 @@ void get_sys_info (sys_info_t * sysInfo)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint plat_ratio,e500_ratio,half_freqSystemBus;
uint lcrr_div;
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
@ -60,6 +62,30 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
}
#endif
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
}
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
/*
* Yes, the entire PQ38 family use the same
* bit-representation for twice the clock divider values.
*/
lcrr_div *= 2;
#endif
sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
} else {
/* In case anyone cares what the unknown value is */
sysInfo->freqLocalBus = lcrr_div;
}
}
@ -82,6 +108,7 @@ int get_clocks (void)
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
gd->mem_clk = sys_info.freqDDRBus;
gd->lbc_clk = sys_info.freqLocalBus;
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,

16
cpu/mpc85xx/start.S
View File

@ -184,19 +184,19 @@ _start_e500:
mtspr DBCR0,r0
#endif
/* create a temp mapping in AS=1 to the boot window */
/* create a temp mapping in AS=1 to the 4M boot window */
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
/* Align the mapping to 16MB */
lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@h
ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@l
lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
lis r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
mtspr MAS0,r6
mtspr MAS1,r7

34
cpu/mpc85xx/tlb.c
View File

@ -26,6 +26,11 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#ifdef CONFIG_ADDR_MAP
#include <addr_map.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
void set_tlb(u8 tlb, u32 epn, u64 rpn,
u8 perms, u8 wimge,
@ -47,6 +52,11 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
mtspr(MAS7, _mas7);
#endif
asm volatile("isync;msync;tlbwe;isync");
#ifdef CONFIG_ADDR_MAP
if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel);
#endif
}
void disable_tlb(u8 esel)
@ -67,6 +77,11 @@ void disable_tlb(u8 esel)
mtspr(MAS7, _mas7);
#endif
asm volatile("isync;msync;tlbwe;isync");
#ifdef CONFIG_ADDR_MAP
if (gd->flags & GD_FLG_RELOC)
addrmap_set_entry(0, 0, 0, esel);
#endif
}
void invalidate_tlb(u8 tlb)
@ -91,6 +106,25 @@ void init_tlbs(void)
return ;
}
#ifdef CONFIG_ADDR_MAP
void init_addr_map(void)
{
int i;
for (i = 0; i < num_tlb_entries; i++) {
if (tlb_table[i].tlb == 0)
continue;
addrmap_set_entry(tlb_table[i].epn,
tlb_table[i].rpn,
(1UL << ((tlb_table[i].tsize * 2) + 10)),
tlb_table[i].esel);
}
return ;
}
#endif
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
unsigned int tlb_size;

21
cpu/mpc86xx/cpu.c
View File

@ -39,8 +39,6 @@ checkcpu(void)
uint pvr, svr;
uint ver;
uint major, minor;
uint lcrr; /* local bus clock ratio register */
uint clkdiv; /* clock divider portion of lcrr */
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
@ -100,22 +98,11 @@ checkcpu(void)
printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
#if defined(CONFIG_SYS_LBC_LCRR)
lcrr = CONFIG_SYS_LBC_LCRR;
#else
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
lcrr = lbc->lcrr;
}
#endif
clkdiv = lcrr & 0x0f;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
printf("LBC:%4lu MHz\n",
sysinfo.freqSystemBus / 1000000 / clkdiv);
if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
printf("LBC:%4lu MHz\n", sysinfo.freqLocalBus / 1000000);
} else {
printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02x)\n",
sysinfo.freqLocalBus);
}
puts(" L2: ");

9
cpu/mpc86xx/fdt.c
View File

@ -13,6 +13,8 @@
DECLARE_GLOBAL_DATA_PTR;
DECLARE_GLOBAL_DATA_PTR;
void ft_cpu_setup(void *blob, bd_t *bd)
{
#if (CONFIG_NUM_CPUS > 1)
@ -29,6 +31,13 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
#if defined(CONFIG_MPC8641)
do_fixup_by_compat_u32(blob, "fsl,mpc8641-localbus",
"bus-frequency", gd->lbc_clk, 1);
#endif
do_fixup_by_compat_u32(blob, "fsl,elbc",
"bus-frequency", gd->lbc_clk, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) \

19
cpu/mpc86xx/speed.c
View File

@ -28,6 +28,7 @@
#include <common.h>
#include <mpc86xx.h>
#include <asm/processor.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -39,6 +40,7 @@ void get_sys_info(sys_info_t *sysInfo)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint plat_ratio, e600_ratio;
uint lcrr_div;
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
@ -90,6 +92,22 @@ void get_sys_info(sys_info_t *sysInfo)
sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
break;
}
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
{
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
}
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);
} else {
/* In case anyone cares what the unknown value is */
sysInfo->freqLocalBus = lcrr_div;
}
}
@ -105,6 +123,7 @@ int get_clocks(void)
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
gd->lbc_clk = sys_info.freqLocalBus;
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,

47
drivers/gpio/Makefile Normal file
View File

@ -0,0 +1,47 @@
#
# Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libgpio.a
COBJS-$(CONFIG_PCA953X) += pca953x.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
########################################################################

227
drivers/gpio/pca953x.c Normal file
View File

@ -0,0 +1,227 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Driver for NXP's 4 and 8 bit I2C gpio expanders (eg pca9537, pca9557, etc)
* TODO: support additional devices with more than 8-bits GPIO
*/
#include <common.h>
#include <i2c.h>
#include <pca953x.h>
/* Default to an address that hopefully won't corrupt other i2c devices */
#ifndef CONFIG_SYS_I2C_PCA953X_ADDR
#define CONFIG_SYS_I2C_PCA953X_ADDR (~0)
#endif
enum {
PCA953X_CMD_INFO,
PCA953X_CMD_DEVICE,
PCA953X_CMD_OUTPUT,
PCA953X_CMD_INPUT,
PCA953X_CMD_INVERT,
};
/*
* Modify masked bits in register
*/
static int pca953x_reg_write(uint8_t chip, uint addr, uint mask, uint data)
{
uint8_t val;
if (i2c_read(chip, addr, 1, &val, 1))
return -1;
val &= ~mask;
val |= data;
return i2c_write(chip, addr, 1, &val, 1);
}
/*
* Set output value of IO pins in 'mask' to corresponding value in 'data'
* 0 = low, 1 = high
*/
int pca953x_set_val(uint8_t chip, uint mask, uint data)
{
return pca953x_reg_write(chip, PCA953X_OUT, mask, data);
}
/*
* Set read polarity of IO pins in 'mask' to corresponding value in 'data'
* 0 = read pin value, 1 = read inverted pin value
*/
int pca953x_set_pol(uint8_t chip, uint mask, uint data)
{
return pca953x_reg_write(chip, PCA953X_POL, mask, data);
}
/*
* Set direction of IO pins in 'mask' to corresponding value in 'data'
* 0 = output, 1 = input
*/
int pca953x_set_dir(uint8_t chip, uint mask, uint data)
{
return pca953x_reg_write(chip, PCA953X_CONF, mask, data);
}
/*
* Read current logic level of all IO pins
*/
int pca953x_get_val(uint8_t chip)
{
uint8_t val;
if (i2c_read(chip, 0, 1, &val, 1))
return -1;
return (int)val;
}
#ifdef CONFIG_CMD_PCA953X
#ifdef CONFIG_CMD_PCA953X_INFO
/*
* Display pca953x information
*/
static int pca953x_info(uint8_t chip)
{
int i;
uint8_t data;
printf("pca953x@ 0x%x:\n\n", chip);
printf("gpio pins: 76543210\n");
printf("-------------------\n");
if (i2c_read(chip, PCA953X_CONF, 1, &data, 1))
return -1;
printf("conf: ");
for (i = 7; i >= 0; i--)
printf("%c", data & (1 << i) ? 'i' : 'o');
printf("\n");
if (i2c_read(chip, PCA953X_POL, 1, &data, 1))
return -1;
printf("invert: ");
for (i = 7; i >= 0; i--)
printf("%c", data & (1 << i) ? '1' : '0');
printf("\n");
if (i2c_read(chip, PCA953X_IN, 1, &data, 1))
return -1;
printf("input: ");
for (i = 7; i >= 0; i--)
printf("%c", data & (1 << i) ? '1' : '0');
printf("\n");
if (i2c_read(chip, PCA953X_OUT, 1, &data, 1))
return -1;
printf("output: ");
for (i = 7; i >= 0; i--)
printf("%c", data & (1 << i) ? '1' : '0');
printf("\n");
return 0;
}
#endif /* CONFIG_CMD_PCA953X_INFO */
cmd_tbl_t cmd_pca953x[] = {
U_BOOT_CMD_MKENT(device, 3, 0, (void *)PCA953X_CMD_DEVICE, "", ""),
U_BOOT_CMD_MKENT(output, 4, 0, (void *)PCA953X_CMD_OUTPUT, "", ""),
U_BOOT_CMD_MKENT(input, 3, 0, (void *)PCA953X_CMD_INPUT, "", ""),
U_BOOT_CMD_MKENT(invert, 4, 0, (void *)PCA953X_CMD_INVERT, "", ""),
#ifdef CONFIG_CMD_PCA953X_INFO
U_BOOT_CMD_MKENT(info, 2, 0, (void *)PCA953X_CMD_INFO, "", ""),
#endif
};
int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR;
int val;
ulong ul_arg2 = 0;
ulong ul_arg3 = 0;
cmd_tbl_t *c;
c = find_cmd_tbl(argv[1], cmd_pca953x, ARRAY_SIZE(cmd_pca953x));
/* All commands but "device" require 'maxargs' arguments */
if (!c || !((argc == (c->maxargs)) ||
(((int)c->cmd == PCA953X_CMD_DEVICE) &&
(argc == (c->maxargs - 1))))) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
/* arg2 used as chip number or pin number */
if (argc > 2)
ul_arg2 = simple_strtoul(argv[2], NULL, 16);
/* arg3 used as pin or invert value */
if (argc > 3)
ul_arg3 = simple_strtoul(argv[3], NULL, 16) & 0x1;
switch ((int)c->cmd) {
#ifdef CONFIG_CMD_PCA953X_INFO
case PCA953X_CMD_INFO:
return pca953x_info(chip);
#endif
case PCA953X_CMD_DEVICE:
if (argc == 3)
chip = (uint8_t)ul_arg2;
printf("Current device address: 0x%x\n", chip);
return 0;
case PCA953X_CMD_INPUT:
pca953x_set_dir(chip, (1 << ul_arg2),
PCA953X_DIR_IN << ul_arg2);
val = (pca953x_get_val(chip) & (1 << ul_arg2)) != 0;
printf("chip 0x%02x, pin 0x%lx = %d\n", chip, ul_arg2, val);
return val;
case PCA953X_CMD_OUTPUT:
pca953x_set_dir(chip, (1 << ul_arg2),
(PCA953X_DIR_OUT << ul_arg2));
return pca953x_set_val(chip, (1 << ul_arg2),
(ul_arg3 << ul_arg2));
case PCA953X_CMD_INVERT:
return pca953x_set_pol(chip, (1 << ul_arg2),
(ul_arg3 << ul_arg2));
default:
/* We should never get here */
return 1;
}
}
U_BOOT_CMD(
pca953x, 5, 1, do_pca953x,
"pca953x - pca953x gpio access\n",
"device [dev]\n"
" - show or set current device address\n"
#ifdef CONFIG_CMD_PCA953X_INFO
"pca953x info\n"
" - display info for current chip\n"
#endif
"pca953x output pin 0|1\n"
" - set pin as output and drive low or high\n"
"pca953x invert pin 0|1\n"
" - disable/enable polarity inversion for reads\n"
"pca953x intput pin\n"
" - set pin as input and read value\n"
);
#endif /* CONFIG_CMD_PCA953X */

6
drivers/mtd/nand/fsl_elbc_nand.c
View File

@ -718,7 +718,7 @@ static void fsl_elbc_ctrl_init(void)
int board_nand_init(struct nand_chip *nand)
{
struct fsl_elbc_mtd *priv;
uint32_t br, or;
uint32_t br = 0, or = 0;
if (!elbc_ctrl) {
fsl_elbc_ctrl_init();
@ -737,11 +737,13 @@ int board_nand_init(struct nand_chip *nand)
* if we could pass more than one datum to the NAND driver...
*/
for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R);
br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
(br & or & BR_BA) == (phys_addr_t)nand->IO_ADDR_R)
(br & or & BR_BA) == BR_PHYS_ADDR(base_addr))
break;
}

29
drivers/pci/fsl_pci_init.c
View File

@ -37,6 +37,11 @@ DECLARE_GLOBAL_DATA_PTR;
#include <pci.h>
#include <asm/immap_fsl_pci.h>
/* Freescale-specific PCI config registers */
#define FSL_PCI_PBFR 0x44
#define FSL_PCIE_CAP_ID 0x4c
#define FSL_PCIE_CFG_RDY 0x4b0
void pciauto_prescan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus);
void pciauto_postscan_setup_bridge(struct pci_controller *hose,
@ -306,6 +311,30 @@ void fsl_pci_init(struct pci_controller *hose)
}
}
/* Enable inbound PCI config cycles for agent/endpoint interface */
void fsl_pci_config_unlock(struct pci_controller *hose)
{
pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
u8 agent;
u8 pcie_cap;
u16 pbfr;
pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
if (!agent)
return;
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
if (pcie_cap != 0x0) {
/* PCIe - set CFG_READY bit of Configuration Ready Register */
pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
} else {
/* PCI - clear ACL bit of PBFR */
pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
pbfr &= ~0x20;
pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
}
}
#ifdef CONFIG_OF_BOARD_SETUP
#include <libfdt.h>
#include <fdt_support.h>

5
include/asm-ppc/fsl_lbc.h
View File

@ -300,7 +300,10 @@
#define LCRR_EADC_2 0x00020000
#define LCRR_EADC_3 0x00030000
#define LCRR_EADC_4 0x00000000
#define LCRR_CLKDIV 0x0000000F
/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
* should always be zero on older parts that have a four bit CLKDIV.
*/
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004

3
include/asm-ppc/global_data.h
View File

@ -89,6 +89,9 @@ typedef struct global_data {
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536)
u32 sdhc_clk;
#endif
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
u32 lbc_clk;
#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
u32 i2c1_clk;
u32 i2c2_clk;

12
include/asm-ppc/io.h
View File

@ -10,6 +10,10 @@
#include <linux/config.h>
#include <asm/byteorder.h>
#ifdef CONFIG_ADDR_MAP
#include <addr_map.h>
#endif
#define SIO_CONFIG_RA 0x398
#define SIO_CONFIG_RD 0x399
@ -287,7 +291,11 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
#ifdef CONFIG_ADDR_MAP
return (void *)(addrmap_phys_to_virt(paddr));
#else
return (void *)((unsigned long)paddr);
#endif
}
/*
@ -300,7 +308,11 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
static inline phys_addr_t virt_to_phys(void * vaddr)
{
#ifdef CONFIG_ADDR_MAP
return addrmap_virt_to_phys(vaddr);
#else
return (phys_addr_t)((unsigned long)vaddr);
#endif
}
#endif

3
include/asm-ppc/mmu.h
View File

@ -431,6 +431,9 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
extern void disable_tlb(u8 esel);
extern void invalidate_tlb(u8 tlb);
extern void init_tlbs(void);
#ifdef CONFIG_ADDR_MAP
extern void init_addr_map(void);
#endif
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \

546
include/configs/XPEDITE5200.h Normal file
View File

@ -0,0 +1,546 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
* Copyright 2004-2008 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* xpedite5200 board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8548 1
#define CONFIG_XPEDITE5200 1
#define CONFIG_SYS_BOARD_NAME "XPedite5200"
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCI1 1 /* PCI controller 1 */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* DDR config
*/
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x54
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_CLK_FREQ 66666666
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS 1
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
/*
* Diagnostics
*/
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
/*
* Memory map
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
* 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
* 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
* 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
* 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
*/
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
/*
* NAND flash configuration
*/
#define CONFIG_SYS_NAND_BASE 0xef800000
#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_NAND_ACTL
#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
#define CONFIG_SYS_NAND_ACTL_DELAY 25
/*
* NOR flash configuration
*/
#define CONFIG_SYS_FLASH_BASE 0xfc000000
#define CONFIG_SYS_FLASH_BASE2 0xf8000000
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
{0xfbf40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
/*
* Chip select configuration
*/
/* NOR Flash 0 on CS0 */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
BR_PS_16 | \
BR_V)
#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_8)
/* NOR Flash 1 on CS1 */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
BR_PS_16 | \
BR_V)
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
/* NAND flash on CS2 */
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
BR_PS_8 | \
BR_V)
/* NAND flash on CS2 */
#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
OR_GPCM_BCTLD | \
OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV4 | \
OR_GPCM_SCY_4 | \
OR_GPCM_TRLX | \
OR_GPCM_EHTR)
/* NAND flash on CS3 */
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
BR_PS_8 | \
BR_V)
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
/*
* Use L1 as initial stack
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
#define CONFIG_SYS_INIT_RAM_END 0x4000
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* Use the HUSH parser
*/
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
* Pass open firmware flat tree
*/
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
#define CONFIG_SYS_64BIT_VSPRINTF 1
#define CONFIG_SYS_64BIT_STRTOUL 1
/*
* I2C
*/
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
/* I2C EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
/* I2C RTC */
#define CONFIG_RTC_M41T11 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
/* GPIO */
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
/* PCA957 @ 0x18 */
#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
#define CONFIG_SYS_PCA953X_FLASH_WP 0x20
#define CONFIG_SYS_PCA953X_MONARCH 0x40
#define CONFIG_SYS_PCA953X_EREADY 0x80
/* PCA957 @ 0x19 */
#define CONFIG_SYS_PCA953X_P14_IO0 0x01
#define CONFIG_SYS_PCA953X_P14_IO1 0x02
#define CONFIG_SYS_PCA953X_P14_IO2 0x04
#define CONFIG_SYS_PCA953X_P14_IO3 0x08
#define CONFIG_SYS_PCA953X_P14_IO4 0x10
#define CONFIG_SYS_PCA953X_P14_IO5 0x20
#define CONFIG_SYS_PCA953X_P14_IO6 0x40
#define CONFIG_SYS_PCA953X_P14_IO7 0x80
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
/*
* Networking options
*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC1_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define TSEC2_FLAGS TSEC_GIGABIT
#define TSEC2_PHY_ADDR 2
#define TSEC2_PHYIDX 0
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#define TSEC3_FLAGS TSEC_GIGABIT
#define TSEC3_PHY_ADDR 3
#define TSEC3_PHYIDX 0
#define CONFIG_HAS_ETH2
#define CONFIG_TSEC4 1
#define CONFIG_TSEC4_NAME "eTSEC4"
#define TSEC4_FLAGS TSEC_GIGABIT
#define TSEC4_PHY_ADDR 4
#define TSEC4_PHYIDX 0
#define CONFIG_HAS_ETH3
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
/*
* Command configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
#define CONFIG_PANIC_HANG /* do not reset board on panic */
#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_FIT 1
#define CONFIG_FIT_VERBOSE 1
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/*
* For booting Linux, the board info and command line data
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
* Environment Configuration
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
/*
* Flash memory map:
* fff80000 - ffffffff Pri U-Boot (512 KB)
* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
* fff00000 - fff3ffff Pri FDT (256KB)
* fef00000 - ffefffff Pri OS image (16MB)
* fc000000 - feefffff Pri OS Use/Filesystem (47MB)
*
* fbf80000 - fbffffff Sec U-Boot (512 KB)
* fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
* fbf00000 - fbf3ffff Sec FDT (256KB)
* faf00000 - fbefffff Sec OS image (16MB)
* f8000000 - faefffff Sec OS Use/Filesystem (47MB)
*/
#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000)
#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
#define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000)
#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
#define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000)
#define CONFIG_PROG_UBOOT1 \
"$download_cmd $loadaddr $ubootfile; " \
"if test $? -eq 0; then " \
"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
"if test $? -ne 0; then " \
"echo PROGRAM FAILED; " \
"else; " \
"echo PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_UBOOT2 \
"$download_cmd $loadaddr $ubootfile; " \
"if test $? -eq 0; then " \
"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
"if test $? -ne 0; then " \
"echo PROGRAM FAILED; " \
"else; " \
"echo PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_BOOT_OS_NET \
"$download_cmd $osaddr $osfile; " \
"if test $? -eq 0; then " \
"if test -n $fdtaddr; then " \
"$download_cmd $fdtaddr $fdtfile; " \
"if test $? -eq 0; then " \
"bootm $osaddr - $fdtaddr; " \
"else; " \
"echo FDT DOWNLOAD FAILED; " \
"fi; " \
"else; " \
"bootm $osaddr; " \
"fi; " \
"else; " \
"echo OS DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_OS1 \
"$download_cmd $osaddr $osfile; " \
"if test $? -eq 0; then " \
"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
"if test $? -ne 0; then " \
"echo OS PROGRAM FAILED; " \
"else; " \
"echo OS PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo OS DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_OS2 \
"$download_cmd $osaddr $osfile; " \
"if test $? -eq 0; then " \
"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
"if test $? -ne 0; then " \
"echo OS PROGRAM FAILED; " \
"else; " \
"echo OS PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo OS DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_FDT1 \
"$download_cmd $fdtaddr $fdtfile; " \
"if test $? -eq 0; then " \
"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
"if test $? -ne 0; then " \
"echo FDT PROGRAM FAILED; " \
"else; " \
"echo FDT PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo FDT DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_FDT2 \
"$download_cmd $fdtaddr $fdtfile; " \
"if test $? -eq 0; then " \
"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
"if test $? -ne 0; then " \
"echo FDT PROGRAM FAILED; " \
"else; " \
"echo FDT PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo FDT DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_EXTRA_ENV_SETTINGS \
"autoload=yes\0" \
"download_cmd=tftp\0" \
"console_args=console=ttyS0,115200\0" \
"root_args=root=/dev/nfs rw\0" \
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
"osfile=/home/user/uImage-XPedite5200\0" \
"fdtfile=/home/user/xpedite5200.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \
"loadaddr=0x1000000\0" \
"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
"prog_os1="CONFIG_PROG_OS1"\0" \
"prog_os2="CONFIG_PROG_OS2"\0" \
"prog_fdt1="CONFIG_PROG_FDT1"\0" \
"prog_fdt2="CONFIG_PROG_FDT2"\0" \
"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
"bootcmd_flash1=run set_bootargs; " \
"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
"bootcmd_flash2=run set_bootargs; " \
"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
"bootcmd=run bootcmd_flash1\0"
#endif /* __CONFIG_H */

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/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
* Copyright 2007-2008 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* xpedite5370 board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8572 1
#define CONFIG_XPEDITE5370 1
#define CONFIG_SYS_BOARD_NAME "XPedite5370"
#define CONFIG_NUM_CPUS 2 /* 2 Cores */
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCIE1 1 /* PCIE controler 1 */
#define CONFIG_PCIE2 1 /* PCIE controler 2 */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
/*
* DDR config
*/
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS 1
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
/*
* Diagnostics
*/
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
/*
* Memory map
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
* 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
* 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
* 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
*/
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
/*
* NAND flash configuration
*/
#define CONFIG_SYS_NAND_BASE 0xef800000
#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
/*
* NOR flash configuration
*/
#define CONFIG_SYS_FLASH_BASE 0xf8000000
#define CONFIG_SYS_FLASH_BASE2 0xf0000000
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
{0xf7f40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
/*
* Chip select configuration
*/
/* NOR Flash 0 on CS0 */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
BR_PS_16 | \
BR_V)
#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
OR_GPCM_CSNT | \
OR_GPCM_XACS | \
OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_8 | \
OR_GPCM_TRLX | \
OR_GPCM_EHTR | \
OR_GPCM_EAD)
/* NOR Flash 1 on CS1 */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
BR_PS_16 | \
BR_V)
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
/* NAND flash on CS2 */
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
(2<<BR_DECC_SHIFT) | \
BR_PS_8 | \
BR_MS_FCM | \
BR_V)
/* NAND flash on CS2 */
#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
OR_FCM_PGS | \
OR_FCM_CSCT | \
OR_FCM_CST | \
OR_FCM_CHT | \
OR_FCM_SCY_1 | \
OR_FCM_TRLX | \
OR_FCM_EHTR)
/* NAND flash on CS3 */
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
(2<<BR_DECC_SHIFT) | \
BR_PS_8 | \
BR_MS_FCM | \
BR_V)
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
/*
* Use L1 as initial stack
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
#define CONFIG_SYS_INIT_RAM_END 0x00004000
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* Use the HUSH parser
*/
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
* Pass open firmware flat tree
*/
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
#define CONFIG_SYS_64BIT_VSPRINTF 1
#define CONFIG_SYS_64BIT_STRTOUL 1
/*
* I2C
*/
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
/* PEX8518 slave I2C interface */
#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
/* I2C DS1631 temperature sensor */
#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
#define CONFIG_DTT_DS1621
#define CONFIG_DTT_SENSORS { 0 }
/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
/* I2C RTC */
#define CONFIG_RTC_M41T11 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
/* GPIO/EEPROM/SRAM */
#define CONFIG_DS4510
#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
/* GPIO */
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
/*
* PU = pulled high, PD = pulled low
* I = input, O = output, IO = input/output
*/
/* PCA9557 @ 0x18*/
#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
/* PCA9557 @ 0x1c*/
#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
/* PCA9557 @ 0x1e*/
#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
/* PCA9557 @ 0x1f */
#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* PCIE1 - VPX P1 */
#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
/* PCIE2 - PEX8518 */
#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
/*
* Networking options
*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_NET_MULTI 1
#define CONFIG_TSEC_TBI
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_ETHPRIME "eTSEC2"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_PHY_ADDR 2
#define TSEC2_PHYIDX 0
#define CONFIG_HAS_ETH1
/*
* Command configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DS4510
#define CONFIG_CMD_DS4510_INFO
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
#define CONFIG_PANIC_HANG /* do not reset board on panic */
#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_FIT 1
#define CONFIG_FIT_VERBOSE 1
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
/*
* For booting Linux, the board info and command line data
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
* Environment Configuration
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
/*
* Flash memory map:
* fff80000 - ffffffff Pri U-Boot (512 KB)
* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
* fff00000 - fff3ffff Pri FDT (256KB)
* fef00000 - ffefffff Pri OS image (16MB)
* f8000000 - feefffff Pri OS Use/Filesystem (111MB)
*
* f7f80000 - f7ffffff Sec U-Boot (512 KB)
* f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
* f7f00000 - f7f3ffff Sec FDT (256KB)
* f6f00000 - f7efffff Sec OS image (16MB)
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
*/
#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
#define CONFIG_PROG_UBOOT1 \
"$download_cmd $loadaddr $ubootfile; " \
"if test $? -eq 0; then " \
"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
"if test $? -ne 0; then " \
"echo PROGRAM FAILED; " \
"else; " \
"echo PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_UBOOT2 \
"$download_cmd $loadaddr $ubootfile; " \
"if test $? -eq 0; then " \
"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
"if test $? -ne 0; then " \
"echo PROGRAM FAILED; " \
"else; " \
"echo PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_BOOT_OS_NET \
"$download_cmd $osaddr $osfile; " \
"if test $? -eq 0; then " \
"if test -n $fdtaddr; then " \
"$download_cmd $fdtaddr $fdtfile; " \
"if test $? -eq 0; then " \
"bootm $osaddr - $fdtaddr; " \
"else; " \
"echo FDT DOWNLOAD FAILED; " \
"fi; " \
"else; " \
"bootm $osaddr; " \
"fi; " \
"else; " \
"echo OS DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_OS1 \
"$download_cmd $osaddr $osfile; " \
"if test $? -eq 0; then " \
"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
"if test $? -ne 0; then " \
"echo OS PROGRAM FAILED; " \
"else; " \
"echo OS PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo OS DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_OS2 \
"$download_cmd $osaddr $osfile; " \
"if test $? -eq 0; then " \
"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
"if test $? -ne 0; then " \
"echo OS PROGRAM FAILED; " \
"else; " \
"echo OS PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo OS DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_FDT1 \
"$download_cmd $fdtaddr $fdtfile; " \
"if test $? -eq 0; then " \
"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
"if test $? -ne 0; then " \
"echo FDT PROGRAM FAILED; " \
"else; " \
"echo FDT PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo FDT DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_FDT2 \
"$download_cmd $fdtaddr $fdtfile; " \
"if test $? -eq 0; then " \
"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
"if test $? -ne 0; then " \
"echo FDT PROGRAM FAILED; " \
"else; " \
"echo FDT PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo FDT DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_EXTRA_ENV_SETTINGS \
"autoload=yes\0" \
"download_cmd=tftp\0" \
"console_args=console=ttyS0,115200\0" \
"root_args=root=/dev/nfs rw\0" \
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
"osfile=/home/user/uImage-XPedite5370\0" \
"fdtfile=/home/user/xpedite5370.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \
"loadaddr=0x1000000\0" \
"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
"prog_os1="CONFIG_PROG_OS1"\0" \
"prog_os2="CONFIG_PROG_OS2"\0" \
"prog_fdt1="CONFIG_PROG_FDT1"\0" \
"prog_fdt2="CONFIG_PROG_FDT2"\0" \
"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
"bootcmd_flash1=run set_bootargs; " \
"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
"bootcmd_flash2=run set_bootargs; " \
"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
"bootcmd=run bootcmd_flash1\0"
#endif /* __CONFIG_H */

20
include/configs/sbc8548.h
View File

@ -399,25 +399,16 @@
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC1"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC2"
#define CONFIG_TSEC4
#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC3_PHY_ADDR 2
#define TSEC4_PHY_ADDR 3
#define TSEC1_PHY_ADDR 0x19
#define TSEC2_PHY_ADDR 0x1a
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
@ -464,6 +455,7 @@
/*
* Miscellaneous configurable options
*/
#define CONFIG_CMDLINE_EDITING /* undef to save memory */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
@ -507,10 +499,6 @@
#define CONFIG_ETHADDR 02:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
#define CONFIG_HAS_ETH3
#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.0.55

1
include/e500.h
View File

@ -13,6 +13,7 @@ typedef struct
unsigned long freqProcessor;
unsigned long freqSystemBus;
unsigned long freqDDRBus;
unsigned long freqLocalBus;
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */

1
include/mpc86xx.h
View File

@ -84,6 +84,7 @@
typedef struct {
unsigned long freqProcessor;
unsigned long freqSystemBus;
unsigned long freqLocalBus;
} MPC86xx_SYS_INFO;
#define l1icache_enable icache_enable

39
include/pca953x.h Normal file
View File

@ -0,0 +1,39 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __PCA953X_H_
#define __PCA953X_H_
#define PCA953X_IN 0x00
#define PCA953X_OUT 0x01
#define PCA953X_POL 0x02
#define PCA953X_CONF 0x03
#define PCA953X_OUT_LOW 0
#define PCA953X_OUT_HIGH 1
#define PCA953X_POL_NORMAL 0
#define PCA953X_POL_INVERT 1
#define PCA953X_DIR_OUT 0
#define PCA953X_DIR_IN 1
int pca953x_set_val(u8 chip, uint mask, uint data);
int pca953x_set_pol(u8 chip, uint mask, uint data);
int pca953x_set_dir(u8 chip, uint mask, uint data);
int pca953x_get_val(u8 chip);
#endif /* __PCA953X_H_ */

8
lib_ppc/board.c
View File

@ -75,6 +75,10 @@
#include <keyboard.h>
#endif
#ifdef CONFIG_ADDR_MAP
#include <asm/mmu.h>
#endif
#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
extern int update_flash_size (int flash_size);
#endif
@ -694,6 +698,10 @@ void board_init_r (gd_t *id, ulong dest_addr)
*/
trap_init (dest_addr);
#if defined(CONFIG_ADDR_MAP) && defined(CONFIG_E500)
init_addr_map();
#endif
#if defined(CONFIG_BOARD_EARLY_INIT_R)
board_early_init_r ();
#endif