ColdFire: Added MCF5275 cpu support.
Signed-off-by: Matthew Fettke <mfettke@videon-central.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com> Acked-by: John Rigby <jrigby@freescale.com>
This commit is contained in:
Matthew Fettke
John Rigby
parent
44e5b9edab
commit
f71d9d91a2
1
CREDITS
1
CREDITS
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@ -431,6 +431,7 @@ D: Support for EP82xxM
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N: Art Shipkowski
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E: art@videon-central.com
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D: Support for NetSilicon NS7520
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D: Support for ColdFire MCF5275
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N: Michal Simek
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E: monstr@monstr.eu
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@ -30,6 +30,7 @@ is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
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is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
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is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
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is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
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is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
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is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
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@ -47,6 +48,9 @@ endif
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ifneq (,$(findstring CONFIG_M5272,$(is5272)))
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PLATFORM_CPPFLAGS += -mcpu=5272
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endif
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ifneq (,$(findstring CONFIG_M5275,$(is5275)))
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PLATFORM_CPPFLAGS += -mcpu=5275
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endif
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ifneq (,$(findstring CONFIG_M5282,$(is5282)))
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PLATFORM_CPPFLAGS += -mcpu=5282
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endif
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@ -6,6 +6,9 @@
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* (C) Copyright 2005
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* BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
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*
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* MCF5275 additions
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* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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@ -180,6 +183,69 @@ int watchdog_init(void)
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#endif /* #ifdef CONFIG_M5272 */
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#ifdef CONFIG_M5275
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int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
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{
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volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
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udelay(1000);
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rcm->rcr = RCM_RCR_SOFTRST;
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/* we don't return! */
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return 0;
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};
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int checkcpu(void)
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{
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char buf[32];
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printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
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strmhz(buf, CFG_CLK));
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return 0;
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};
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#if defined(CONFIG_WATCHDOG)
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/* Called by macro WATCHDOG_RESET */
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void watchdog_reset(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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wdt->wsr = 0x5555;
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wdt->wsr = 0xAAAA;
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}
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int watchdog_disable(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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wdt->wsr = 0x5555; /* reset watchdog counter */
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wdt->wsr = 0xAAAA;
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wdt->wcr = 0; /* disable watchdog timer */
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puts("WATCHDOG:disabled\n");
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return (0);
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}
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int watchdog_init(void)
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{
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volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
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wdt->wcr = 0; /* disable watchdog */
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/* set timeout and enable watchdog */
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wdt->wmr =
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((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
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wdt->wsr = 0x5555; /* reset watchdog counter */
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wdt->wsr = 0xAAAA;
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puts("WATCHDOG:enabled\n");
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return (0);
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}
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#endif /* #ifdef CONFIG_WATCHDOG */
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#endif /* #ifdef CONFIG_M5275 */
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#ifdef CONFIG_M5282
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int checkcpu(void)
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{
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@ -10,6 +10,9 @@
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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* Hayden Fraser (Hayden.Fraser@freescale.com)
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*
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* MCF5275 additions
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* Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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@ -245,6 +248,114 @@ void uart_port_conf(void)
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}
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#endif /* #if defined(CONFIG_M5272) */
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#if defined(CONFIG_M5275)
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(void)
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{
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/* if we come from RAM we assume the CPU is
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* already initialized.
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*/
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#ifndef CONFIG_MONITOR_IS_IN_RAM
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volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
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volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
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volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
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/* Kill watchdog so we can initialize the PLL */
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wdog_reg->wcr = 0;
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/* Memory Controller: */
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/* Flash */
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csctrl_reg->ar0 = CFG_AR0_PRELIM;
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csctrl_reg->cr0 = CFG_CR0_PRELIM;
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csctrl_reg->mr0 = CFG_MR0_PRELIM;
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#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
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csctrl_reg->ar1 = CFG_AR1_PRELIM;
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csctrl_reg->cr1 = CFG_CR1_PRELIM;
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csctrl_reg->mr1 = CFG_MR1_PRELIM;
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#endif
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#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
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csctrl_reg->ar2 = CFG_AR2_PRELIM;
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csctrl_reg->cr2 = CFG_CR2_PRELIM;
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csctrl_reg->mr2 = CFG_MR2_PRELIM;
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#endif
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#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
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csctrl_reg->ar3 = CFG_AR3_PRELIM;
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csctrl_reg->cr3 = CFG_CR3_PRELIM;
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csctrl_reg->mr3 = CFG_MR3_PRELIM;
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#endif
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#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
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csctrl_reg->ar4 = CFG_AR4_PRELIM;
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csctrl_reg->cr4 = CFG_CR4_PRELIM;
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csctrl_reg->mr4 = CFG_MR4_PRELIM;
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#endif
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#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
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csctrl_reg->ar5 = CFG_AR5_PRELIM;
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csctrl_reg->cr5 = CFG_CR5_PRELIM;
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csctrl_reg->mr5 = CFG_MR5_PRELIM;
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#endif
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#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
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csctrl_reg->ar6 = CFG_AR6_PRELIM;
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csctrl_reg->cr6 = CFG_CR6_PRELIM;
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csctrl_reg->mr6 = CFG_MR6_PRELIM;
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#endif
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#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
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csctrl_reg->ar7 = CFG_AR7_PRELIM;
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csctrl_reg->cr7 = CFG_CR7_PRELIM;
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csctrl_reg->mr7 = CFG_MR7_PRELIM;
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#endif
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#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
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#ifdef CONFIG_FSL_I2C
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gpio_reg->par_feci2c = 0x000F;
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#endif
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/* enable instruction cache now */
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icache_enable();
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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return (0);
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}
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void uart_port_conf(void)
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{
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volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
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/* Setup Ports: */
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switch (CFG_UART_PORT) {
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case 0:
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gpio->par_uart |= UART0_ENABLE_MASK;
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break;
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case 1:
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gpio->par_uart |= UART1_ENABLE_MASK;
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break;
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case 2:
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gpio->par_uart |= UART2_ENABLE_MASK;
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break;
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}
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}
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#endif /* #if defined(CONFIG_M5275) */
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#if defined(CONFIG_M5282)
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/*
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* Breath some life into the CPU...
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@ -59,7 +59,7 @@ void dtimer_intr_setup(void)
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#endif /* CONFIG_MCFTMR */
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#endif /* CONFIG_M5272 */
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#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
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#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
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int interrupt_init(void)
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{
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volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
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@ -81,7 +81,7 @@ void dtimer_intr_setup(void)
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intp->imrl0 &= ~CFG_TMRINTR_MASK;
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}
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#endif /* CONFIG_MCFTMR */
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#endif /* CONFIG_M5282 | CONFIG_M5271 */
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#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
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#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
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int interrupt_init(void)
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@ -64,8 +64,18 @@ int get_clocks (void)
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#endif /* CONFIG_M5249 || CONFIG_M5253 */
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#if defined(CONFIG_M5275)
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volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
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/* Setup PLL */
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pll->syncr = 0x01080000;
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while (!(pll->synsr & FMPLL_SYNSR_LOCK));
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pll->syncr = 0x01000000;
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while (!(pll->synsr & FMPLL_SYNSR_LOCK));
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#endif
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gd->cpu_clk = CFG_CLK;
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#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
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#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
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gd->bus_clk = gd->cpu_clk / 2;
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#else
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gd->bus_clk = gd->cpu_clk;
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@ -197,6 +197,17 @@ _copy_flash:
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_after_flash_copy:
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#endif
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#ifdef CONFIG_M5275
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/* Initialize IPSBAR */
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move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
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move.l %d0, 0x40000000
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/* movec %d0, %MBAR */
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/* Initialize RAMBAR: locate SRAM and validate it */
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move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
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movec %d0, %RAMBAR1
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#endif
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#if 0
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/* invalidate and disable cache */
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move.l #0x01000000, %d0 /* Invalidate cache cmd */
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@ -394,6 +405,25 @@ icache_enable:
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rts
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#endif
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#if defined(CONFIG_M5275)
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/*
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* Instruction cache only
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*/
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.globl icache_enable
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icache_enable:
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move.l #0x01400000, %d0 /* Invalidate cache cmd */
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movec %d0, %CACR /* Invalidate cache */
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move.l #0x0000c000, %d0 /* Setup SDRAM caching */
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movec %d0, %ACR0 /* Enable cache */
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move.l #0x00000000, %d0 /* No other caching */
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movec %d0, %ACR1 /* Enable cache */
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move.l #0x80400100, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Enable cache */
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moveq #1, %d0
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move.l %d0, icache_state
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rts
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#endif
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#ifdef CONFIG_M5282
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.globl icache_enable
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icache_enable:
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@ -180,6 +180,30 @@
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#endif
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#endif /* CONFIG_M5272 */
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#ifdef CONFIG_M5275
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#include <asm/immap_5275.h>
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#include <asm/m5275.h>
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#define CFG_FEC0_IOBASE (MMAP_FEC0)
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#define CFG_FEC1_IOBASE (MMAP_FEC1)
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#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x40))
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#define CFG_INTR_BASE (MMAP_INTC0)
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#define CFG_NUM_IRQS (192)
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/* Timer */
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR3)
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#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
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#define CFG_TMRINTR_NO (INT0_LO_DTMR3)
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#define CFG_TMRINTR_MASK (INTC_IPRL_INT22)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (0x1E)
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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#endif /* CONFIG_M5275 */
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#ifdef CONFIG_M5282
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#include <asm/immap_5282.h>
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#include <asm/m5282.h>
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@ -0,0 +1,469 @@
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/*
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* MCF5274/5 Internal Memory Map
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*
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* Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
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* Based on work Copyright (c) 2003 Josef Baumgartner
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* <josef.baumgartner@telex.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __IMMAP_5275__
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#define __IMMAP_5275__
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#define MMAP_SCM (CFG_MBAR + 0x00000000)
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#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
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#define MMAP_FBCS (CFG_MBAR + 0x00000080)
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#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
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#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
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#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
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#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
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#define MMAP_UART0 (CFG_MBAR + 0x00000200)
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#define MMAP_UART1 (CFG_MBAR + 0x00000240)
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#define MMAP_UART2 (CFG_MBAR + 0x00000280)
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#define MMAP_I2C (CFG_MBAR + 0x00000300)
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#define MMAP_QSPI (CFG_MBAR + 0x00000340)
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#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
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#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
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#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
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#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
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#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
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#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
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#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
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#define MMAP_FEC0 (CFG_MBAR + 0x00001000)
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#define MMAP_FEC0FIFO (CFG_MBAR + 0x00001400)
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#define MMAP_FEC1 (CFG_MBAR + 0x00001800)
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#define MMAP_FEC1FIFO (CFG_MBAR + 0x00001C00)
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#define MMAP_GPIO (CFG_MBAR + 0x00100000)
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#define MMAP_RCM (CFG_MBAR + 0x00110000)
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#define MMAP_CCM (CFG_MBAR + 0x00110004)
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#define MMAP_PLL (CFG_MBAR + 0x00120000)
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#define MMAP_EPORT (CFG_MBAR + 0x00130000)
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#define MMAP_WDOG (CFG_MBAR + 0x00140000)
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#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
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#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
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#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
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#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
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#define MMAP_MDHA (CFG_MBAR + 0x00190000)
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#define MMAP_RNG (CFG_MBAR + 0x001A0000)
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#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
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#define MMAP_USB (CFG_MBAR + 0x001C0000)
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#define MMAP_PWM0 (CFG_MBAR + 0x001D0000)
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/* System configuration registers
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*/
|
||||
typedef struct sys_ctrl {
|
||||
u32 ipsbar;
|
||||
u32 res1;
|
||||
u32 rambar;
|
||||
u32 res2;
|
||||
u8 crsr;
|
||||
u8 cwcr;
|
||||
u8 lpicr;
|
||||
u8 cwsr;
|
||||
u8 res3[8];
|
||||
u32 mpark;
|
||||
u8 mpr;
|
||||
u8 res4[3];
|
||||
u8 pacr0;
|
||||
u8 pacr1;
|
||||
u8 pacr2;
|
||||
u8 pacr3;
|
||||
u8 pacr4;
|
||||
u8 res5;
|
||||
u8 pacr5;
|
||||
u8 pacr6;
|
||||
u8 pacr7;
|
||||
u8 res6;
|
||||
u8 pacr8;
|
||||
u8 res7;
|
||||
u8 gpacr;
|
||||
u8 res8[3];
|
||||
} sysctrl_t;
|
||||
/* SDRAM controller registers, offset: 0x040
|
||||
*/
|
||||
typedef struct sdram_ctrl {
|
||||
u32 sdmr;
|
||||
u32 sdcr;
|
||||
u32 sdcfg1;
|
||||
u32 sdcfg2;
|
||||
u32 sdbar0;
|
||||
u32 sdbmr0;
|
||||
u32 sdbar1;
|
||||
u32 sdbmr1;
|
||||
} sdramctrl_t;
|
||||
|
||||
/* Chip select module registers, offset: 0x080
|
||||
*/
|
||||
typedef struct cs_ctlr {
|
||||
u16 ar0;
|
||||
u16 res1;
|
||||
u32 mr0;
|
||||
u16 res2;
|
||||
u16 cr0;
|
||||
u16 ar1;
|
||||
u16 res3;
|
||||
u32 mr1;
|
||||
u16 res4;
|
||||
u16 cr1;
|
||||
u16 ar2;
|
||||
u16 res5;
|
||||
u32 mr2;
|
||||
u16 res6;
|
||||
u16 cr2;
|
||||
u16 ar3;
|
||||
u16 res7;
|
||||
u32 mr3;
|
||||
u16 res8;
|
||||
u16 cr3;
|
||||
u16 ar4;
|
||||
u16 res9;
|
||||
u32 mr4;
|
||||
u16 res10;
|
||||
u16 cr4;
|
||||
u16 ar5;
|
||||
u16 res11;
|
||||
u32 mr5;
|
||||
u16 res12;
|
||||
u16 cr5;
|
||||
u16 ar6;
|
||||
u16 res13;
|
||||
u32 mr6;
|
||||
u16 res14;
|
||||
u16 cr6;
|
||||
u16 ar7;
|
||||
u16 res15;
|
||||
u32 mr7;
|
||||
u16 res16;
|
||||
u16 cr7;
|
||||
} csctrl_t;
|
||||
|
||||
/* DMA module registers, offset 0x100
|
||||
*/
|
||||
typedef struct dma_ctrl {
|
||||
u32 sar;
|
||||
u32 dar;
|
||||
u32 dsrbcr;
|
||||
u32 dcr;
|
||||
} dma_t;
|
||||
|
||||
/* QSPI module registers, offset 0x340
|
||||
*/
|
||||
typedef struct qspi_ctrl {
|
||||
u16 qmr;
|
||||
u8 res1[2];
|
||||
u16 qdlyr;
|
||||
u8 res2[2];
|
||||
u16 qwr;
|
||||
u8 res3[2];
|
||||
u16 qir;
|
||||
u8 res4[2];
|
||||
u16 qar;
|
||||
u8 res5[2];
|
||||
u16 qdr;
|
||||
u8 res6[2];
|
||||
} qspi_t;
|
||||
|
||||
/* Interrupt module registers, offset 0xc00
|
||||
*/
|
||||
typedef struct int_ctrl {
|
||||
u32 iprh0;
|
||||
u32 iprl0;
|
||||
u32 imrh0;
|
||||
u32 imrl0;
|
||||
u32 frch0;
|
||||
u32 frcl0;
|
||||
u8 irlr;
|
||||
u8 iacklpr;
|
||||
u8 res1[0x26];
|
||||
u8 icr0[64]; /* No ICR0, done this way for readability */
|
||||
u8 res2[0x60];
|
||||
u8 swiack0;
|
||||
u8 res3[3];
|
||||
u8 Lniack0_1;
|
||||
u8 res4[3];
|
||||
u8 Lniack0_2;
|
||||
u8 res5[3];
|
||||
u8 Lniack0_3;
|
||||
u8 res6[3];
|
||||
u8 Lniack0_4;
|
||||
u8 res7[3];
|
||||
u8 Lniack0_5;
|
||||
u8 res8[3];
|
||||
u8 Lniack0_6;
|
||||
u8 res9[3];
|
||||
u8 Lniack0_7;
|
||||
u8 res10[3];
|
||||
} int0_t;
|
||||
|
||||
/* GPIO port registers
|
||||
*/
|
||||
typedef struct gpio_ctrl {
|
||||
/* Port Output Data Registers */
|
||||
u8 podr_res1[4];
|
||||
u8 podr_busctl;
|
||||
u8 podr_addr;
|
||||
u8 podr_res2[2];
|
||||
u8 podr_cs;
|
||||
u8 podr_res3;
|
||||
u8 podr_fec0h;
|
||||
u8 podr_fec0l;
|
||||
u8 podr_feci2c;
|
||||
u8 podr_qspi;
|
||||
u8 podr_sdram;
|
||||
u8 podr_timerh;
|
||||
u8 podr_timerl;
|
||||
u8 podr_uartl;
|
||||
u8 podr_fec1h;
|
||||
u8 podr_fec1l;
|
||||
u8 podr_bs;
|
||||
u8 podr_res4;
|
||||
u8 podr_usbh;
|
||||
u8 podr_usbl;
|
||||
u8 podr_uarth;
|
||||
u8 podr_res5[3];
|
||||
/* Port Data Direction Registers */
|
||||
u8 pddr_res1[4];
|
||||
u8 pddr_busctl;
|
||||
u8 pddr_addr;
|
||||
u8 pddr_res2[2];
|
||||
u8 pddr_cs;
|
||||
u8 pddr_res3;
|
||||
u8 pddr_fec0h;
|
||||
u8 pddr_fec0l;
|
||||
u8 pddr_feci2c;
|
||||
u8 pddr_qspi;
|
||||
u8 pddr_sdram;
|
||||
u8 pddr_timerh;
|
||||
u8 pddr_timerl;
|
||||
u8 pddr_uartl;
|
||||
u8 pddr_fec1h;
|
||||
u8 pddr_fec1l;
|
||||
u8 pddr_bs;
|
||||
u8 pddr_res4;
|
||||
u8 pddr_usbh;
|
||||
u8 pddr_usbl;
|
||||
u8 pddr_uarth;
|
||||
u8 pddr_res5[3];
|
||||
/* Port Pin Data/Set Registers */
|
||||
u8 ppdsdr_res1[4];
|
||||
u8 ppdsdr_busctl;
|
||||
u8 ppdsdr_addr;
|
||||
u8 ppdsdr_res2[2];
|
||||
u8 ppdsdr_cs;
|
||||
u8 ppdsdr_res3;
|
||||
u8 ppdsdr_fec0h;
|
||||
u8 ppdsdr_fec0l;
|
||||
u8 ppdsdr_feci2c;
|
||||
u8 ppdsdr_qspi;
|
||||
u8 ppdsdr_sdram;
|
||||
u8 ppdsdr_timerh;
|
||||
u8 ppdsdr_timerl;
|
||||
u8 ppdsdr_uartl;
|
||||
u8 ppdsdr_fec1h;
|
||||
u8 ppdsdr_fec1l;
|
||||
u8 ppdsdr_bs;
|
||||
u8 ppdsdr_res4;
|
||||
u8 ppdsdr_usbh;
|
||||
u8 ppdsdr_usbl;
|
||||
u8 ppdsdr_uarth;
|
||||
u8 ppdsdr_res5[3];
|
||||
/* Port Clear Output Data Registers */
|
||||
u8 pclrr_res1[4];
|
||||
u8 pclrr_busctl;
|
||||
u8 pclrr_addr;
|
||||
u8 pclrr_res2[2];
|
||||
u8 pclrr_cs;
|
||||
u8 pclrr_res3;
|
||||
u8 pclrr_fec0h;
|
||||
u8 pclrr_fec0l;
|
||||
u8 pclrr_feci2c;
|
||||
u8 pclrr_qspi;
|
||||
u8 pclrr_sdram;
|
||||
u8 pclrr_timerh;
|
||||
u8 pclrr_timerl;
|
||||
u8 pclrr_uartl;
|
||||
u8 pclrr_fec1h;
|
||||
u8 pclrr_fec1l;
|
||||
u8 pclrr_bs;
|
||||
u8 pclrr_res4;
|
||||
u8 pclrr_usbh;
|
||||
u8 pclrr_usbl;
|
||||
u8 pclrr_uarth;
|
||||
u8 pclrr_res5[3];
|
||||
/* Pin Assignment Registers */
|
||||
u8 par_addr;
|
||||
u8 par_cs;
|
||||
u16 par_busctl;
|
||||
u8 par_res1[2];
|
||||
u16 par_usb;
|
||||
u8 par_fec0hl;
|
||||
u8 par_fec1hl;
|
||||
u16 par_timer;
|
||||
u16 par_uart;
|
||||
u16 par_qspi;
|
||||
u16 par_sdram;
|
||||
u16 par_feci2c;
|
||||
u8 par_bs;
|
||||
u8 par_res2[3];
|
||||
} gpio_t;
|
||||
|
||||
|
||||
/* PWM module registers
|
||||
*/
|
||||
typedef struct pwm_ctrl {
|
||||
u8 pwcr0;
|
||||
u8 res1[3];
|
||||
u8 pwcr1;
|
||||
u8 res2[3];
|
||||
u8 pwcr2;
|
||||
u8 res3[7];
|
||||
u8 pwwd0;
|
||||
u8 res4[3];
|
||||
u8 pwwd1;
|
||||
u8 res5[3];
|
||||
u8 pwwd2;
|
||||
u8 res6[7];
|
||||
} pwm_t;
|
||||
|
||||
/* Watchdog registers
|
||||
*/
|
||||
typedef struct wdog_ctrl {
|
||||
u16 wcr;
|
||||
u16 wmr;
|
||||
u16 wcntr;
|
||||
u16 wsr;
|
||||
u8 res4[114];
|
||||
} wdog_t;
|
||||
|
||||
/* USB module registers
|
||||
*/
|
||||
typedef struct usb {
|
||||
u16 res1;
|
||||
u16 fnr;
|
||||
u16 res2;
|
||||
u16 fnmr;
|
||||
u16 res3;
|
||||
u16 rfmr;
|
||||
u16 res4;
|
||||
u16 rfmmr;
|
||||
u8 res5[3];
|
||||
u8 far;
|
||||
u32 asr;
|
||||
u32 drr1;
|
||||
u32 drr2;
|
||||
u16 res6;
|
||||
u16 specr;
|
||||
u16 res7;
|
||||
u16 ep0sr;
|
||||
u32 iep0cfg;
|
||||
u32 oep0cfg;
|
||||
u32 ep1cfg;
|
||||
u32 ep2cfg;
|
||||
u32 ep3cfg;
|
||||
u32 ep4cfg;
|
||||
u32 ep5cfg;
|
||||
u32 ep6cfg;
|
||||
u32 ep7cfg;
|
||||
u32 ep0ctl;
|
||||
u16 res8;
|
||||
u16 ep1ctl;
|
||||
u16 res9;
|
||||
u16 ep2ctl;
|
||||
u16 res10;
|
||||
u16 ep3ctl;
|
||||
u16 res11;
|
||||
u16 ep4ctl;
|
||||
u16 res12;
|
||||
u16 ep5ctl;
|
||||
u16 res13;
|
||||
u16 ep6ctl;
|
||||
u16 res14;
|
||||
u16 ep7ctl;
|
||||
u32 ep0isr;
|
||||
u16 res15;
|
||||
u16 ep1isr;
|
||||
u16 res16;
|
||||
u16 ep2isr;
|
||||
u16 res17;
|
||||
u16 ep3isr;
|
||||
u16 res18;
|
||||
u16 ep4isr;
|
||||
u16 res19;
|
||||
u16 ep5isr;
|
||||
u16 res20;
|
||||
u16 ep6isr;
|
||||
u16 res21;
|
||||
u16 ep7isr;
|
||||
u32 ep0imr;
|
||||
u16 res22;
|
||||
u16 ep1imr;
|
||||
u16 res23;
|
||||
u16 ep2imr;
|
||||
u16 res24;
|
||||
u16 ep3imr;
|
||||
u16 res25;
|
||||
u16 ep4imr;
|
||||
u16 res26;
|
||||
u16 ep5imr;
|
||||
u16 res27;
|
||||
u16 ep6imr;
|
||||
u16 res28;
|
||||
u16 ep7imr;
|
||||
u32 ep0dr;
|
||||
u32 ep1dr;
|
||||
u32 ep2dr;
|
||||
u32 ep3dr;
|
||||
u32 ep4dr;
|
||||
u32 ep5dr;
|
||||
u32 ep6dr;
|
||||
u32 ep7dr;
|
||||
u16 res29;
|
||||
u16 ep0dpr;
|
||||
u16 res30;
|
||||
u16 ep1dpr;
|
||||
u16 res31;
|
||||
u16 ep2dpr;
|
||||
u16 res32;
|
||||
u16 ep3dpr;
|
||||
u16 res33;
|
||||
u16 ep4dpr;
|
||||
u16 res34;
|
||||
u16 ep5dpr;
|
||||
u16 res35;
|
||||
u16 ep6dpr;
|
||||
u16 res36;
|
||||
u16 ep7dpr;
|
||||
u8 res37[788];
|
||||
u8 cfgram[1024];
|
||||
} usb_t;
|
||||
|
||||
/* PLL module registers
|
||||
*/
|
||||
typedef struct pll_ctrl {
|
||||
u32 syncr;
|
||||
u32 synsr;
|
||||
} pll_t;
|
||||
|
||||
typedef struct rcm {
|
||||
u8 rcr;
|
||||
u8 rsr;
|
||||
} rcm_t;
|
||||
|
||||
#endif /* __IMMAP_5275__ */
|
||||
|
|
@ -0,0 +1,241 @@
|
|||
/*
|
||||
* MCF5275 Internal Memory Map
|
||||
*
|
||||
* Copyright (C) 2003-2004, Greg Ungerer (gerg@snapgear.com)
|
||||
* Copyright (C) 2004-2008 Arthur Shipkowski (art@videon-central.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __M5275_H__
|
||||
#define __M5275_H__
|
||||
|
||||
/*
|
||||
* Define the 5275 SIM register set addresses. These are similar,
|
||||
* but not quite identical to the 5282 registers and offsets.
|
||||
*/
|
||||
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
|
||||
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
|
||||
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
|
||||
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
|
||||
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
|
||||
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
|
||||
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
|
||||
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
|
||||
#define MCFINTC_IRLR 0x18 /* */
|
||||
#define MCFINTC_IACKL 0x19 /* */
|
||||
#define MCFINTC_ICR0 0x40 /* Base ICR register */
|
||||
|
||||
#define MCF_GPIO_PAR_UART 0x10007c
|
||||
#define UART0_ENABLE_MASK 0x000f
|
||||
#define UART1_ENABLE_MASK 0x00f0
|
||||
#define UART2_ENABLE_MASK 0x3f00
|
||||
|
||||
#define MCF_GPIO_PAR_FECI2C 0x100082
|
||||
#define PAR_SDA_ENABLE_MASK 0x0003
|
||||
#define PAR_SCL_ENABLE_MASK 0x000c
|
||||
|
||||
#define MCFSIM_WRRR 0x140000
|
||||
#define MCFSIM_SDCR 0x40
|
||||
|
||||
/*********************************************************************
|
||||
* SDRAM Controller (SDRAMC)
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SDRAMC_SDMR (*(vuint32*)(void*)(&__IPSBAR[0x000040]))
|
||||
#define MCF_SDRAMC_SDCR (*(vuint32*)(void*)(&__IPSBAR[0x000044]))
|
||||
#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(void*)(&__IPSBAR[0x000048]))
|
||||
#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
|
||||
#define MCF_SDRAMC_SDBAR0 (*(vuint32*)(void*)(&__IPSBAR[0x000050]))
|
||||
#define MCF_SDRAMC_SDBAR1 (*(vuint32*)(void*)(&__IPSBAR[0x000058]))
|
||||
#define MCF_SDRAMC_SDMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000054]))
|
||||
#define MCF_SDRAMC_SDMR1 (*(vuint32*)(void*)(&__IPSBAR[0x00005C]))
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDMR */
|
||||
#define MCF_SDRAMC_SDMR_CMD (0x00010000)
|
||||
#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
|
||||
#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
|
||||
#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
|
||||
#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDCR */
|
||||
#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
|
||||
#define MCF_SDRAMC_SDCR_IREF (0x00000004)
|
||||
#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10)
|
||||
#define MCF_SDRAMC_SDCR_DQP_BP (0x00008000)
|
||||
#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
|
||||
#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
|
||||
#define MCF_SDRAMC_SDCR_REF (0x10000000)
|
||||
#define MCF_SDRAMC_SDCR_CKE (0x40000000)
|
||||
#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
|
||||
#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
|
||||
#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
|
||||
#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
|
||||
#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
|
||||
#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
|
||||
#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
|
||||
#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
|
||||
#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
|
||||
#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
|
||||
#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
|
||||
#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDBARn */
|
||||
#define MCF_SDRAMC_SDBARn_BASE(x) (((x)&0x00003FFF)<<18)
|
||||
#define MCF_SDRAMC_SDBARn_BA(x) ((x)&0xFFFF0000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDMRn */
|
||||
#define MCF_SDRAMC_SDMRn_V (0x00000001)
|
||||
#define MCF_SDRAMC_SDMRn_WP (0x00000080)
|
||||
#define MCF_SDRAMC_SDMRn_MASK(x) (((x)&0x00003FFF)<<18)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_4G (0xFFFF0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_2G (0x7FFF0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_1G (0x3FFF0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_1024M (0x3FFF0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_512M (0x1FFF0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_256M (0x0FFF0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_128M (0x07FF0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_64M (0x03FF0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_32M (0x01FF0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_16M (0x00FF0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_8M (0x007F0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_4M (0x003F0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_2M (0x001F0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_1M (0x000F0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_1024K (0x000F0000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_512K (0x00070000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_256K (0x00030000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_128K (0x00010000)
|
||||
#define MCF_SDRAMC_SDMRn_BAM_64K (0x00000000)
|
||||
|
||||
/*********************************************************************
|
||||
* Interrupt Controller (INTC)
|
||||
********************************************************************/
|
||||
#define INT0_LO_RSVD0 (0)
|
||||
#define INT0_LO_EPORT1 (1)
|
||||
#define INT0_LO_EPORT2 (2)
|
||||
#define INT0_LO_EPORT3 (3)
|
||||
#define INT0_LO_EPORT4 (4)
|
||||
#define INT0_LO_EPORT5 (5)
|
||||
#define INT0_LO_EPORT6 (6)
|
||||
#define INT0_LO_EPORT7 (7)
|
||||
#define INT0_LO_SCM (8)
|
||||
#define INT0_LO_DMA0 (9)
|
||||
#define INT0_LO_DMA1 (10)
|
||||
#define INT0_LO_DMA2 (11)
|
||||
#define INT0_LO_DMA3 (12)
|
||||
#define INT0_LO_UART0 (13)
|
||||
#define INT0_LO_UART1 (14)
|
||||
#define INT0_LO_UART2 (15)
|
||||
#define INT0_LO_RSVD1 (16)
|
||||
#define INT0_LO_I2C (17)
|
||||
#define INT0_LO_QSPI (18)
|
||||
#define INT0_LO_DTMR0 (19)
|
||||
#define INT0_LO_DTMR1 (20)
|
||||
#define INT0_LO_DTMR2 (21)
|
||||
#define INT0_LO_DTMR3 (22)
|
||||
#define INT0_LO_FEC0_TXF (23)
|
||||
#define INT0_LO_FEC0_TXB (24)
|
||||
#define INT0_LO_FEC0_UN (25)
|
||||
#define INT0_LO_FEC0_RL (26)
|
||||
#define INT0_LO_FEC0_RXF (27)
|
||||
#define INT0_LO_FEC0_RXB (28)
|
||||
#define INT0_LO_FEC0_MII (29)
|
||||
#define INT0_LO_FEC0_LC (30)
|
||||
#define INT0_LO_FEC0_HBERR (31)
|
||||
#define INT0_HI_FEC0_GRA (32)
|
||||
#define INT0_HI_FEC0_EBERR (33)
|
||||
#define INT0_HI_FEC0_BABT (34)
|
||||
#define INT0_HI_FEC0_BABR (35)
|
||||
#define INT0_HI_PIT0 (36)
|
||||
#define INT0_HI_PIT1 (37)
|
||||
#define INT0_HI_PIT2 (38)
|
||||
#define INT0_HI_PIT3 (39)
|
||||
#define INT0_HI_RNG (40)
|
||||
#define INT0_HI_SKHA (41)
|
||||
#define INT0_HI_MDHA (42)
|
||||
#define INT0_HI_USB (43)
|
||||
#define INT0_HI_USB_EP0 (44)
|
||||
#define INT0_HI_USB_EP1 (45)
|
||||
#define INT0_HI_USB_EP2 (46)
|
||||
#define INT0_HI_USB_EP3 (47)
|
||||
/* 48-63 Reserved */
|
||||
|
||||
/* 0-22 Reserved */
|
||||
#define INT1_LO_FEC1_TXF (23)
|
||||
#define INT1_LO_FEC1_TXB (24)
|
||||
#define INT1_LO_FEC1_UN (25)
|
||||
#define INT1_LO_FEC1_RL (26)
|
||||
#define INT1_LO_FEC1_RXF (27)
|
||||
#define INT1_LO_FEC1_RXB (28)
|
||||
#define INT1_LO_FEC1_MII (29)
|
||||
#define INT1_LO_FEC1_LC (30)
|
||||
#define INT1_LO_FEC1_HBERR (31)
|
||||
#define INT1_HI_FEC1_GRA (32)
|
||||
#define INT1_HI_FEC1_EBERR (33)
|
||||
#define INT1_HI_FEC1_BABT (34)
|
||||
#define INT1_HI_FEC1_BABR (35)
|
||||
/* 36-63 Reserved */
|
||||
|
||||
/* Bit definitions and macros for INTC_IPRL */
|
||||
#define INTC_IPRL_INT31 (0x80000000)
|
||||
#define INTC_IPRL_INT30 (0x40000000)
|
||||
#define INTC_IPRL_INT29 (0x20000000)
|
||||
#define INTC_IPRL_INT28 (0x10000000)
|
||||
#define INTC_IPRL_INT27 (0x08000000)
|
||||
#define INTC_IPRL_INT26 (0x04000000)
|
||||
#define INTC_IPRL_INT25 (0x02000000)
|
||||
#define INTC_IPRL_INT24 (0x01000000)
|
||||
#define INTC_IPRL_INT23 (0x00800000)
|
||||
#define INTC_IPRL_INT22 (0x00400000)
|
||||
#define INTC_IPRL_INT21 (0x00200000)
|
||||
#define INTC_IPRL_INT20 (0x00100000)
|
||||
#define INTC_IPRL_INT19 (0x00080000)
|
||||
#define INTC_IPRL_INT18 (0x00040000)
|
||||
#define INTC_IPRL_INT17 (0x00020000)
|
||||
#define INTC_IPRL_INT16 (0x00010000)
|
||||
#define INTC_IPRL_INT15 (0x00008000)
|
||||
#define INTC_IPRL_INT14 (0x00004000)
|
||||
#define INTC_IPRL_INT13 (0x00002000)
|
||||
#define INTC_IPRL_INT12 (0x00001000)
|
||||
#define INTC_IPRL_INT11 (0x00000800)
|
||||
#define INTC_IPRL_INT10 (0x00000400)
|
||||
#define INTC_IPRL_INT9 (0x00000200)
|
||||
#define INTC_IPRL_INT8 (0x00000100)
|
||||
#define INTC_IPRL_INT7 (0x00000080)
|
||||
#define INTC_IPRL_INT6 (0x00000040)
|
||||
#define INTC_IPRL_INT5 (0x00000020)
|
||||
#define INTC_IPRL_INT4 (0x00000010)
|
||||
#define INTC_IPRL_INT3 (0x00000008)
|
||||
#define INTC_IPRL_INT2 (0x00000004)
|
||||
#define INTC_IPRL_INT1 (0x00000002)
|
||||
#define INTC_IPRL_INT0 (0x00000001)
|
||||
|
||||
/* Bit definitions and macros for RCR */
|
||||
#define RCM_RCR_FRCRSTOUT (0x40)
|
||||
#define RCM_RCR_SOFTRST (0x80)
|
||||
|
||||
#define FMPLL_SYNSR_LOCK (0x00000008)
|
||||
|
||||
#endif /* __M5275_H__ */
|
||||
Loading…
Reference in New Issue