ppc4xx: Add EEPROM write protection for PLU405 boards + misc. updates
- add EEPROM write protection for esd PLU405 boards. - initialize NAND GPIOs - use correct io accessors - cleanup Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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@ -109,8 +109,8 @@ int misc_init_f (void)
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int misc_init_r (void)
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int misc_init_r (void)
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{
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{
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volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
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unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
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volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
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unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
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unsigned char *dst;
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unsigned char *dst;
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ulong len = sizeof(fpgadata);
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ulong len = sizeof(fpgadata);
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int status;
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int status;
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@ -184,16 +184,28 @@ int misc_init_r (void)
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/*
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/*
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* Reset external DUARTs
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* Reset external DUARTs
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*/
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*/
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
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udelay(10); /* wait 10us */
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udelay(10); /* wait 10us */
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out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
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udelay(1000); /* wait 1ms */
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udelay(1000); /* wait 1ms */
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
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/*
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* Setup EEPROM write protection
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*/
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
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out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
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/*
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/*
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* Enable interrupts in exar duart mcr[3]
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* Enable interrupts in exar duart mcr[3]
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*/
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*/
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*duart0_mcr = 0x08;
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out_8(duart0_mcr, 0x08);
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*duart1_mcr = 0x08;
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out_8(duart1_mcr, 0x08);
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return (0);
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return (0);
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}
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}
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@ -259,3 +271,74 @@ void reset_phy(void)
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lxt971_no_sleep();
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lxt971_no_sleep();
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#endif
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#endif
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}
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}
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#if defined(CFG_EEPROM_WREN)
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/* Input: <dev_addr> I2C address of EEPROM device to enable.
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* <state> -1: deliver current state
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* 0: disable write
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* 1: enable write
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* Returns: -1: wrong device address
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* 0: dis-/en- able done
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* 0/1: current state if <state> was -1.
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*/
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int eeprom_write_enable (unsigned dev_addr, int state)
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{
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if (CFG_I2C_EEPROM_ADDR != dev_addr) {
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return -1;
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} else {
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switch (state) {
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case 1:
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/* Enable write access, clear bit GPIO0. */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
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state = 0;
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break;
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case 0:
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/* Disable write access, set bit GPIO0. */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
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state = 0;
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break;
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default:
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/* Read current status back. */
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state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
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break;
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}
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}
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return state;
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}
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int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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int query = argc == 1;
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int state = 0;
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if (query) {
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/* Query write access state. */
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
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if (state < 0) {
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puts ("Query of write access state failed.\n");
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} else {
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printf ("Write access for device 0x%0x is %sabled.\n",
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CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
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state = 0;
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}
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} else {
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if ('0' == argv[1][0]) {
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/* Disable write access. */
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
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} else {
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/* Enable write access. */
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
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}
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if (state < 0) {
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puts ("Setup of write access state failed.\n");
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}
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}
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return state;
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}
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U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
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"eepwren - Enable / disable / query EEPROM write access\n",
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NULL);
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#endif /* #if defined(CFG_EEPROM_WREN) */
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@ -288,6 +288,7 @@
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
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#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
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#define CFG_EEPROM_WREN 1
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/* CAT24WC08/16... */
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/* CAT24WC08/16... */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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@ -379,15 +380,16 @@
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* GPIO0[28-29] - UART1 data signal input/output
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* GPIO0[28-29] - UART1 data signal input/output
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* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
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* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
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*/
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*/
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#define CFG_GPIO0_OSRH 0x40000550
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#define CFG_GPIO0_OSRH 0x00000550
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#define CFG_GPIO0_OSRL 0x00000110
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#define CFG_GPIO0_OSRL 0x00000110
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#define CFG_GPIO0_ISR1H 0x00000000
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#define CFG_GPIO0_ISR1H 0x00000000
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#define CFG_GPIO0_ISR1L 0x15555445
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#define CFG_GPIO0_ISR1L 0x15555445
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#define CFG_GPIO0_TSRH 0x00000000
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#define CFG_GPIO0_TSRH 0x00000000
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#define CFG_GPIO0_TSRL 0x00000000
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#define CFG_GPIO0_TSRL 0x00000000
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#define CFG_GPIO0_TCR 0xF7FE0014
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#define CFG_GPIO0_TCR 0x77FE0014
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#define CFG_DUART_RST (0x80000000 >> 14)
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#define CFG_DUART_RST (0x80000000 >> 14)
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#define CFG_EEPROM_WP (0x80000000 >> 0)
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/*
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/*
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* Internal Definitions
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* Internal Definitions
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