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Add support for wrPPMC7xx/74xx boards 

Patch from Richard Danter, 12 Aug 2005
This commit is contained in:
Heiko Schocher 2006-06-19 11:02:41 +02:00
parent 8d352247ec
commit f5e0d03970
16 changed files with 1703 additions and 4 deletions
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3
CHANGELOG
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@ -2,6 +2,9 @@
Changes since U-Boot 1.1.4:
======================================================================
* Add support for wrPPMC7xx/74xx boards
Patch from Richard Danter, 12 Aug 2005
* Add support for gth2 board
Patch by Thomas Lange, Aug 11 2005

4
CREDITS
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@ -105,6 +105,10 @@ N: Magnus Damm
E: damm@opensource.se
D: 8xxrom
N: Richard Danter
E: richard.danter@windriver.com
D: Support for Wind River PPMC 7xx/74xx boards
N: George G. Davis
E: gdavis@mvista.com
D: Board ports for ADS GraphicsClient+ and Intel Assabet

2
MAKEALL
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@ -142,7 +142,7 @@ LIST_74xx=" \
"
LIST_7xx=" \
BAB7xx CPCI750 ELPPC \
BAB7xx CPCI750 ELPPC ppmc7xx \
"
LIST_ppc="${LIST_5xx} ${LIST_5xxx} \

3
Makefile
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@ -1452,6 +1452,9 @@ PCIPPC6_config: unconfig
ZUMA_config: unconfig
@./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
ppmc7xx_config: unconfig
@./mkconfig $(@:_config=) ppc 74xx_7xx ppmc7xx
#========================================================================
# ARM
#========================================================================

47
board/ppmc7xx/Makefile Normal file
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@ -0,0 +1,47 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := ppmc7xx.o pci.o flash.o
SOBJS := init.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

33
board/ppmc7xx/config.mk Normal file
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@ -0,0 +1,33 @@
#
# (C) Copyright 2005
# Richard Danter, Wind River Systems
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
#
#
TEXT_BASE = 0xFFF00000
TEXT_END = 0xFFF40000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

494
board/ppmc7xx/flash.c Normal file
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@ -0,0 +1,494 @@
/*
* flash.c
* -------
*
* Flash programming routines for the Wind River PPMC 74xx/7xx
* based on flash.c from the TQM8260 board.
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
#include <common.h>
#include <asm/processor.h>
#include <74xx_7xx.h>
#define DWORD unsigned long long
/* Local function prototypes */
static int write_dword (flash_info_t* info, ulong dest, unsigned char *pdata);
static void write_via_fpu (volatile DWORD* addr, DWORD* data);
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
/*-----------------------------------------------------------------------
*/
void flash_reset (void)
{
unsigned long msr;
DWORD cmd_reset = 0x00F000F000F000F0LL;
if (flash_info[0].flash_id != FLASH_UNKNOWN) {
msr = get_msr ();
set_msr (msr | MSR_FP);
write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
set_msr (msr);
}
}
/*-----------------------------------------------------------------------
*/
ulong flash_get_size (ulong baseaddr, flash_info_t * info)
{
int i;
unsigned long msr;
DWORD flashtest;
DWORD cmd_select[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
0x0090009000900090LL };
/* Enable FPU */
msr = get_msr ();
set_msr (msr | MSR_FP);
/* Write auto-select command sequence */
write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
/* Restore FPU */
set_msr (msr);
/* Read manufacturer ID */
flashtest = *(volatile DWORD*)baseaddr;
switch ((int)flashtest) {
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
default:
/* No, faulty or unknown flash */
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0);
}
/* Read device ID */
flashtest = *(volatile DWORD*)(baseaddr + 8);
switch ((long)flashtest) {
case AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00400000;
break;
case AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00400000;
break;
case AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00800000;
break;
case AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00800000;
break;
case AMD_ID_DL322T:
info->flash_id += FLASH_AMDL322T;
info->sector_count = 71;
info->size = 0x01000000;
break;
case AMD_ID_DL322B:
info->flash_id += FLASH_AMDL322B;
info->sector_count = 71;
info->size = 0x01000000;
break;
case AMD_ID_DL323T:
info->flash_id += FLASH_AMDL323T;
info->sector_count = 71;
info->size = 0x01000000;
break;
case AMD_ID_DL323B:
info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x01000000;
break;
case AMD_ID_LV640U:
info->flash_id += FLASH_AM640U;
info->sector_count = 128;
info->size = 0x02000000;
break;
default:
/* Unknown flash type */
info->flash_id = FLASH_UNKNOWN;
return (0);
}
if ((long)flashtest == AMD_ID_LV640U) {
/* set up sector start adress table (uniform sector type) */
for (i = 0; i < info->sector_count; i++)
info->start[i] = baseaddr + (i * 0x00040000);
} else if (info->flash_id & FLASH_BTYPE) {
/* set up sector start adress table (bottom sector type) */
info->start[0] = baseaddr + 0x00000000;
info->start[1] = baseaddr + 0x00010000;
info->start[2] = baseaddr + 0x00018000;
info->start[3] = baseaddr + 0x00020000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
}
} else {
/* set up sector start adress table (top sector type) */
i = info->sector_count - 1;
info->start[i--] = baseaddr + info->size - 0x00010000;
info->start[i--] = baseaddr + info->size - 0x00018000;
info->start[i--] = baseaddr + info->size - 0x00020000;
for (; i >= 0; i--) {
info->start[i] = baseaddr + i * 0x00040000;
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
if (*(volatile DWORD*)(info->start[i] + 16) & 0x0001000100010001LL) {
info->protect[i] = 1; /* D0 = 1 if protected */
} else {
info->protect[i] = 0;
}
}
flash_reset ();
return (info->size);
}
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0 = 0;
int i;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here (only one bank) */
size_b0 = flash_get_size (CFG_FLASH_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 >> 20);
}
/*
* protect monitor and environment sectors
*/
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
#endif
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
#endif
return (size_b0);
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf ("AMD ");
break;
case FLASH_MAN_FUJ:
printf ("FUJITSU ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM800T:
printf ("29LV800T (8 M, top sector)\n");
break;
case FLASH_AM800B:
printf ("29LV800T (8 M, bottom sector)\n");
break;
case FLASH_AM160T:
printf ("29LV160T (16 M, top sector)\n");
break;
case FLASH_AM160B:
printf ("29LV160B (16 M, bottom sector)\n");
break;
case FLASH_AMDL322T:
printf ("29DL322T (32 M, top sector)\n");
break;
case FLASH_AMDL322B:
printf ("29DL322B (32 M, bottom sector)\n");
break;
case FLASH_AMDL323T:
printf ("29DL323T (32 M, top sector)\n");
break;
case FLASH_AMDL323B:
printf ("29DL323B (32 M, bottom sector)\n");
break;
case FLASH_AM640U:
printf ("29LV640D (64 M, uniform sector)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect, l_sect;
ulong start, now, last;
unsigned long msr;
DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
0x0080008000800080LL, 0x00AA00AA00AA00AALL,
0x0055005500550055LL, 0x0030003000300030LL };
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect])
prot++;
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Enable FPU */
msr = get_msr();
set_msr ( msr | MSR_FP );
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[0] );
write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[1] );
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[2] );
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[3] );
write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[4] );
udelay (1000);
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
write_via_fpu ((DWORD*)info->start[sect], &cmd_erase[5] );
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* Restore FPU */
set_msr (msr);
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL )
!= 0x0080008000800080LL )
{
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
serial_putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
flash_reset ();
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong dp;
static unsigned char bb[8];
int i, l, rc, cc = cnt;
dp = (addr & ~7); /* get lower dword aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - dp) != 0) {
for (i = 0; i < 8; i++)
bb[i] = (i < l || (i - l) >= cc) ? *(char*)(dp + i) : *src++;
if ((rc = write_dword (info, dp, bb)) != 0) {
return (rc);
}
dp += 8;
cc -= 8 - l;
}
/*
* handle word aligned part
*/
while (cc >= 8) {
if ((rc = write_dword (info, dp, src)) != 0) {
return (rc);
}
dp += 8;
src += 8;
cc -= 8;
}
if (cc <= 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
for (i = 0; i < 8; i++) {
bb[i] = (i < cc) ? *src++ : *(char*)(dp + i);
}
return (write_dword (info, dp, bb));
}
/*-----------------------------------------------------------------------
* Write a dword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
{
ulong start;
unsigned long msr;
int flag, i;
DWORD data;
DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
0x00A000A000A000A0LL };
for (data = 0, i = 0; i < 8; i++)
data = (data << 8) + *pdata++;
/* Check if Flash is (sufficiently) erased */
if ((*(DWORD*)dest & data) != data) {
return (2);
}
/* Enable FPU */
msr = get_msr();
set_msr( msr | MSR_FP );
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[0] );
write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_write[1] );
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[2] );
write_via_fpu ((DWORD*)dest, &data );
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* Restore FPU */
set_msr(msr);
/* data polling for D7 */
start = get_timer (0);
while (*(volatile DWORD*)dest != data ) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/
static void write_via_fpu (volatile DWORD* addr, DWORD* data)
{
__asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
__asm__ __volatile__ ("eieio");
}

336
board/ppmc7xx/init.S Normal file
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@ -0,0 +1,336 @@
/*
* init.S
* ------
*
* Wind River PPMC 7xx/74xx init code.
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*
* NOTE: The following code was generated automatically by Workbench
* from the ppmc7400_107.reg register file.
*/
#include <ppc_asm.tmpl>
.globl board_asm_init
board_asm_init:
lis r4,0xFEC0
ori r4,r4,0x0000
lis r5,0xFEE0
ori r5,r5,0x0000
lis r3,0x8000 # ADDR_00
ori r3,r3,0x0000
stwbrx r3,0,r4
li r3,0x1057 # VENDOR
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_02
ori r3,r3,0x0002
stwbrx r3,0,r4
li r3,0x0004 # ID
li r8, 0x2
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_04
ori r3,r3,0x0004
stwbrx r3,0,r4
li r3,0x0006 # PCICMD
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_06
ori r3,r3,0x0006
stwbrx r3,0,r4
li r3,0x00A0 # PCISTAT
li r8, 0x2
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_08
ori r3,r3,0x0008
stwbrx r3,0,r4
li r3,0x10 # REVID
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_09
ori r3,r3,0x0009
stwbrx r3,0,r4
li r3,0x00 # PROGIR
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_0A
ori r3,r3,0x000A
stwbrx r3,0,r4
li r3,0x00 # SUBCCODE
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_0B
ori r3,r3,0x000B
stwbrx r3,0,r4
li r3,0x06 # PBCCR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_0C
ori r3,r3,0x000C
stwbrx r3,0,r4
li r3,0x08 # PCLSR
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_0D
ori r3,r3,0x000D
stwbrx r3,0,r4
li r3,0x00 # PLTR
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_0E
ori r3,r3,0x000E
stwbrx r3,0,r4
li r3,0x00 # HEADTYPE
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_0F
ori r3,r3,0x000F
stwbrx r3,0,r4
li r3,0x00 # BISTCTRL
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_10
ori r3,r3,0x0010
stwbrx r3,0,r4
lis r3,0x0000 # LMBAR
ori r3,r3,0x0008
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_14
ori r3,r3,0x0014
stwbrx r3,0,r4
lis r3,0xF000 # PCSRBAR
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_3C
ori r3,r3,0x003C
stwbrx r3,0,r4
li r3,0x00 # ILR
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_3D
ori r3,r3,0x003D
stwbrx r3,0,r4
li r3,0x01 # INTPIN
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_3E
ori r3,r3,0x003E
stwbrx r3,0,r4
li r3,0x00 # MIN_GNT
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_3F
ori r3,r3,0x003F
stwbrx r3,0,r4
li r3,0x00 # MAX_LAT
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_40
ori r3,r3,0x0040
stwbrx r3,0,r4
li r3,0x00 # BUSNB
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_41
ori r3,r3,0x0041
stwbrx r3,0,r4
li r3,0x00 # SBUSNB
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_46
ori r3,r3,0x0046
stwbrx r3,0,r4
# li r3,0xE080 # PCIARB
li r3,-0x1F80 # PCIARB
li r8, 0x2
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_70
ori r3,r3,0x0070
stwbrx r3,0,r4
li r3,0x0000 # PMCR1
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_72
ori r3,r3,0x0072
stwbrx r3,0,r4
li r3,0xC0 # PMCR2
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_73
ori r3,r3,0x0073
stwbrx r3,0,r4
li r3,0xEF # ODCR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_74
ori r3,r3,0x0074
stwbrx r3,0,r4
li r3,0x7D00 # CLKDCR
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_76
ori r3,r3,0x0076
stwbrx r3,0,r4
li r3,0x00 # MDCR
stb r3,0x2(r5)
lis r6,0xFCE0
ori r6,r6,0x0000 # r6 is the EUMBAR Base Address
lis r3,0x8000 # ADDR_78
ori r3,r3,0x0078
stwbrx r3,0,r4
lis r3,0xFCE0 # EUMBBAR
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_80
ori r3,r3,0x0080
stwbrx r3,0,r4
lis r3,0xFFFF # MSADDR1
ori r3,r3,0x4000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_84
ori r3,r3,0x0084
stwbrx r3,0,r4
lis r3,0xFFFF # MSADDR2
ori r3,r3,0xFFFF
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_88
ori r3,r3,0x0088
stwbrx r3,0,r4
lis r3,0x0303 # EMSADDR1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_8C
ori r3,r3,0x008C
stwbrx r3,0,r4
lis r3,0x0303 # EMSADDR2
ori r3,r3,0x0303
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_90
ori r3,r3,0x0090
stwbrx r3,0,r4
lis r3,0xFFFF # EMEADDR1
ori r3,r3,0x7F3F
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_94
ori r3,r3,0x0094
stwbrx r3,0,r4
lis r3,0xFFFF # EMEADDR2
ori r3,r3,0xFFFF
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_98
ori r3,r3,0x0098
stwbrx r3,0,r4
lis r3,0x0303 # EXTEMEM1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_9C
ori r3,r3,0x009C
stwbrx r3,0,r4
lis r3,0x0303 # EXTEMEM2
ori r3,r3,0x0303
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_A0
ori r3,r3,0x00A0
stwbrx r3,0,r4
li r3,0x03 # MEMBNKEN
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_A3
ori r3,r3,0x00A3
stwbrx r3,0,r4
li r3,0x00 # MEMPMODE
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_B8
ori r3,r3,0x00B8
stwbrx r3,0,r4
li r3,0x00 # ECCCNT
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_B9
ori r3,r3,0x00B9
stwbrx r3,0,r4
li r3,0x00 # ECCTRG
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_C0
ori r3,r3,0x00C0
stwbrx r3,0,r4
li r3,0xFF # ERRENR1
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_C1
ori r3,r3,0x00C1
stwbrx r3,0,r4
li r3,0x00 # ERRDR1
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_C3
ori r3,r3,0x00C3
stwbrx r3,0,r4
li r3,0x50 # IPBESR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_C4
ori r3,r3,0x00C4
stwbrx r3,0,r4
li r3,0xBF # ERRENR2
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_C5
ori r3,r3,0x00C5
stwbrx r3,0,r4
li r3,0x00 # ERRDR2
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_C7
ori r3,r3,0x00C7
stwbrx r3,0,r4
li r3,0x00 # PCIBESR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_C8
ori r3,r3,0x00C8
stwbrx r3,0,r4
lis r3,0x0000 # BERRADDR
ori r3,r3,0xE0FE
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_E0
ori r3,r3,0x00E0
stwbrx r3,0,r4
li r3,0xC0 # AMBOR
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_F4
ori r3,r3,0x00F4
stwbrx r3,0,r4
lis r3,0x0000 # MCCR2
ori r3,r3,0x020C
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_F8
ori r3,r3,0x00F8
stwbrx r3,0,r4
lis r3,0x0230 # MCCR3
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_FC
ori r3,r3,0x00FC
stwbrx r3,0,r4
lis r3,0x2532 # MCCR4
ori r3,r3,0x2220
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_F0
ori r3,r3,0x00F0
stwbrx r3,0,r4
lis r3,0xFFC8 # MCCR1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_A8
ori r3,r3,0x00A8
stwbrx r3,0,r4
lis r3,0xFF14 # PICR1
ori r3,r3,0x1CC8
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_AC
ori r3,r3,0x00AC
stwbrx r3,0,r4
lis r3,0x0000 # PICR2
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
blr

97
board/ppmc7xx/pci.c Normal file
View File

@ -0,0 +1,97 @@
/*
* (C) Copyright 2002 ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* PCI initialisation for the MPC10x.
*/
#include <common.h>
#include <pci.h>
#include <mpc106.h>
#ifdef CONFIG_PCI
struct pci_controller local_hose;
void pci_init_board(void)
{
struct pci_controller* hose = (struct pci_controller *)&local_hose;
u16 reg16;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0,
CFG_PCI_MEMORY_BUS,
CFG_PCI_MEMORY_PHYS,
CFG_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
CFG_PCI_MEM_BUS,
CFG_PCI_MEM_PHYS,
CFG_PCI_MEM_SIZE,
PCI_REGION_MEM);
/* ISA/PCI memory space */
pci_set_region(hose->regions + 2,
CFG_ISA_MEM_BUS,
CFG_ISA_MEM_PHYS,
CFG_ISA_MEM_SIZE,
PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region(hose->regions + 3,
CFG_PCI_IO_BUS,
CFG_PCI_IO_PHYS,
CFG_PCI_IO_SIZE,
PCI_REGION_IO);
/* ISA/PCI I/O space */
pci_set_region(hose->regions + 4,
CFG_ISA_IO_BUS,
CFG_ISA_IO_PHYS,
CFG_ISA_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 5;
pci_setup_indirect(hose,
MPC106_REG_ADDR,
MPC106_REG_DATA);
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
/* Initialises the MPC10x PCI Configuration regs. */
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
/* Clear non-reserved bits in status register */
pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
}
#endif /* CONFIG_PCI */

104
board/ppmc7xx/ppmc7xx.c Normal file
View File

@ -0,0 +1,104 @@
/*
* ppmc7xx.c
* ---------
*
* Main board-specific routines for Wind River PPMC 7xx/74xx board.
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
#include <common.h>
#include <command.h>
/* Define some MPC107 (memory controller) registers */
#define MPC107_EUMB_GCR 0xfce41020
#define MPC107_EUMB_IACKR 0xfce600a0
/* Function prototypes */
extern void unlock_ram_in_cache( void );
extern void _start_warm(void);
/*
* initdram()
*
* This function normally initialises the (S)DRAM of the system. For this board
* the SDRAM was already initialised by board_asm_init (see init.S) so we just
* return the size of RAM.
*/
long initdram( int board_type )
{
return CFG_SDRAM_SIZE;
}
/*
* after_reloc()
*
* This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
* us an opportunity to do some additional setup before the rest of the system
* is initialised. We don't need to do anything, so we just call board_init_r()
* which should never return.
*/
void after_reloc( ulong dest_addr, gd_t* gd )
{
/* Jump to the main U-Boot board init code */
board_init_r( gd, dest_addr );
}
/*
* checkboard()
*
* We could do some board level checks here, such as working out what version
* it is, but for this board we simply display it's name (on the console).
*/
int checkboard( void )
{
puts( "Board: Wind River PPMC 7xx/74xx\n" );
return 0;
}
/*
* misc_init_r
*
* Used for other setup which needs to be done late in the bring-up phase.
*/
int misc_init_r( void )
{
/* Reset the EPIC and clear pending interrupts */
out32r(MPC107_EUMB_GCR, 0xa0000000);
while( in32r( MPC107_EUMB_GCR ) & 0x80000000 );
out32r( MPC107_EUMB_GCR, 0x20000000 );
while( in32r( MPC107_EUMB_IACKR ) != 0xff );
/* Enable the I-Cache */
icache_enable();
return 0;
}
/*
* do_reset()
*
* Shell command to reset the board.
*/
void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
{
printf( "Resetting...\n" );
/* Disabe and invalidate cache */
icache_disable();
dcache_disable();
/* Jump to warm start (in RAM) */
_start_warm();
/* Should never get here */
while(1);
}

135
board/ppmc7xx/u-boot.lds Normal file
View File

@ -0,0 +1,135 @@
/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
/* common/environment.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

3
cpu/74xx_7xx/cpu.c
View File

@ -215,7 +215,8 @@ soft_restart(unsigned long addr)
#if !defined(CONFIG_PCIPPC2) && \
!defined(CONFIG_BAB7xx) && \
!defined(CONFIG_ELPPC)
!defined(CONFIG_ELPPC) && \
!defined(CONFIG_PPMC7XX)
/* no generic way to do board reset. simply call soft_reset. */
void
do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

3
cpu/74xx_7xx/start.S
View File

@ -756,7 +756,8 @@ in_ram:
#if defined(CONFIG_AMIGAONEG3SE) || \
defined(CONFIG_DB64360) || \
defined(CONFIG_DB64460) || \
defined(CONFIG_CPCI750)
defined(CONFIG_CPCI750) || \
defined(CONFIG_PPMC7XX)
mr r4, r9 /* Use RAM copy of the global data */
#endif
bl after_reloc

2
drivers/pci.c
View File

@ -163,7 +163,7 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
#endif
for (bdf = PCI_BDF(bus,0,0);
#ifdef CONFIG_ELPPC
#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
#else
bdf < PCI_BDF(bus+1,0,0);

419
include/configs/ppmc7xx.h Normal file
View File

@ -0,0 +1,419 @@
/*
* ppmc7xx.h
* ---------
*
* Wind River PPMC 7xx/74xx board configuration file.
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_PPMC7XX
/*===================================================================
*
* User configurable settings - Modify to your preference
*
*===================================================================
*/
/*
* Debug
*
* DEBUG - Define this is you want extra debug info
* GTREGREAD - Required to build with debug
* do_bdinfo - Required to build with debug
*/
#undef DEBUG
#define GTREGREAD(x) 0xFFFFFFFF
#define do_bdinfo(a,b,c,d)
/*
* CPU type
*
* CONFIG_7xx - We have a 750 or 755 CPU
* CONFIG_74xx - We have a 7400 CPU
* CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
* CONFIG_BUS_CLK - System bus clock in Hz
*/
#define CONFIG_7xx
#undef CONFIG_74xx
#undef CONFIG_ALTIVEC
#define CONFIG_BUS_CLK 66000000
/*
* Monitor configuration
*
* CONFIG_COMMANDS - List of command sets to include in shell
*
* The following command sets have been tested and known to work:
*
* CFG_CMD_CACHE - Cache control commands
* CFG_CMD_MEMORY - Memory display, change and test commands
* CFG_CMD_FLASH - Erase and program flash
* CFG_CMD_ENV - Environment commands
* CFG_CMD_RUN - Run commands stored in env vars
* CFG_CMD_ELF - Load ELF files
* CFG_CMD_NET - Networking/file download commands
* CFG_CMD_PING - ICMP Echo Request command
* CFG_CMD_PCI - PCI Bus scanning command
*/
#define CONFIG_COMMANDS ( (CFG_CMD_DFL & ~(CFG_CMD_KGDB)) | \
CFG_CMD_FLASH | \
CFG_CMD_ENV | \
CFG_CMD_RUN | \
CFG_CMD_ELF | \
CFG_CMD_NET | \
CFG_CMD_PING | \
CFG_CMD_PCI)
/*
* Serial configuration
*
* CONFIG_CONS_INDEX - Serial console port number (COM1)
* CONFIG_BAUDRATE - Serial speed
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 9600
/*
* PCI config
*
* CONFIG_PCI - Enable PCI bus
* CONFIG_PCI_PNP - Enable Plug & Play support
* CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
*/
#define CONFIG_PCI
#define CONFIG_PCI_PNP
#undef CONFIG_PCI_SCAN_SHOW
/*
* Network config
*
* CONFIG_NET_MULTI - Support for multiple network interfaces
* CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
* CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
*/
#define CONFIG_NET_MULTI
#define CONFIG_EEPRO100
#define CONFIG_EEPRO100_SROM_WRITE
/*
* Enable extra init functions
*
* CONFIG_MISC_INIT_F - Call pre-relocation init functions
* CONFIG_MISC_INIT_R - Call post relocation init functions
*/
#undef CONFIG_MISC_INIT_F
#define CONFIG_MISC_INIT_R
/*
* Boot config
*
* CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
* CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
*/
#define CONFIG_BOOTCOMMAND \
"bootp;" \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
"bootm"
#define CONFIG_BOOTDELAY 5
/*===================================================================
*
* Board configuration settings - You should not need to modify these
*
*===================================================================
*/
#include <cmd_confdefs.h>
/*
* Memory map
*
* This board runs in a standard CHRP (Map-B) configuration.
*
* Type Start End Size Width Chip Sel
* ----------- ----------- ----------- ------- ------- --------
* SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
* User LED's 0x78000000 RCS3
* UART 0x7C000000 RCS2
* Mailbox 0xFF000000 RCS1
* Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
*
* Flash sectors are laid out as follows.
*
* Sector Start End Size Comments
* ------- ----------- ----------- ------- -----------
* 0 0xFFC00000 0xFFC3FFFF 256KB
* 1 0xFFC40000 0xFFC7FFFF 256KB
* 2 0xFFC80000 0xFFCBFFFF 256KB
* 3 0xFFCC0000 0xFFCFFFFF 256KB
* 4 0xFFD00000 0xFFD3FFFF 256KB
* 5 0xFFD40000 0xFFD7FFFF 256KB
* 6 0xFFD80000 0xFFDBFFFF 256KB
* 7 0xFFDC0000 0xFFDFFFFF 256KB
* 8 0xFFE00000 0xFFE3FFFF 256KB
* 9 0xFFE40000 0xFFE7FFFF 256KB
* 10 0xFFE80000 0xFFEBFFFF 256KB
* 11 0xFFEC0000 0xFFEFFFFF 256KB
* 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
* 13 0xFFF40000 0xFFF7FFFF 256KB
* 14 0xFFF80000 0xFFFBFFFF 256KB
* 15 0xFFFC0000 0xFFFDFFFF 128KB
* 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
* 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
* 18 0xFFFF0000 0xFFFFFFFF 64KB
*/
/*
* SDRAM config - see memory map details above.
*
* CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
* CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 0x04000000
/*
* Flash config - see memory map details above.
*
* CFG_FLASH_BASE - Start address of flash memory
* CFG_FLASH_SIZE - Total size of contiguous flash mem
* CFG_FLASH_ERASE_TOUT - Erase timeout in ms
* CFG_FLASH_WRITE_TOUT - Write timeout in ms
* CFG_MAX_FLASH_BANKS - Number of banks of flash on board
* CFG_MAX_FLASH_SECT - Number of sectors in a bank
*/
#define CFG_FLASH_BASE 0xFFC00000
#define CFG_FLASH_SIZE 0x00400000
#define CFG_FLASH_ERASE_TOUT 250000
#define CFG_FLASH_WRITE_TOUT 5000
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MAX_FLASH_SECT 19
/*
* Monitor config - see memory map details above
*
* CFG_MONITOR_BASE - Base address of monitor code
* CFG_MALLOC_LEN - Size of malloc pool (128KB)
*/
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MALLOC_LEN 0x20000
/*
* Command shell settings
*
* CFG_BARGSIZE - Boot Argument buffer size
* CFG_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
* CFG_CBSIZE - Console Buffer (input) size
* CFG_LOAD_ADDR - Default load address
* CFG_LONGHELP - Provide more detailed help
* CFG_MAXARGS - Number of args accepted by monitor commands
* CFG_MEMTEST_START - Start address of test to run on RAM
* CFG_MEMTEST_END - End address of RAM test
* CFG_PBSIZE - Print Buffer (output) size
* CFG_PROMPT - Prompt string
*/
#define CFG_BARGSIZE 1024
#define CFG_BOOTMAPSZ 0x800000
#define CFG_CBSIZE 1024
#define CFG_LOAD_ADDR 0x100000
#define CFG_LONGHELP
#define CFG_MAXARGS 16
#define CFG_MEMTEST_START 0x00040000
#define CFG_MEMTEST_END 0x00040100
#define CFG_PBSIZE 1024
#define CFG_PROMPT "=> "
/*
* Environment config - see memory map details above
*
* CFG_ENV_IS_IN_FLASH - The env variables are stored in flash
* CFG_ENV_ADDR - Address of the sector containing env vars
* CFG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
* CFG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR 0xFFFE0000
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_ADDR_REDUND 0xFFFE8000
#define CFG_ENV_SIZE_REDUND 0x1000
#define CFG_ENV_SECT_SIZE 0x8000
/*
* Initial RAM config
*
* Since the main system RAM is initialised very early, we place the INIT_RAM
* in the main system RAM just above the exception vectors. The contents are
* copied to top of RAM by the init code.
*
* CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect
* CFG_INIT_RAM_END - Size of Init RAM
* CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
* CFG_GBL_DATA_OFFSET - Start of global data, top of stack
*/
#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000)
#define CFG_INIT_RAM_END 0x4000
#define CFG_GBL_DATA_SIZE 128
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/*
* Initial BAT config
*
* BAT0 - System SDRAM
* BAT1 - LED's and Serial Port
* BAT2 - PCI Memory
* BAT3 - PCI I/O including Flash Memory
*/
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
#define CFG_DBAT0L CFG_IBAT0L
#define CFG_DBAT0U CFG_IBAT0U
#define CFG_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
/*
* Cache config
*
* CFG_CACHELINE_SIZE - Size of a cache line (CPU specific)
* CFG_L2 - L2 cache enabled if defined
* L2_INIT - L2 cache init flags
* L2_ENABLE - L2 cache enable flags
*/
#define CFG_CACHELINE_SIZE 32
#undef CFG_L2
#define L2_INIT 0
#define L2_ENABLE 0
/*
* Clocks config
*
* CFG_BUS_HZ - Bus clock frequency in Hz
* CFG_BUS_CLK - As above (?)
* CFG_HZ - Decrementer freq in Hz
*/
#define CFG_BUS_HZ CONFIG_BUS_CLK
#define CFG_BUS_CLK CONFIG_BUS_CLK
#define CFG_HZ 1000
/*
* Serial port config
*
* CFG_BAUDRATE_TABLE - List of valid baud rates
* CFG_NS16550 - Include the NS16550 driver
* CFG_NS16550_SERIAL - Include the serial (wrapper) driver
* CFG_NS16550_CLK - Frequency of reference clock
* CFG_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
* CFG_NS16550_COM1 - Base address of 1st serial port
*/
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_CLK 3686400
#define CFG_NS16550_REG_SIZE -8
#define CFG_NS16550_COM1 0x7C000000
/*
* PCI Config - Address Map B (CHRP)
*/
#define CFG_PCI_MEMORY_BUS 0x00000000
#define CFG_PCI_MEMORY_PHYS 0x00000000
#define CFG_PCI_MEMORY_SIZE 0x40000000
#define CFG_PCI_MEM_BUS 0x80000000
#define CFG_PCI_MEM_PHYS 0x80000000
#define CFG_PCI_MEM_SIZE 0x7D000000
#define CFG_ISA_MEM_BUS 0x00000000
#define CFG_ISA_MEM_PHYS 0xFD000000
#define CFG_ISA_MEM_SIZE 0x01000000
#define CFG_PCI_IO_BUS 0x00800000
#define CFG_PCI_IO_PHYS 0xFE800000
#define CFG_PCI_IO_SIZE 0x00400000
#define CFG_ISA_IO_BUS 0x00000000
#define CFG_ISA_IO_PHYS 0xFE000000
#define CFG_ISA_IO_SIZE 0x00800000
#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
#define CFG_ISA_IO CFG_ISA_IO_PHYS
#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
/*
* Extra init functions
*
* CFG_BOARD_ASM_INIT - Call assembly init code
*/
#define CFG_BOARD_ASM_INIT
/*
* Boot flags
*
* BOOTFLAG_COLD - Indicates a power-on boot
* BOOTFLAG_WARM - Indicates a software reset
*/
#define BOOTFLAG_COLD 0x01
#define BOOTFLAG_WARM 0x02
#endif /* __CONFIG_H */

22
include/ns16550.h
View File

@ -7,6 +7,9 @@
* added prototypes for ns16550.c
* reduced no of com ports to 2
* modifications (c) Rob Taylor, Flying Pig Systems. 2000.
*
* added support for port on 64-bit bus
* by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
*/
#if (CFG_NS16550_REG_SIZE == 1)
@ -82,6 +85,25 @@ struct NS16550 {
int pad10:24;
#endif
} __attribute__ ((packed));
#elif (CFG_NS16550_REG_SIZE == -8)
struct NS16550 {
unsigned char rbr; /* 0 */
unsigned char pad0[7];
unsigned char ier; /* 1 */
unsigned char pad1[7];
unsigned char fcr; /* 2 */
unsigned char pad2[7];
unsigned char lcr; /* 3 */
unsigned char pad3[7];
unsigned char mcr; /* 4 */
unsigned char pad4[7];
unsigned char lsr; /* 5 */
unsigned char pad5[7];
unsigned char msr; /* 6 */
unsigned char pad6[7];
unsigned char scr; /* 7 */
unsigned char pad7[7];
} __attribute__ ((packed));
#else
#error "Please define NS16550 registers size."
#endif