* Patch by liang a lei, 9 Jan 2004:
Fix Intel 28F128J3 ID in include/flash.h * Patch by Masami Komiya, 09 Jan 2004: add support for TB0229 board (NEC VR4131 MIPS processor) * Patch by Leon Kukovec, 12 Dec 2003: changed extern __inline__ into static __inline__ in include/linux/byteorder/swab.h
This commit is contained in:
wdenk
parent
ba56f62576
commit
f4863a7aec
10
CHANGELOG
10
CHANGELOG
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@ -2,6 +2,16 @@
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Changes since U-Boot 1.0.1:
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======================================================================
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* Patch by liang a lei, 9 Jan 2004:
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Fix Intel 28F128J3 ID in include/flash.h
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* Patch by Masami Komiya, 09 Jan 2004:
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add support for TB0229 board (NEC VR4131 MIPS processor)
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* Patch by Leon Kukovec, 12 Dec 2003:
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changed extern __inline__ into static __inline__ in
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include/linux/byteorder/swab.h
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* Patch by Travis Sawyer, 30 Dec 2003:
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Add support for IBM PPC440GX. Multiple EMAC Ethernet devices,
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select MDI port based on enabled EMAC device.
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3
Makefile
3
Makefile
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@ -1027,6 +1027,9 @@ incaip_config: unconfig
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}
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@./mkconfig -a $(call xtract_incaip,$@) mips mips incaip
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tb0229_config: unconfig
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@./mkconfig $(@:_config=) mips mips tb0229
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#########################################################################
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## MIPS64 5Kc
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#########################################################################
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@ -0,0 +1,43 @@
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#
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# (C) Masami Komiya <mkomiya@sonare.it> 2004
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#
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# (C) Copyright 2003-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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||||
# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o vr4131-pci.o
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SOBJS = memsetup.o
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$(LIB): .depend $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS) $(SOBJS)
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend
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#########################################################################
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@ -0,0 +1,30 @@
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#
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# (C) Masami Komiya <mkomiya@sonare.it> 2004
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#
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# (C) Copyright 2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# ROM version
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TEXT_BASE = 0xBFC00000
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# RAM version
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#TEXT_BASE = 0x80400000
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,71 @@
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/*
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* Memory sub-system initialization code for TANBAC Evaluation board TB0229.
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*
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* Copyright (c) 2003 Masami Komiya <mkomiya@sonare.it>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2, or (at
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* your option) any later version.
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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.globl memsetup
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memsetup:
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/* BCUCNTREG1 = 0x0040 */
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la t0, 0xaf000000
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li t1, 0x0040
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sh t1, 0(t0)
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/* ROMSIZEREG = 0x3333 */
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la t0, 0xaf000004
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li t1, 0x3333
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sh t1, 0(t0)
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/* ROMSPEEDREG = 0x3003 */
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la t0, 0xaf000006
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li t1, 0x3003
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sh t1, 0(t0)
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/* BCUCNTREG3 = 0 */
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la t0, 0xaf000016
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li t1, 0x0000
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sh t1, 0(t0)
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/* CMUCLKMSK */
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la t0, 0xaf000060
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li t1, 0x39a2
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sh t1, 0(t0)
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/* PMUCNTREG */
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la t0, 0xaf0000c2
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li t1, 0x0006
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sh t1, 0(t0)
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/* SDRAMMODEREG = 0x8029 */
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la t0, 0xaf000400
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li t1, 0x8029
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sh t1, 0(t0)
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/* SDRAMCNTREG = 0x2322 */
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la t0, 0xaf000402
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li t1, 0x2322
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sh t1, 0(t0)
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/* BCURFCNTREG = 0x0106 */
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la t0, 0xaf000404
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li t1, 0x0106
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sh t1, 0(t0)
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/* RAMSZEREG = 0x5555 (64MB Bank) */
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la t0, 0xaf000408
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li t1, 0x5555
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sh t1, 0(t0)
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j ra
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nop
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@ -0,0 +1,42 @@
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/*
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* Board initialize code for TANBAC Evaluation board TB0229.
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*
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* (C) Masami Komiya <mkomiya@sonare.it> 2004
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2, or (at
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* your option) any later version.
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/addrspace.h>
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#include <asm/inca-ip.h>
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#include <pci.h>
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unsigned long mips_io_port_base = 0;
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#if defined(CONFIG_PCI)
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static struct pci_controller hose;
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void pci_init_board (void)
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{
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init_vr4131_pci(&hose);
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}
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#endif
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long int initdram(int board_type)
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{
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return get_ram_size (CFG_SDRAM_BASE, 0x8000000);
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}
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int checkboard (void)
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{
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printf("Board: TANBAC TB0229 ");
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printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
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return 0;
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}
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@ -0,0 +1,68 @@
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/*
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* (C) Masami Komiya <mkomiya@sonare.it> 2004
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*
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* (C) Copyright 2003
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* Wolfgang Denk Engineering, <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
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OUTPUT_ARCH(mips)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x00000000;
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. = ALIGN(4);
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.text :
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{
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*(.text)
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}
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. = ALIGN(4);
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.rodata : { *(.rodata) }
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. = ALIGN(4);
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.data : { *(.data) }
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. = ALIGN(4);
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.sdata : { *(.sdata) }
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_gp = ALIGN(16);
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__got_start = .;
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.got : { *(.got) }
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__got_end = .;
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.sdata : { *(.sdata) }
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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uboot_end_data = .;
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num_got_entries = (__got_end - __got_start) >> 2;
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. = ALIGN(4);
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.sbss : { *(.sbss) }
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.bss : { *(.bss) }
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uboot_end = .;
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}
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@ -0,0 +1,254 @@
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/*
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* VR4131 PCIU support code for TANBAC Evaluation board TB0229.
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*
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* (C) Masami Komiya <mkomiya@sonare.it> 2004
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2, or (at
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* your option) any later version.
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/addrspace.h>
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#define VR4131_PCIMMAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c00)
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#define VR4131_PCIMMAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c04)
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#define VR4131_PCITAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c08)
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#define VR4131_PCITAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c0c)
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#define VR4131_PCIMIOAWREG (volatile unsigned int*)(KSEG1 + 0x0f000c10)
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#define VR4131_PCICONFDREG (volatile unsigned int*)(KSEG1 + 0x0f000c14)
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#define VR4131_PCICONFAREG (volatile unsigned int*)(KSEG1 + 0x0f000c18)
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#define VR4131_PCIMAILREG (volatile unsigned int*)(KSEG1 + 0x0f000c1c)
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#define VR4131_BUSERRADREG (volatile unsigned int*)(KSEG1 + 0x0f000c24)
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#define VR4131_INTCNTSTAREG (volatile unsigned int*)(KSEG1 + 0x0f000c28)
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#define VR4131_PCIEXACCREG (volatile unsigned int*)(KSEG1 + 0x0f000c2c)
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#define VR4131_PCIRECONTREG (volatile unsigned int*)(KSEG1 + 0x0f000c30)
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#define VR4131_PCIENREG (volatile unsigned int*)(KSEG1 + 0x0f000c34)
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#define VR4131_PCICLKSELREG (volatile unsigned int*)(KSEG1 + 0x0f000c38)
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#define VR4131_PCITRDYREG (volatile unsigned int*)(KSEG1 + 0x0f000c3c)
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#define VR4131_PCICLKRUNREG (volatile unsigned int*)(KSEG1 + 0x0f000c60)
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#define VR4131_PCIHOSTCONFIG (volatile unsigned int*)(KSEG1 + 0x0f000d00)
|
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#define VR4131_VENDORIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00)
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#define VR4131_DEVICEIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00)
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#define VR4131_COMMANDREG (volatile unsigned int*)(KSEG1 + 0x0f000d04)
|
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#define VR4131_STATUSREG (volatile unsigned int*)(KSEG1 + 0x0f000d04)
|
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#define VR4131_REVREG (volatile unsigned int*)(KSEG1 + 0x0f000d08)
|
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#define VR4131_CLASSREG (volatile unsigned int*)(KSEG1 + 0x0f000d08)
|
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#define VR4131_CACHELSREG (volatile unsigned int*)(KSEG1 + 0x0f000d0c)
|
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#define VR4131_LATTIMERRG (volatile unsigned int*)(KSEG1 + 0x0f000d0c)
|
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#define VR4131_MAILBAREG (volatile unsigned int*)(KSEG1 + 0x0f000d10)
|
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#define VR4131_PCIMBA1REG (volatile unsigned int*)(KSEG1 + 0x0f000d14)
|
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#define VR4131_PCIMBA2REG (volatile unsigned int*)(KSEG1 + 0x0f000d18)
|
||||
|
||||
/*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */
|
||||
/*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */
|
||||
/*#define VR4122_PCI_HOST_BASE 0xa0000000 */
|
||||
|
||||
volatile unsigned int *pciconfigaddr;
|
||||
volatile unsigned int *pciconfigdata;
|
||||
|
||||
#define PCI_ACCESS_READ 0
|
||||
#define PCI_ACCESS_WRITE 1
|
||||
|
||||
/*
|
||||
* Access PCI Configuration Register for VR4131
|
||||
*/
|
||||
|
||||
static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg,
|
||||
u32 * data)
|
||||
{
|
||||
u32 bus;
|
||||
u32 device;
|
||||
|
||||
bus = ((dev & 0xff0000) >> 16);
|
||||
device = ((dev & 0xf800) >> 11);
|
||||
|
||||
if (bus == 0) {
|
||||
/* Type 0 Configuration */
|
||||
*VR4131_PCICONFAREG = (u32) (1UL << device | (reg & 0xfc));
|
||||
} else {
|
||||
/* Type 1 Configuration */
|
||||
*VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1);
|
||||
}
|
||||
|
||||
if (access_type == PCI_ACCESS_WRITE) {
|
||||
*VR4131_PCICONFDREG = *data;
|
||||
} else {
|
||||
*data = *VR4131_PCICONFDREG;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val)
|
||||
{
|
||||
u32 data;
|
||||
|
||||
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
|
||||
return -1;
|
||||
|
||||
*val = (data >> ((reg & 3) << 3)) & 0xff;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val)
|
||||
{
|
||||
u32 data;
|
||||
|
||||
if (reg & 1)
|
||||
return -1;
|
||||
|
||||
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
|
||||
return -1;
|
||||
|
||||
*val = (data >> ((reg & 3) << 3)) & 0xffff;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg,
|
||||
u32 * val)
|
||||
{
|
||||
u32 data = 0;
|
||||
|
||||
if (reg & 3)
|
||||
return -1;
|
||||
|
||||
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
|
||||
return -1;
|
||||
|
||||
*val = data;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val)
|
||||
{
|
||||
u32 data = 0;
|
||||
|
||||
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
|
||||
return -1;
|
||||
|
||||
data = (data & ~(0xff << ((reg & 3) << 3))) | (val <<
|
||||
((reg & 3) << 3));
|
||||
|
||||
if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val)
|
||||
{
|
||||
u32 data = 0;
|
||||
|
||||
if (reg & 1)
|
||||
return -1;
|
||||
|
||||
if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
|
||||
return -1;
|
||||
|
||||
data = (data & ~(0xffff << ((reg & 3) << 3))) | (val <<
|
||||
((reg & 3) << 3));
|
||||
|
||||
if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val)
|
||||
{
|
||||
u32 data;
|
||||
|
||||
if (reg & 3) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
data = val;
|
||||
|
||||
if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
|
||||
return -1;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Initialize VR4131 PCIU
|
||||
*/
|
||||
|
||||
vr4131_pciu_init ()
|
||||
{
|
||||
/* PCI clock */
|
||||
*VR4131_PCICLKSELREG = 0x00000002;
|
||||
|
||||
/* PCI memory and I/O space */
|
||||
*VR4131_PCIMMAW1REG = 0x100F9010;
|
||||
*VR4131_PCIMMAW2REG = 0x140FD014;
|
||||
*VR4131_PCIMIOAWREG = 0x160FD000;
|
||||
|
||||
/* Target memory window */
|
||||
*VR4131_PCITAW1REG = 0x00081000; /* 64MB */
|
||||
*VR4131_PCITAW2REG = 0x00000000;
|
||||
|
||||
*VR4131_MAILBAREG = 0UL;
|
||||
*VR4131_PCIMBA1REG = 0UL;
|
||||
|
||||
*VR4131_PCITRDYREG = 0x00008004;
|
||||
|
||||
*VR4131_PCIENREG = 0x00000004; /* PCI enable */
|
||||
*VR4131_COMMANDREG = 0x02000007;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize Module
|
||||
*/
|
||||
|
||||
void init_vr4131_pci (struct pci_controller *hose)
|
||||
{
|
||||
hose->first_busno = 0;
|
||||
hose->last_busno = 0xff;
|
||||
|
||||
vr4131_pciu_init (); /* Initialize VR4131 PCIU */
|
||||
|
||||
/* PCI memory space #1 */
|
||||
pci_set_region (hose->regions + 0,
|
||||
0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM);
|
||||
|
||||
/* PCI memory space #2 */
|
||||
pci_set_region (hose->regions + 1,
|
||||
0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM);
|
||||
|
||||
|
||||
/* PCI I/O space */
|
||||
pci_set_region (hose->regions + 2,
|
||||
0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO);
|
||||
|
||||
/* System memory space */
|
||||
pci_set_region (hose->regions + 3,
|
||||
0x00000000,
|
||||
0x80000000,
|
||||
0x04000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
hose->region_count = 4;
|
||||
|
||||
hose->read_byte = vr4131_pci_read_config_byte;
|
||||
hose->read_word = vr4131_pci_read_config_word;
|
||||
hose->read_dword = vr4131_pci_read_config_dword;
|
||||
hose->write_byte = vr4131_pci_write_config_byte;
|
||||
hose->write_word = vr4131_pci_write_config_word;
|
||||
hose->write_dword = vr4131_pci_write_config_dword;
|
||||
|
||||
pci_register_hose (hose);
|
||||
|
||||
hose->last_busno = pci_hose_scan (hose);
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -30,7 +30,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
{
|
||||
#if defined(CONFIG_INCA_IP)
|
||||
*INCA_IP_WDT_RST_REQ = 0x3f;
|
||||
#elif defined(CONFIG_PURPLE)
|
||||
#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229)
|
||||
void (*f)(void) = (void *) 0xbfc00000;
|
||||
|
||||
f();
|
||||
|
|
|
|||
|
|
@ -214,7 +214,11 @@ reset:
|
|||
mtc0 zero, CP0_WATCHHI
|
||||
|
||||
/* STATUS register */
|
||||
#ifdef CONFIG_TB0229
|
||||
li k0, ST0_CU0
|
||||
#else
|
||||
mfc0 k0, CP0_STATUS
|
||||
#endif
|
||||
li k1, ~ST0_IE
|
||||
and k0, k1
|
||||
mtc0 k0, CP0_STATUS
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@
|
|||
* Returns the uncached address of a sdram address
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef CONFIG_AU1X00
|
||||
#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
|
||||
/* We use a 36 bit physical address map here and
|
||||
cannot access physical memory directly from core */
|
||||
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,177 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Masami Komiya <mkomiya@sonare.it>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Config header file for TANBAC TB0229 board using an VR4131 CPU module
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
|
||||
#define CONFIG_TB0229 1 /* on a TB0229 Board */
|
||||
|
||||
#ifndef CPU_CLOCK_RATE
|
||||
#define CPU_CLOCK_RATE 200000000 /* 200 MHz clock for the MIPS core */
|
||||
#endif
|
||||
#define CPU_TCLOCK_RATE 16588800 /* 16.5888 MHz for TClock */
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"boot\" for the network boot using DHCP, TFTP and NFS;" \
|
||||
"echo Type \"run netboot_initrd\" for the network boot with initrd;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo Type \"run flash_local\" to mount local root filesystem;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netboot=dhcp;tftp;run netargs; bootm\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0" \
|
||||
"localargs=setenv bootargs root=1F02 ip=dhcp\0" \
|
||||
"addmisc=setenv bootargs $(bootargs) " \
|
||||
"console=ttyS0,$(baudrate) " \
|
||||
"read-only=readonly\0" \
|
||||
"netargs=run nfsargs addmisc\0" \
|
||||
"flash_nfs=run nfsargs addmisc;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"flash_local=run localargs addmisc;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"netboot_initrd=dhcp;tftp;tftp 80600000 initrd;" \
|
||||
"setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\
|
||||
"run addmisc;" \
|
||||
"bootm 80400000 80600000\0" \
|
||||
"rootpath=/export/miniroot-mipsel\0" \
|
||||
"autoload=no\0" \
|
||||
"kernel_addr=BFC60000\0" \
|
||||
"ramdisk_addr=B0100000\0" \
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"bootfile=uImage\0" \
|
||||
"load=dhcp;tftp 80400000 $(u-boot)\0" \
|
||||
"load_kernel=dhcp;tftp 80400000 $(bootfile)\0" \
|
||||
"update_uboot=run load;" \
|
||||
"protect off BFC00000 BFC3FFFF;" \
|
||||
"erase BFC00000 BFC3FFFF;" \
|
||||
"cp.b 80400000 BFC00000 $(filesize)\0" \
|
||||
"update_kernel=run load_kernel;" \
|
||||
"erase BFC60000 BFD5FFFF;" \
|
||||
"cp.b 80400000 BFC60000 $(filesize)\0" \
|
||||
"initenv=erase bfc40000 bfc5ffff\0" \
|
||||
""
|
||||
//#define CONFIG_BOOTCOMMAND "run flash_local"
|
||||
#define CONFIG_BOOTCOMMAND "run netboot"
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_ELF )
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "# " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args*/
|
||||
|
||||
#define CFG_MALLOC_LEN 128*1024
|
||||
|
||||
#define CFG_BOOTPARAMS_LEN 128*1024
|
||||
|
||||
#define CFG_HZ (CPU_TCLOCK_RATE/4)
|
||||
|
||||
#define CFG_SDRAM_BASE 0x80000000
|
||||
|
||||
#define CFG_LOAD_ADDR 0x80400000 /* default load address */
|
||||
|
||||
#define CFG_MEMTEST_START 0x80000000
|
||||
#define CFG_MEMTEST_END 0x80800000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
|
||||
|
||||
#define PHYS_FLASH_1 0xbfc00000 /* Flash Bank #1 */
|
||||
|
||||
/* The following #defines are needed to get flash environment right */
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#define CFG_MONITOR_LEN (192 << 10)
|
||||
|
||||
#define CFG_INIT_SP_OFFSET 0x400000
|
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CFG_FLASH_ERASE_TOUT (20 * CFG_HZ) /* Timeout for Flash Erase */
|
||||
#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
|
||||
/* Address and size of Primary Environment Sector */
|
||||
#define CFG_ENV_ADDR 0xBFC40000
|
||||
#define CFG_ENV_SIZE 0x20000
|
||||
|
||||
#define CFG_DIRECT_FLASH_TFTP
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_DCACHE_SIZE 16384
|
||||
#define CFG_ICACHE_SIZE 16384
|
||||
#define CFG_CACHELINE_SIZE 16
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Configuration
|
||||
*/
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
#define CFG_NS16550_REG_SIZE 1
|
||||
#define CFG_NS16550_CLK 18432000
|
||||
#define CFG_NS16550_COM1 0xaf000800
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*/
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_EEPRO100
|
||||
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
|
||||
|
||||
#define CONFIG_RTL8139
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -96,34 +96,34 @@
|
|||
#endif /* OPTIMIZE */
|
||||
|
||||
|
||||
extern __inline__ __const__ __u16 __fswab16(__u16 x)
|
||||
static __inline__ __const__ __u16 __fswab16(__u16 x)
|
||||
{
|
||||
return __arch__swab16(x);
|
||||
}
|
||||
extern __inline__ __u16 __swab16p(__u16 *x)
|
||||
static __inline__ __u16 __swab16p(__u16 *x)
|
||||
{
|
||||
return __arch__swab16p(x);
|
||||
}
|
||||
extern __inline__ void __swab16s(__u16 *addr)
|
||||
static __inline__ void __swab16s(__u16 *addr)
|
||||
{
|
||||
__arch__swab16s(addr);
|
||||
}
|
||||
|
||||
extern __inline__ __const__ __u32 __fswab32(__u32 x)
|
||||
static __inline__ __const__ __u32 __fswab32(__u32 x)
|
||||
{
|
||||
return __arch__swab32(x);
|
||||
}
|
||||
extern __inline__ __u32 __swab32p(__u32 *x)
|
||||
static __inline__ __u32 __swab32p(__u32 *x)
|
||||
{
|
||||
return __arch__swab32p(x);
|
||||
}
|
||||
extern __inline__ void __swab32s(__u32 *addr)
|
||||
static __inline__ void __swab32s(__u32 *addr)
|
||||
{
|
||||
__arch__swab32s(addr);
|
||||
}
|
||||
|
||||
#ifdef __BYTEORDER_HAS_U64__
|
||||
extern __inline__ __const__ __u64 __fswab64(__u64 x)
|
||||
static __inline__ __const__ __u64 __fswab64(__u64 x)
|
||||
{
|
||||
# ifdef __SWAB_64_THRU_32__
|
||||
__u32 h = x >> 32;
|
||||
|
|
@ -133,11 +133,11 @@ extern __inline__ __const__ __u64 __fswab64(__u64 x)
|
|||
return __arch__swab64(x);
|
||||
# endif
|
||||
}
|
||||
extern __inline__ __u64 __swab64p(__u64 *x)
|
||||
static __inline__ __u64 __swab64p(__u64 *x)
|
||||
{
|
||||
return __arch__swab64p(x);
|
||||
}
|
||||
extern __inline__ void __swab64s(__u64 *addr)
|
||||
static __inline__ void __swab64s(__u64 *addr)
|
||||
{
|
||||
__arch__swab64s(addr);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -393,6 +393,13 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
/* IP Address */
|
||||
bd->bi_ip_addr = getenv_IPaddr("ipaddr");
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/*
|
||||
* Do pci configuration
|
||||
*/
|
||||
pci_init();
|
||||
#endif
|
||||
|
||||
/** leave this here (after malloc(), environment and PCI are working) **/
|
||||
/* Initialize devices */
|
||||
devices_init ();
|
||||
|
|
|
|||
Loading…
Reference in New Issue