phone-side
/
uboot-mt623x
9
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

mpc8308: add SICR{L,H} fields definitions 

This patch adds defines to set supported fields in System I/O
Configuration Registers High and Low on Freescale MPC8308 CPU.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Ilya Yanok 2010-09-17 23:41:48 +02:00 committed by Wolfgang Denk
parent f1371048ab
commit f3ce250d96
1 changed files with 48 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
include/mpc83xx.h
View File

@ -319,6 +319,54 @@
#define SICRH_GPIO2_H 0x00000030
#define SICRH_SPI 0x00000003
#define SICRH_SPI_SD 0x00000001
#elif defined(CONFIG_MPC8308)
/* SICRL bits - MPC8308 specific */
#define SICRL_SPI_PF0 (0 << 28)
#define SICRL_SPI_PF1 (1 << 28)
#define SICRL_SPI_PF3 (3 << 28)
#define SICRL_UART_PF0 (0 << 26)
#define SICRL_UART_PF1 (1 << 26)
#define SICRL_UART_PF3 (3 << 26)
#define SICRL_IRQ_PF0 (0 << 24)
#define SICRL_IRQ_PF1 (1 << 24)
#define SICRL_I2C2_PF0 (0 << 20)
#define SICRL_I2C2_PF1 (1 << 20)
#define SICRL_ETSEC1_TX_CLK (0 << 6)
#define SICRL_ETSEC1_GTX_CLK125 (1 << 6)
/* SICRH bits - MPC8308 specific */
#define SICRH_ESDHC_A_SD (0 << 30)
#define SICRH_ESDHC_A_GTM (1 << 30)
#define SICRH_ESDHC_A_GPIO (3 << 30)
#define SICRH_ESDHC_B_SD (0 << 28)
#define SICRH_ESDHC_B_GTM (1 << 28)
#define SICRH_ESDHC_B_GPIO (3 << 28)
#define SICRH_ESDHC_C_SD (0 << 26)
#define SICRH_ESDHC_C_GTM (1 << 26)
#define SICRH_ESDHC_C_GPIO (3 << 26)
#define SICRH_GPIO_A_GPIO (0 << 24)
#define SICRH_GPIO_A_TSEC2 (1 << 24)
#define SICRH_GPIO_B_GPIO (0 << 22)
#define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22)
#define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22)
#define SICRH_IEEE1588_A_TMR (1 << 20)
#define SICRH_IEEE1588_A_GPIO (3 << 20)
#define SICRH_USB (1 << 18)
#define SICRH_GTM_GTM (1 << 16)
#define SICRH_GTM_GPIO (3 << 16)
#define SICRH_IEEE1588_B_TMR (1 << 14)
#define SICRH_IEEE1588_B_GPIO (3 << 14)
#define SICRH_ETSEC2_CRS (1 << 12)
#define SICRH_ETSEC2_GPIO (3 << 12)
#define SICRH_GPIOSEL_0 (0 << 8)
#define SICRH_GPIOSEL_1 (1 << 8)
#define SICRH_TMROBI_V3P3 (0 << 4)
#define SICRH_TMROBI_V2P5 (1 << 4)
#define SICRH_TSOBI1_V3P3 (0 << 1)
#define SICRH_TSOBI1_V2P5 (1 << 1)
#define SICRH_TSOBI2_V3P3 (0 << 0)
#define SICRH_TSOBI2_V2P5 (1 << 0)
#endif
/* SWCRR - System Watchdog Control Register