Configuration changes for ADS5121 Rev 3
ADS5121 Rev 3 board is now the default config
config targets are now
ads5121_config
Rev 3 board with
PCI
M41T62 on board RTC
512MB DRAM
ads5121_rev2_config
Rev 2 board with
No PCI
256MB DRAM
Signed-off-by: Martha Marx <mmarx@silicontkx.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: John Rigby <jrigby@freescale.com>
This commit is contained in:
Martha Marx
John Rigby
parent
16bee7b0dc
commit
f31c49db2a
9
Makefile
9
Makefile
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@ -750,12 +750,11 @@ motionpro_config: unconfig
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## MPC512x Systems
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#########################################################################
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ads5121_config \
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ads5121_PCI_config \
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: unconfig
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ads5121_rev2_config \
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: unconfig
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@mkdir -p $(obj)include
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@if [ "$(findstring _PCI_,$@)" ] ; then \
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echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
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$(XECHO) "... with PCI enabled" ; \
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@if [ "$(findstring rev2,$@)" ] ; then \
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echo "#define CONFIG_ADS5121_REV2 1" > $(obj)include/config.h; \
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fi
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@$(MKCONFIG) -a ads5121 ppc mpc512x ads5121
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@ -0,0 +1,9 @@
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To configure for the current (Rev 3.x) ADS5121
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make ads5121_config
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This will automatically include PCI, the Real Time CLock, add backup flash
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ability and set the correct frequency and memory configuration.
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To configure for the older Rev 2 ADS5121 type (this will not have PCI)
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make ads5121_rev2_config
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@ -26,7 +26,9 @@
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#include <asm/bitops.h>
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#include <command.h>
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#include <fdt_support.h>
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#ifdef CONFIG_MISC_INIT_R
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#include <i2c.h>
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#endif
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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@ -75,8 +77,21 @@ int board_early_init_f (void)
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* Without this the flash identification routine fails, as it needs to issue
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* write commands in order to establish the device ID.
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*/
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*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
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#ifdef CONFIG_ADS5121_REV2
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*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
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#else
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if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) {
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*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
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} else {
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/* running from Backup flash */
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*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32;
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}
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#endif
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/*
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* Configure Flash Speed
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*/
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*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
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/*
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* Enable clocks
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*/
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@ -133,8 +133,9 @@ void watchdog_reset (void)
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#ifdef CONFIG_OF_LIBFDT
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void ft_cpu_setup(void *blob, bd_t *bd)
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{
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char * cpu_path = "/cpus/" OF_CPU;
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char * eth_path = "/" OF_SOC "/ethernet@2800";
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char *cpu_path = "/cpus/" OF_CPU;
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char *eth_path = "/" OF_SOC "/ethernet@2800";
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char *eth_path_old = "/" OF_SOC_OLD "/ethernet@2800";
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do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
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do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
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@ -144,5 +145,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
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/* this is so old kernels with old device trees will boot */
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do_fixup_by_path_u32(blob, "/" OF_SOC_OLD, "bus-frequency", bd->bi_ipsfreq, 0);
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do_fixup_by_path(blob, eth_path_old, "local-mac-address",
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bd->bi_enetaddr, 6, 0);
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do_fixup_by_path(blob, eth_path_old, "address", bd->bi_enetaddr, 6, 0);
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}
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#endif
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@ -58,7 +58,12 @@
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/* CONFIG_PCI is defined at config time */
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#ifdef CONFIG_ADS5121_REV2
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#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
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#else
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#define CFG_MPC512X_CLKIN 33333333 /* in Hz */
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#define CONFIG_PCI
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#endif
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R
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@ -72,7 +77,11 @@
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/*
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* DDR Setup - manually set all parameters as there's no SPD etc.
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*/
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#ifdef CONFIG_ADS5121_REV2
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#define CFG_DDR_SIZE 256 /* MB */
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#else
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#define CFG_DDR_SIZE 512 /* MB */
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#endif
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#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
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#define CFG_SDRAM_BASE CFG_DDR_BASE
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@ -120,14 +129,20 @@
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* [09:05] DRAM tRP:
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* [04:00] DRAM tRPA
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*/
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#ifdef CONFIG_ADS5121_REV2
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#define CFG_MDDRC_SYS_CFG 0xF8604A00
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#define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00
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#define CFG_MDDRC_TIME_CFG1 0x54EC1168
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#define CFG_MDDRC_TIME_CFG2 0x35210864
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#else
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#define CFG_MDDRC_SYS_CFG 0xFA804A00
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#define CFG_MDDRC_SYS_CFG_RUN 0xEA804A00
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#define CFG_MDDRC_TIME_CFG1 0x68EC1168
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#define CFG_MDDRC_TIME_CFG2 0x34310864
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#endif
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#define CFG_MDDRC_SYS_CFG_EN 0xF0000000
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#define CFG_MDDRC_TIME_CFG0 0x00003D2E
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#define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E
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#define CFG_MDDRC_TIME_CFG1 0x54EC1168
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#define CFG_MDDRC_TIME_CFG2 0x35210864
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#define CFG_MICRON_NOP 0x01380000
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#define CFG_MICRON_PCHG_ALL 0x01100400
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@ -166,12 +181,17 @@
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/*
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* NOR FLASH on the Local Bus
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*/
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#undef CONFIG_BKUP_FLASH
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#define CFG_FLASH_CFI /* use the Common Flash Interface */
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#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
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#ifdef CONFIG_BKUP_FLASH
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#define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */
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#define CFG_FLASH_SIZE 0x00800000 /* max flash size in bytes */
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#else
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#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */
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#define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */
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#endif
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#define CFG_FLASH_USE_BUFFER_WRITE
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
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#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
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@ -287,14 +307,13 @@
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#define CONFIG_NET_MULTI
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#define CONFIG_PHY_ADDR 0x1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_FEC_AN_TIMEOUT 1
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#if 0
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/*
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* Configure on-board RTC
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*/
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#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
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#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
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#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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#endif
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/*
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* Environment
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@ -303,7 +322,11 @@
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/* This has to be a multiple of the Flash sector size */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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#define CFG_ENV_SIZE 0x2000
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#ifdef CONFIG_BKUP_FLASH
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#define CFG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */
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#else
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#define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
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#endif
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
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@ -322,6 +345,7 @@
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_DATE
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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