Header file update, clean up and cache handling
Replaced immap_5329.h and m5329.h with immap.h. Included cache_invalid. Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChungLiew
John Rigby
parent
2e3f25ae90
commit
f2208fbc2e
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@ -2,7 +2,7 @@
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2007
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* (C) Copyright 2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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@ -28,8 +28,7 @@
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#include <malloc.h>
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#include <asm/fec.h>
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#include <asm/m5329.h>
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#include <asm/immap_5329.h>
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#include <asm/immap.h>
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#include <command.h>
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#include <config.h>
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@ -41,17 +40,8 @@
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#undef MII_DEBUG
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/* Ethernet Transmit and Receive Buffers */
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#define DBUF_LENGTH 1520
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#define TX_BUF_CNT 2
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/*
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NOTE: PKT_MAXBUF_SIZE must be larger or equal to PKT_MAXBLR_SIZE,
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see M54455 User Manual for MAX_FL of Receive Control Register for more
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description. If PKT_MAXBUF_SIZE set to 1518, the FEC bandwidth will
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reduce to about 20~40% of normal bandwidth. Changing PKT_MAXBLR_SIZE
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will not make any improvement on speed
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*/
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#define DBUF_LENGTH 1520
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#define TX_BUF_CNT 2
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#define PKT_MAXBUF_SIZE 1518
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#define PKT_MINBUF_SIZE 64
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#define PKT_MAXBLR_SIZE 1520
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@ -102,12 +92,6 @@ struct fec_info_s fec_info[] = {
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#endif
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};
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/*
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* FEC Ethernet Tx and Rx buffer descriptors allocated at the
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* immr->udata_bd address on Dual-Port RAM
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* Provide for Double Buffering
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*/
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int fec_send(struct eth_device *dev, volatile void *packet, int length);
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int fec_recv(struct eth_device *dev);
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int fec_init(struct eth_device *dev, bd_t * bd);
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@ -166,15 +150,23 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
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* Wait for ready
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*/
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j = 0;
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#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
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icache_invalid();
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#endif
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while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
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(j < MCFFEC_TOUT_LOOP)) {
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udelay(1);
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j++;
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#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
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icache_invalid();
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#endif
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}
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if (j >= MCFFEC_TOUT_LOOP) {
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printf("TX not ready\n");
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}
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#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
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icache_invalid();
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#endif
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info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
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info->txbd[info->txIdx].cbd_datlen = length;
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info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
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@ -183,10 +175,16 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
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fecp->tdar = 0x01000000; /* Descriptor polling active */
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j = 0;
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#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
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icache_invalid();
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#endif
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while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
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(j < MCFFEC_TOUT_LOOP)) {
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udelay(1);
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j++;
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#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
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icache_invalid();
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#endif
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}
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if (j >= MCFFEC_TOUT_LOOP) {
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printf("TX timeout\n");
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@ -199,6 +197,9 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
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#endif
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/* return only status bits */ ;
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#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
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icache_invalid();
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#endif
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rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
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info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
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@ -257,12 +258,6 @@ int fec_recv(struct eth_device *dev)
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return length;
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}
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/**************************************************************
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*
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* FEC Ethernet Initialization Routine
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*
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*************************************************************/
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#ifdef ET_DEBUG
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void dbgFecRegs(struct eth_device *dev)
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{
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@ -419,7 +414,7 @@ int fec_init(struct eth_device *dev, bd_t * bd)
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struct fec_info_s *info = dev->priv;
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volatile fec_t *fecp = (fec_t *) (info->iobase);
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int i;
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u8 *ea;
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u8 *ea = NULL;
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fecpin_setclear(dev, 1);
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@ -549,7 +544,9 @@ int mcffec_initialize(bd_t * bis)
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for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
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dev = (struct eth_device *)malloc(sizeof *dev);
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dev =
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(struct eth_device *)memalign(CFG_CACHELINE_SIZE,
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sizeof *dev);
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if (dev == NULL)
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hang();
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@ -565,16 +562,19 @@ int mcffec_initialize(bd_t * bis)
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/* setup Receive and Transmit buffer descriptor */
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fec_info[i].rxbd =
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(cbd_t *) memalign(32, (PKTBUFSRX * sizeof(cbd_t) + 31));
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(cbd_t *) memalign(CFG_CACHELINE_SIZE,
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(PKTBUFSRX * sizeof(cbd_t)));
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fec_info[i].txbd =
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(cbd_t *) memalign(32, (TX_BUF_CNT * sizeof(cbd_t) + 31));
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fec_info[i].txbuf = (char *)memalign(32, DBUF_LENGTH + 31);
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(cbd_t *) memalign(CFG_CACHELINE_SIZE,
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(TX_BUF_CNT * sizeof(cbd_t)));
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fec_info[i].txbuf =
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(char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH);
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#ifdef ET_DEBUG
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printf("rxbd %x txbd %x\n",
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(int)fec_info[i].rxbd, (int)fec_info[i].txbd);
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#endif
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fec_info[i].phy_name = (char *)malloc(32);
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fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32);
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eth_register(dev);
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