ppc4xx: Big lwmon5 board support rework/update
This patch brings the lwmon5 board support up-to-date. Here a summary of the changes: lwmon5 board port related: - GPIO's changed to control the LSB transmitter - Reset USB PHY's upon power-up - Enable CAN upon power-up - USB init error workaround (errata CHIP_6) - EBC: Enable burstmode and modify the timings for the GDC memory - EBC: Speed up NOR flash timings lwmon5 board POST related: - Add FPGA memory test - Add GDC memory test - DSP POST reworked - SYSMON POST: Fix handling of negative temperatures - Add output for sysmon1 POST - HW-watchdog min. time test reworked Additionally some coding-style changes were done. Signed-off-by: Sascha Laue <sascha.laue@liebherr.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Sascha Laue
Stefan Roese
parent
d0e6665a24
commit
f14ae4180a
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@ -45,6 +45,10 @@ static int compare_magic (uchar *kbd_data, uchar *str);
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/*--------------------- Local macros and constants --------------------*/
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#define _NOT_USED_ 0xFFFFFFFF
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/*------------------------- dspic io expander -----------------------*/
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#define DSPIC_PON_STATUS_REG 0x80A
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#define DSPIC_PON_INV_STATUS_REG 0x80C
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#define DSPIC_PON_KEY_REG 0x810
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/*------------------------- Keyboard controller -----------------------*/
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/* command codes */
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#define KEYBD_CMD_READ_KEYS 0x01
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@ -75,6 +79,7 @@ static int compare_magic (uchar *kbd_data, uchar *str);
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/* maximum number of "magic" key codes that can be assigned */
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static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
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static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
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static uchar *key_match (uchar *);
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@ -167,6 +172,23 @@ static void kbd_init (void)
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}
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}
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/* Read a register from the dsPIC. */
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int _dspic_read(ushort reg, ushort *data)
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{
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uchar buf[sizeof(*data)];
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int rval;
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if (i2c_read(dspic_addr, reg, 2, buf, 2))
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return -1;
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rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
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*data = (buf[0] << 8) | buf[1];
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return rval;
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}
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/***********************************************************************
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F* Function: int misc_init_r (void) P*A*Z*
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*
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@ -197,6 +219,7 @@ int misc_init_r_kbd (void)
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uchar kbd_init_status = gd->kbd_status >> 8;
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uchar kbd_status = gd->kbd_status;
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uchar val;
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ushort data, inv_data;
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char *str;
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int i;
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@ -231,9 +254,31 @@ int misc_init_r_kbd (void)
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i2c_write (kbd_addr, 0, 0, &val, 1);
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i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
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/* read out start key from bse01 received via can */
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_dspic_read(DSPIC_PON_STATUS_REG, &data);
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/* check highbyte from status register */
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if (data > 0xFF) {
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_dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
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/* check inverse data */
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if ((data+inv_data) == 0xFFFF) {
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/* don't overwrite local key */
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if (kbd_data[1] == 0) {
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/* read key value */
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_dspic_read(DSPIC_PON_KEY_REG, &data);
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str = (char *)&data;
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/* swap bytes */
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kbd_data[1] = str[1];
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kbd_data[2] = str[0];
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printf("CAN received startkey: 0x%X\n", data);
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}
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}
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}
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for (i = 0; i < KEYBD_DATALEN; ++i) {
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sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
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}
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setenv ("keybd", keybd_env);
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str = strdup ((char *)key_match (kbd_data)); /* decode keys */
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2007
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* (C) Copyright 2007-2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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@ -24,10 +24,13 @@
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#include <asm/processor.h>
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#include <asm/ppc4xx-gpio.h>
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#include <asm/io.h>
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#include <post.h>
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#include <flash.h>
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#include <mtd/cfi_flash.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
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ulong flash_get_size(ulong base, int banknum);
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int misc_init_r_kbd(void);
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@ -97,16 +100,18 @@ int board_early_init_f(void)
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gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
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#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
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gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1);
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/* enable the LSB transmitter */
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gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
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/* enable the CAN transmitter */
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gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
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reg = 0; /* reuse as counter */
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out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
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in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
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& ~CONFIG_SYS_DSPIC_TEST_MASK);
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while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
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while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
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udelay(1000);
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}
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gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0);
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if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
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/* set "boot error" flag */
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out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
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@ -135,9 +140,61 @@ int board_early_init_f(void)
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return 0;
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}
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/*---------------------------------------------------------------------------+
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| misc_init_r.
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+---------------------------------------------------------------------------*/
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/*
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* Override weak default with board specific version
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*/
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phys_addr_t cfi_flash_bank_addr(int bank)
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{
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return lwmon5_cfi_flash_bank_addr[bank];
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}
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/*
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* Override the weak default mapping function with a board specific one
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*/
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u32 flash_get_bank_size(int cs, int idx)
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{
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return flash_info[idx].size;
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}
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int board_early_init_r(void)
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{
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u32 val0, val1;
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/*
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* lwmon5 is manufactured in 2 different board versions:
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* The lwmon5a board has 64MiB NOR flash instead of the
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* 128MiB of the original lwmon5. Unfortunately the CFI driver
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* will report 2 banks of 64MiB even for the smaller flash
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* chip, since the bank is mirrored. To fix this, we bring
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* one bank into CFI query mode and read its response. This
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* enables us to detect the real number of flash devices/
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* banks which will be used later on by the common CFI driver.
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*/
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/* Put bank 0 into CFI command mode and read */
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out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
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val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
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val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
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/* Reset flash again out of query mode */
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out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
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/* When not identical, we have 2 different flash devices/banks */
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if (val0 != val1)
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return 0;
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/*
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* Now we're sure that we're running on a LWMON5a board with
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* only 64MiB NOR flash in one bank:
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*
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* Set flash base address and bank count for CFI driver probing.
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*/
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cfi_flash_num_flash_banks = 1;
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lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
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return 0;
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}
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int misc_init_r(void)
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{
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u32 pbcr;
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@ -145,7 +202,7 @@ int misc_init_r(void)
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u32 reg;
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unsigned long usb2d0cr = 0;
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unsigned long usb2phy0cr, usb2h0cr = 0;
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unsigned long sdr0_pfc1;
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unsigned long sdr0_pfc1, sdr0_srst;
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/*
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* FLASH stuff...
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@ -158,32 +215,7 @@ int misc_init_r(void)
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gd->bd->bi_flashoffset = 0;
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mfebc(PB0CR, pbcr);
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switch (gd->bd->bi_flashsize) {
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case 1 << 20:
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size_val = 0;
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break;
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case 2 << 20:
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size_val = 1;
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break;
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case 4 << 20:
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size_val = 2;
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break;
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case 8 << 20:
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size_val = 3;
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break;
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case 16 << 20:
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size_val = 4;
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break;
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case 32 << 20:
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size_val = 5;
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break;
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case 64 << 20:
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size_val = 6;
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break;
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case 128 << 20:
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size_val = 7;
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break;
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}
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size_val = ffs(gd->bd->bi_flashsize) - 21;
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
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mtebc(PB0CR, pbcr);
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@ -193,53 +225,92 @@ int misc_init_r(void)
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flash_get_size(gd->bd->bi_flashstart, 0);
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CONFIG_SYS_MONITOR_LEN,
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0xffffffff,
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&flash_info[1]);
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flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
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&flash_info[cfi_flash_num_flash_banks - 1]);
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/* Env protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR_REDUND,
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CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[1]);
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flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
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CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[cfi_flash_num_flash_banks - 1]);
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/*
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* USB suff...
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*/
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/* Reset USB */
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/* Reset of USB2PHY0 must be active at least 10 us */
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mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
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udelay(2000);
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mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
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SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
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SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
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udelay(2000);
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/* Errata CHIP_6 */
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/* 1. Set internal PHY configuration */
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/* SDR Setting */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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mfsdr(SDR0_USB0, usb2d0cr);
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mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mfsdr(SDR0_USB2H0CR, usb2h0cr);
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
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usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
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usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
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usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
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usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
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usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
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/* An 8-bit/60MHz interface is the only possible alternative
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when connecting the Device to the PHY */
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usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
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usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
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/*
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* An 8-bit/60MHz interface is the only possible alternative
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* when connecting the Device to the PHY
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*/
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usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
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usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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mtsdr(SDR0_USB0, usb2d0cr);
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mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mtsdr(SDR0_USB2H0CR, usb2h0cr);
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/* 2. De-assert internal PHY reset */
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mfsdr(SDR0_SRST1, sdr0_srst);
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sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
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mtsdr(SDR0_SRST1, sdr0_srst);
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/* 3. Wait for more than 1 ms */
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udelay(2000);
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/* 4. De-assert USB 2.0 Host main reset */
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mfsdr(SDR0_SRST0, sdr0_srst);
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sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
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mtsdr(SDR0_SRST0, sdr0_srst);
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udelay(1000);
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/* 5. De-assert reset of OPB2 cores */
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mfsdr(SDR0_SRST1, sdr0_srst);
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sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
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sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
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sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
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mtsdr(SDR0_SRST1, sdr0_srst);
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udelay(1000);
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/* 6. Set EHCI Configure FLAG */
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/* 7. Reassert internal PHY reset: */
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mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
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udelay(1000);
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/*
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* Clear resets
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*/
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udelay (1000);
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mtsdr(SDR0_SRST1, 0x00000000);
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udelay (1000);
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mtsdr(SDR0_SRST0, 0x00000000);
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printf("USB: Host(int phy) Device(ext phy)\n");
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@ -264,7 +335,7 @@ int checkboard(void)
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{
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char *s = getenv("serial#");
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printf("Board: lwmon5");
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puts("Board: lwmon5");
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if (s != NULL) {
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puts(", serial# ");
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@ -331,34 +402,33 @@ U_BOOT_CMD(
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extern GraphicDevice mb862xx;
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static const gdc_regs init_regs [] =
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{
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{0x0100, 0x00000f00},
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{0x0020, 0x801401df},
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{0x0024, 0x00000000},
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{0x0028, 0x00000000},
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{0x002c, 0x00000000},
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{0x0110, 0x00000000},
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{0x0114, 0x00000000},
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{0x0118, 0x01df0280},
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{0x0004, 0x031f0000},
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{0x0008, 0x027f027f},
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{0x000c, 0x015f028f},
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{0x0010, 0x020c0000},
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{0x0014, 0x01df01ea},
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{0x0018, 0x00000000},
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{0x001c, 0x01e00280},
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{0x0100, 0x80010f00},
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{0x0, 0x0}
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static const gdc_regs init_regs [] = {
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{ 0x0100, 0x00000f00 },
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{ 0x0020, 0x801401df },
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{ 0x0024, 0x00000000 },
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{ 0x0028, 0x00000000 },
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{ 0x002c, 0x00000000 },
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{ 0x0110, 0x00000000 },
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{ 0x0114, 0x00000000 },
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{ 0x0118, 0x01df0280 },
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{ 0x0004, 0x031f0000 },
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||||
{ 0x0008, 0x027f027f },
|
||||
{ 0x000c, 0x015f028f },
|
||||
{ 0x0010, 0x020c0000 },
|
||||
{ 0x0014, 0x01df01ea },
|
||||
{ 0x0018, 0x00000000 },
|
||||
{ 0x001c, 0x01e00280 },
|
||||
{ 0x0100, 0x80010f00 },
|
||||
{ 0x0, 0x0 }
|
||||
};
|
||||
|
||||
const gdc_regs *board_get_regs (void)
|
||||
const gdc_regs *board_get_regs(void)
|
||||
{
|
||||
return init_regs;
|
||||
}
|
||||
|
||||
/* Returns Lime base address */
|
||||
unsigned int board_video_init (void)
|
||||
unsigned int board_video_init(void)
|
||||
{
|
||||
/*
|
||||
* Reset Lime controller
|
||||
|
|
@ -375,7 +445,7 @@ unsigned int board_video_init (void)
|
|||
return CONFIG_SYS_LIME_BASE_0;
|
||||
}
|
||||
|
||||
#define DEFAULT_BRIGHTNESS 0x64
|
||||
#define DEFAULT_BRIGHTNESS 0x64
|
||||
|
||||
static void board_backlight_brightness(int brightness)
|
||||
{
|
||||
|
|
@ -390,7 +460,7 @@ static void board_backlight_brightness(int brightness)
|
|||
}
|
||||
}
|
||||
|
||||
void board_backlight_switch (int flag)
|
||||
void board_backlight_switch(int flag)
|
||||
{
|
||||
char * param;
|
||||
int rc;
|
||||
|
|
@ -410,15 +480,14 @@ void board_backlight_switch (int flag)
|
|||
/*
|
||||
* Return text to be printed besides the logo.
|
||||
*/
|
||||
void video_get_info_str (int line_number, char *info)
|
||||
void video_get_info_str(int line_number, char *info)
|
||||
{
|
||||
if (line_number == 1) {
|
||||
strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
|
||||
} else {
|
||||
if (line_number == 1)
|
||||
strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
|
||||
else
|
||||
info [0] = '\0';
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_CONSOLE_EXTRA_INFO */
|
||||
#endif /* CONFIG_VIDEO */
|
||||
|
||||
void board_reset(void)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2007-2008
|
||||
* (C) Copyright 2007-2010
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
|
|
@ -18,58 +18,63 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
/*
|
||||
* lwmon5.h - configuration for lwmon5 board
|
||||
***********************************************************************/
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Liebherr extra version info
|
||||
*/
|
||||
#define CONFIG_IDENT_STRING " - v2.0"
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
#define CONFIG_LWMON5 1 /* Board is lwmon5 */
|
||||
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
#define CONFIG_BOARD_RESET 1 /* Call board_reset */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
|
||||
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
|
||||
#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
|
||||
#define CONFIG_MISC_INIT_R /* Call misc_init_r */
|
||||
#define CONFIG_BOARD_RESET /* Call board_reset */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
|
||||
*/
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of U-Boot */
|
||||
#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
|
||||
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
|
||||
|
||||
#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
|
||||
#define CONFIG_SYS_LIME_BASE_0 0xc0000000
|
||||
#define CONFIG_SYS_LIME_BASE_1 0xc1000000
|
||||
#define CONFIG_SYS_LIME_BASE_2 0xc2000000
|
||||
#define CONFIG_SYS_LIME_BASE_3 0xc3000000
|
||||
#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
|
||||
#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
|
||||
#define CONFIG_SYS_LIME_BASE_0 0xc0000000
|
||||
#define CONFIG_SYS_LIME_BASE_1 0xc1000000
|
||||
#define CONFIG_SYS_LIME_BASE_2 0xc2000000
|
||||
#define CONFIG_SYS_LIME_BASE_3 0xc3000000
|
||||
#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
|
||||
#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
|
||||
#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
|
||||
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
|
||||
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
|
||||
#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
|
||||
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
|
||||
#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
|
||||
#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
|
||||
#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
|
||||
|
||||
#define CONFIG_SYS_USB2D0_BASE 0xe0000100
|
||||
#define CONFIG_SYS_USB_DEVICE 0xe0000000
|
||||
#define CONFIG_SYS_USB_HOST 0xe0000400
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer
|
||||
*----------------------------------------------------------------------*/
|
||||
/*
|
||||
* Initial RAM & stack pointer
|
||||
*
|
||||
* On LWMON5 we use D-cache as init-ram and stack pointer. We also move
|
||||
* the POST_WORD from OCM to a 440EPx register that preserves it's
|
||||
* content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
|
||||
|
|
@ -77,18 +82,18 @@
|
|||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
|
||||
#define CONFIG_SYS_INIT_RAM_END (4 << 10)
|
||||
#define CONFIG_SYS_INIT_RAM_END (4 << 10)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data*/
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
|
||||
CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
/* unused GPT0 COMP reg */
|
||||
#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
|
||||
/* unused GPT0 COMP reg */
|
||||
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
|
||||
/* 440EPx errata CHIP 11 */
|
||||
#define CONFIG_SYS_OCM_SIZE (16 << 10)
|
||||
/* 440EPx errata CHIP 11: don't use last 4kbytes */
|
||||
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
|
||||
|
||||
/* Additional registers for watchdog timer post test */
|
||||
|
||||
#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
|
||||
#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
|
||||
#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
|
||||
|
|
@ -100,9 +105,9 @@
|
|||
#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
|
||||
#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
|
|
@ -110,77 +115,79 @@
|
|||
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
|
||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SERIAL_MULTI 1
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
|
||||
#define CONFIG_SYS_FLASH0 0xFC000000
|
||||
#define CONFIG_SYS_FLASH1 0xF8000000
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
|
||||
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
|
||||
#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
|
||||
*/
|
||||
#define CONFIG_SYS_MBYTES_SDRAM 256
|
||||
#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
|
||||
#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
|
||||
#define CONFIG_DDR_ECC 1 /* enable ECC */
|
||||
#define CONFIG_SYS_POST_ECC_ON CONFIG_SYS_POST_ECC
|
||||
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
|
||||
#define CONFIG_DDR_ECC /* enable ECC */
|
||||
|
||||
/* POST support */
|
||||
#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
|
||||
CONFIG_SYS_POST_CPU | \
|
||||
CONFIG_SYS_POST_ECC_ON | \
|
||||
CONFIG_SYS_POST_ETHER | \
|
||||
CONFIG_SYS_POST_FPU | \
|
||||
CONFIG_SYS_POST_I2C | \
|
||||
CONFIG_SYS_POST_MEMORY | \
|
||||
CONFIG_SYS_POST_OCM | \
|
||||
CONFIG_SYS_POST_RTC | \
|
||||
CONFIG_SYS_POST_SPR | \
|
||||
CONFIG_SYS_POST_UART | \
|
||||
CONFIG_SYS_POST_SYSMON | \
|
||||
CONFIG_SYS_POST_WATCHDOG | \
|
||||
CONFIG_SYS_POST_DSP | \
|
||||
CONFIG_SYS_POST_BSPEC1 | \
|
||||
CONFIG_SYS_POST_BSPEC2 | \
|
||||
CONFIG_SYS_POST_BSPEC3 | \
|
||||
CONFIG_SYS_POST_BSPEC4 | \
|
||||
#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
|
||||
CONFIG_SYS_POST_CPU | \
|
||||
CONFIG_SYS_POST_ECC | \
|
||||
CONFIG_SYS_POST_ETHER | \
|
||||
CONFIG_SYS_POST_FPU | \
|
||||
CONFIG_SYS_POST_I2C | \
|
||||
CONFIG_SYS_POST_MEMORY | \
|
||||
CONFIG_SYS_POST_OCM | \
|
||||
CONFIG_SYS_POST_RTC | \
|
||||
CONFIG_SYS_POST_SPR | \
|
||||
CONFIG_SYS_POST_UART | \
|
||||
CONFIG_SYS_POST_SYSMON | \
|
||||
CONFIG_SYS_POST_WATCHDOG | \
|
||||
CONFIG_SYS_POST_DSP | \
|
||||
CONFIG_SYS_POST_BSPEC1 | \
|
||||
CONFIG_SYS_POST_BSPEC2 | \
|
||||
CONFIG_SYS_POST_BSPEC3 | \
|
||||
CONFIG_SYS_POST_BSPEC4 | \
|
||||
CONFIG_SYS_POST_BSPEC5)
|
||||
|
||||
#define CONFIG_POST_WATCHDOG {\
|
||||
/* Define here the base-addresses of the UARTs to test in POST */
|
||||
#define CONFIG_SYS_POST_UART_TABLE { UART0_BASE, UART1_BASE }
|
||||
|
||||
#define CONFIG_POST_WATCHDOG { \
|
||||
"Watchdog timer test", \
|
||||
"watchdog", \
|
||||
"This test checks the watchdog timer.", \
|
||||
|
|
@ -188,10 +195,10 @@
|
|||
&lwmon5_watchdog_post_test, \
|
||||
NULL, \
|
||||
NULL, \
|
||||
CONFIG_SYS_POST_WATCHDOG \
|
||||
CONFIG_SYS_POST_WATCHDOG \
|
||||
}
|
||||
|
||||
#define CONFIG_POST_BSPEC1 {\
|
||||
#define CONFIG_POST_BSPEC1 { \
|
||||
"dsPIC init test", \
|
||||
"dspic_init", \
|
||||
"This test returns result of dsPIC READY test run earlier.", \
|
||||
|
|
@ -199,10 +206,10 @@
|
|||
&dspic_init_post_test, \
|
||||
NULL, \
|
||||
NULL, \
|
||||
CONFIG_SYS_POST_BSPEC1 \
|
||||
CONFIG_SYS_POST_BSPEC1 \
|
||||
}
|
||||
|
||||
#define CONFIG_POST_BSPEC2 {\
|
||||
#define CONFIG_POST_BSPEC2 { \
|
||||
"dsPIC test", \
|
||||
"dspic", \
|
||||
"This test gets result of dsPIC POST and dsPIC version.", \
|
||||
|
|
@ -210,32 +217,32 @@
|
|||
&dspic_post_test, \
|
||||
NULL, \
|
||||
NULL, \
|
||||
CONFIG_SYS_POST_BSPEC2 \
|
||||
CONFIG_SYS_POST_BSPEC2 \
|
||||
}
|
||||
|
||||
#define CONFIG_POST_BSPEC3 {\
|
||||
#define CONFIG_POST_BSPEC3 { \
|
||||
"FPGA test", \
|
||||
"fpga", \
|
||||
"This test checks FPGA registers and memory.", \
|
||||
POST_RAM | POST_ALWAYS, \
|
||||
POST_RAM | POST_ALWAYS | POST_MANUAL, \
|
||||
&fpga_post_test, \
|
||||
NULL, \
|
||||
NULL, \
|
||||
CONFIG_SYS_POST_BSPEC3 \
|
||||
CONFIG_SYS_POST_BSPEC3 \
|
||||
}
|
||||
|
||||
#define CONFIG_POST_BSPEC4 {\
|
||||
#define CONFIG_POST_BSPEC4 { \
|
||||
"GDC test", \
|
||||
"gdc", \
|
||||
"This test checks GDC registers and memory.", \
|
||||
POST_RAM | POST_ALWAYS, \
|
||||
POST_RAM | POST_ALWAYS | POST_MANUAL,\
|
||||
&gdc_post_test, \
|
||||
NULL, \
|
||||
NULL, \
|
||||
CONFIG_SYS_POST_BSPEC4 \
|
||||
CONFIG_SYS_POST_BSPEC4 \
|
||||
}
|
||||
|
||||
#define CONFIG_POST_BSPEC5 {\
|
||||
#define CONFIG_POST_BSPEC5 { \
|
||||
"SYSMON1 test", \
|
||||
"sysmon1", \
|
||||
"This test checks GPIO_62_EPX pin indicating power failure.", \
|
||||
|
|
@ -243,7 +250,7 @@
|
|||
&sysmon1_post_test, \
|
||||
NULL, \
|
||||
NULL, \
|
||||
CONFIG_SYS_POST_BSPEC5 \
|
||||
CONFIG_SYS_POST_BSPEC5 \
|
||||
}
|
||||
|
||||
#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
|
||||
|
|
@ -253,34 +260,53 @@
|
|||
#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
*/
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
|
||||
#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
|
||||
#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
|
||||
#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
|
||||
#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
|
||||
#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
|
||||
#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
|
||||
/* 64 byte page write mode using*/
|
||||
/* last 6 bits of the address */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
|
||||
|
||||
#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
|
||||
#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
|
||||
#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
|
||||
#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
|
||||
#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
|
||||
#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
|
||||
|
||||
#define I2C_ADDR_LIST { \
|
||||
CONFIG_SYS_I2C_RTC_ADDR, \
|
||||
CONFIG_SYS_I2C_EEPROM_CPU_ADDR, \
|
||||
CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
|
||||
CONFIG_SYS_I2C_DSPIC_ADDR, \
|
||||
CONFIG_SYS_I2C_DSPIC_2_ADDR, \
|
||||
CONFIG_SYS_I2C_DSPIC_KEYB_ADDR, \
|
||||
CONFIG_SYS_I2C_DSPIC_IO_ADDR }
|
||||
|
||||
/*
|
||||
* Pass open firmware flat tree
|
||||
*/
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
/* Update size in "reg" property of NOR FLASH device tree nodes */
|
||||
#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
|
||||
|
||||
#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
|
||||
#if 0
|
||||
#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
|
||||
#define CONFIG_AUTOBOOT_PROMPT \
|
||||
"\nEnter password - autoboot in %d sec...\n", bootdelay
|
||||
#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
|
||||
#endif
|
||||
|
||||
#define CONFIG_PREBOOT "setenv bootdelay 15"
|
||||
|
||||
|
|
@ -314,15 +340,11 @@
|
|||
"cp.b 200000 FFF80000 80000\0" \
|
||||
"upd=run load update\0" \
|
||||
"lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
|
||||
"source 200000\0" \
|
||||
"autoscr 200000\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
|
@ -410,9 +432,9 @@
|
|||
#define CONFIG_CMD_USB
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
|
|
@ -445,9 +467,9 @@
|
|||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* PCI stuff
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
|
||||
|
|
@ -461,29 +483,32 @@
|
|||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
|
||||
|
||||
#ifndef DEBUG
|
||||
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
|
||||
#endif
|
||||
#define CONFIG_WD_PERIOD 40000 /* in usec */
|
||||
#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
* have to be in the first 16 MB of memory, since this is
|
||||
* the maximum mapped by the 40x Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
|
||||
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* External Bus Controller (EBC) Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
|
||||
|
||||
/* Memory Bank 0 (NOR-FLASH) initialization */
|
||||
#define CONFIG_SYS_EBC_PB0AP 0x03050200
|
||||
#define CONFIG_SYS_EBC_PB0AP 0x03000280
|
||||
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
|
||||
|
||||
/* Memory Bank 1 (Lime) initialization */
|
||||
#define CONFIG_SYS_EBC_PB1AP 0x01004380
|
||||
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xdc000)
|
||||
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
|
||||
|
||||
/* Memory Bank 2 (FPGA) initialization */
|
||||
#define CONFIG_SYS_EBC_PB2AP 0x01004400
|
||||
|
|
@ -495,19 +520,27 @@
|
|||
|
||||
#define CONFIG_SYS_EBC_CFG 0xb8400000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Graphics (Fujitsu Lime)
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
/* SDRAM Clock frequency adjustment register */
|
||||
#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
|
||||
#if 1 /* 133MHz is not tested enough, use 100MHz for now */
|
||||
/* Lime Clock frequency is to set 100MHz */
|
||||
#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
|
||||
#if 0
|
||||
#else
|
||||
/* Lime Clock frequency for 133MHz */
|
||||
#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
|
||||
#endif
|
||||
|
||||
/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
|
||||
and pixel flare on display when 133MHz was configured. According to
|
||||
SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
|
||||
/* SDRAM Parameter register */
|
||||
#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
|
||||
/*
|
||||
* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
|
||||
* and pixel flare on display when 133MHz was configured. According to
|
||||
* SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
|
||||
* Grade
|
||||
*/
|
||||
#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
|
||||
#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
|
||||
#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
|
||||
|
|
@ -516,13 +549,15 @@
|
|||
#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* GPIO Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
#define CONFIG_SYS_GPIO_PHY1_RST 12
|
||||
#define CONFIG_SYS_GPIO_FLASH_WP 14
|
||||
#define CONFIG_SYS_GPIO_PHY0_RST 22
|
||||
#define CONFIG_SYS_GPIO_DSPIC_READY 51
|
||||
#define CONFIG_SYS_GPIO_CAN_ENABLE 53
|
||||
#define CONFIG_SYS_GPIO_LSB_ENABLE 54
|
||||
#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
|
||||
#define CONFIG_SYS_GPIO_HIGHSIDE 56
|
||||
#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
|
||||
|
|
@ -532,7 +567,7 @@
|
|||
#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
|
||||
#define CONFIG_SYS_GPIO_WATCHDOG 63
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* PPC440 GPIO Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
|
||||
|
|
|
|||
|
|
@ -33,20 +33,37 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define DSP_STATUS_REG 0xC4000008
|
||||
#define DSP_STATUS_REG 0xC4000008
|
||||
#define FPGA_STATUS_REG 0xC400000C
|
||||
|
||||
int dsp_post_test(int flags)
|
||||
{
|
||||
uint old_value;
|
||||
uint read_value;
|
||||
int ret;
|
||||
|
||||
/* momorize fpga status */
|
||||
old_value = in_be32((void *)FPGA_STATUS_REG);
|
||||
/* enable outputs */
|
||||
out_be32((void *)FPGA_STATUS_REG, 0x30);
|
||||
|
||||
/* generate sync signal */
|
||||
out_be32((void *)DSP_STATUS_REG, 0x300);
|
||||
udelay(5);
|
||||
out_be32((void *)DSP_STATUS_REG, 0);
|
||||
udelay(500);
|
||||
|
||||
/* read status */
|
||||
ret = 0;
|
||||
read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
|
||||
if (read_value != 0x3) {
|
||||
if (read_value != 0x03) {
|
||||
post_log("\nDSP status read %08X\n", read_value);
|
||||
ret = 1;
|
||||
}
|
||||
|
||||
/* restore fpga status */
|
||||
out_be32((void *)FPGA_STATUS_REG, old_value);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -38,14 +38,16 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
#define DSPIC_POST_ERROR_REG 0x800
|
||||
#define DSPIC_SYS_ERROR_REG 0x802
|
||||
#define DSPIC_VERSION_REG 0x804
|
||||
#define DSPIC_SYS_VERSION_REG 0x804
|
||||
#define DSPIC_FW_VERSION_REG 0x808
|
||||
|
||||
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
|
||||
|
||||
/* Verify that dsPIC ready test done early at hw init passed ok */
|
||||
int dspic_init_post_test(int flags)
|
||||
{
|
||||
if (in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) & CONFIG_SYS_DSPIC_TEST_MASK) {
|
||||
if (in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) &
|
||||
CONFIG_SYS_DSPIC_TEST_MASK) {
|
||||
post_log("dsPIC init test failed\n");
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -57,46 +59,60 @@ int dspic_init_post_test(int flags)
|
|||
|
||||
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC2
|
||||
/* Read a register from the dsPIC. */
|
||||
int dspic_read(ushort reg)
|
||||
int dspic_read(ushort reg, ushort *data)
|
||||
{
|
||||
uchar buf[2];
|
||||
uchar buf[sizeof(*data)];
|
||||
int rval;
|
||||
|
||||
if (i2c_read(CONFIG_SYS_I2C_DSPIC_IO_ADDR, reg, 2, buf, 2))
|
||||
return -1;
|
||||
rval = i2c_read(CONFIG_SYS_I2C_DSPIC_IO_ADDR, reg, sizeof(reg),
|
||||
buf, sizeof(*data));
|
||||
*data = (buf[0] << 8) | buf[1];
|
||||
|
||||
return (uint)((buf[0] << 8) | buf[1]);
|
||||
return rval;
|
||||
}
|
||||
|
||||
/* Verify error codes regs, display version */
|
||||
int dspic_post_test(int flags)
|
||||
{
|
||||
int data;
|
||||
ushort data;
|
||||
int ret = 0;
|
||||
|
||||
post_log("\n");
|
||||
data = dspic_read(DSPIC_VERSION_REG);
|
||||
if (data == -1) {
|
||||
post_log("dsPIC : failed read version\n");
|
||||
|
||||
/* read dspic FW-Version */
|
||||
if (dspic_read(DSPIC_FW_VERSION_REG, &data)) {
|
||||
post_log("dsPIC: failed read FW-Version\n");
|
||||
ret = 1;
|
||||
} else {
|
||||
post_log("dsPIC version: %u.%u\n",
|
||||
(data >> 8) & 0xFF, data & 0xFF);
|
||||
post_log("dsPIC FW-Version: %u.%u\n",
|
||||
(data >> 8) & 0xFF, data & 0xFF);
|
||||
}
|
||||
|
||||
data = dspic_read(DSPIC_POST_ERROR_REG);
|
||||
if (data != 0) ret = 1;
|
||||
if (data == -1) {
|
||||
post_log("dsPIC : failed read POST code\n");
|
||||
} else {
|
||||
post_log("dsPIC POST code 0x%04X\n", data);
|
||||
}
|
||||
|
||||
data = dspic_read(DSPIC_SYS_ERROR_REG);
|
||||
if (data == -1) {
|
||||
post_log("dsPIC : failed read system error\n");
|
||||
/* read dspic SYS-Version */
|
||||
if (dspic_read(DSPIC_SYS_VERSION_REG, &data)) {
|
||||
post_log("dsPIC: failed read version\n");
|
||||
ret = 1;
|
||||
} else {
|
||||
post_log("dsPIC SYS-ERROR code: 0x%04X\n", data);
|
||||
post_log("dsPIC SYS-Version: %u.%u\n",
|
||||
(data >> 8) & 0xFF, data & 0xFF);
|
||||
}
|
||||
|
||||
/* read dspic POST error code */
|
||||
if (dspic_read(DSPIC_POST_ERROR_REG, &data)) {
|
||||
post_log("dsPIC: failed read POST code\n");
|
||||
ret = 1;
|
||||
} else {
|
||||
post_log("dsPIC POST-ERROR code: 0x%04X\n", data);
|
||||
}
|
||||
|
||||
/* read dspic SYS error code */
|
||||
if ((data = dspic_read(DSPIC_SYS_ERROR_REG, &data))) {
|
||||
post_log("dsPIC: failed read system error\n");
|
||||
ret = 1;
|
||||
} else {
|
||||
post_log("dsPIC SYS-ERROR code: 0x%04X\n", data);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
*/
|
||||
|
||||
#include <post.h>
|
||||
|
||||
#include <watchdog.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
|
@ -38,18 +38,28 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#define FPGA_RAM_START 0xC4200000
|
||||
#define FPGA_RAM_END 0xC4203FFF
|
||||
#define FPGA_STAT 0xC400000C
|
||||
#define FPGA_BUFFER 0x00800000
|
||||
#define FPGA_RAM_SIZE (FPGA_RAM_END - FPGA_RAM_START + 1)
|
||||
|
||||
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
|
||||
|
||||
/* Testpattern for fpga memorytest */
|
||||
static uint pattern[] = {
|
||||
const static unsigned long pattern[] = {
|
||||
0xffffffff,
|
||||
0xaaaaaaaa,
|
||||
0xcccccccc,
|
||||
0xf0f0f0f0,
|
||||
0xff00ff00,
|
||||
0xffff0000,
|
||||
0x0000ffff,
|
||||
0x00ff00ff,
|
||||
0x0f0f0f0f,
|
||||
0x33333333,
|
||||
0x55555555,
|
||||
0xAAAAAAAA,
|
||||
0xAA5555AA,
|
||||
0x55AAAA55,
|
||||
0x0
|
||||
0x00000000,
|
||||
};
|
||||
|
||||
const static unsigned long otherpattern = 0x01234567;
|
||||
|
||||
static int one_scratch_test(uint value)
|
||||
{
|
||||
uint read_value;
|
||||
|
|
@ -62,51 +72,226 @@ static int one_scratch_test(uint value)
|
|||
read_value = in_be32((void *)FPGA_SCRATCH_REG);
|
||||
if (read_value != value) {
|
||||
post_log("FPGA SCRATCH test failed write %08X, read %08X\n",
|
||||
value, read_value);
|
||||
ret = 1;
|
||||
value, read_value);
|
||||
ret = -1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fpga_post_test1(ulong *start, ulong size, ulong val)
|
||||
{
|
||||
int ret = 0;
|
||||
ulong i = 0;
|
||||
ulong *mem = start;
|
||||
ulong readback;
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
mem[i] = val;
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
readback = mem[i];
|
||||
if (readback != val) {
|
||||
post_log("FPGA Memory error at %08x, "
|
||||
"wrote %08x, read %08x !\n",
|
||||
mem + i, val, readback);
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fpga_post_test2(ulong *start, ulong size)
|
||||
{
|
||||
int ret = 0;
|
||||
ulong i = 0;
|
||||
ulong *mem = start;
|
||||
ulong readback;
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
mem[i] = 1 << (i % 32);
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
readback = mem[i];
|
||||
if (readback != 1 << (i % 32)) {
|
||||
post_log("FPGA Memory error at %08x, "
|
||||
"wrote %08x, read %08x !\n",
|
||||
mem + i, 1 << (i % 32), readback);
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fpga_post_test3(ulong *start, ulong size)
|
||||
{
|
||||
int ret = 0;
|
||||
ulong i = 0;
|
||||
ulong *mem = start;
|
||||
ulong readback;
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
mem[i] = i;
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
readback = mem[i];
|
||||
if (readback != i) {
|
||||
post_log("FPGA Memory error at %08x, "
|
||||
"wrote %08x, read %08x !\n",
|
||||
mem + i, i, readback);
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fpga_post_test4(ulong *start, ulong size)
|
||||
{
|
||||
int ret = 0;
|
||||
ulong i = 0;
|
||||
ulong *mem = start;
|
||||
ulong readback;
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
mem[i] = ~i;
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
readback = mem[i];
|
||||
if (readback != ~i) {
|
||||
post_log("FPGA Memory error at %08x, "
|
||||
"wrote %08x, read %08x !\n",
|
||||
mem + i, ~i, readback);
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* FPGA Memory-pattern-test */
|
||||
static int fpga_mem_test(void * address)
|
||||
static int fpga_mem_test(void)
|
||||
{
|
||||
int ret = 1;
|
||||
uint read_value;
|
||||
uint old_value;
|
||||
uint i = 0;
|
||||
/* save content */
|
||||
old_value = in_be32(address);
|
||||
int ret = 0;
|
||||
ulong* start = (ulong *)FPGA_RAM_START;
|
||||
ulong size = FPGA_RAM_SIZE;
|
||||
|
||||
while (pattern[i] != 0) {
|
||||
out_be32(address, pattern[i]);
|
||||
/* read other location (protect against data lines capacity) */
|
||||
ret = in_be16((void *)FPGA_VERSION_REG);
|
||||
/* verify test pattern */
|
||||
read_value = in_be32(address);
|
||||
if (ret == 0)
|
||||
ret = fpga_post_test1(start, size, 0x00000000);
|
||||
|
||||
if (read_value != pattern[i]) {
|
||||
post_log("FPGA Memory test failed.");
|
||||
post_log(" write %08X, read %08X at address %08X\n",
|
||||
pattern[i], read_value, address);
|
||||
ret = 1;
|
||||
goto out;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
if (ret == 0)
|
||||
ret = fpga_post_test1(start, size, 0xffffffff);
|
||||
|
||||
if (ret == 0)
|
||||
ret = fpga_post_test1(start, size, 0x55555555);
|
||||
|
||||
if (ret == 0)
|
||||
ret = fpga_post_test1(start, size, 0xaaaaaaaa);
|
||||
|
||||
WATCHDOG_RESET();
|
||||
|
||||
if (ret == 0)
|
||||
ret = fpga_post_test2(start, size);
|
||||
|
||||
if (ret == 0)
|
||||
ret = fpga_post_test3(start, size);
|
||||
|
||||
if (ret == 0)
|
||||
ret = fpga_post_test4(start, size);
|
||||
|
||||
ret = 0;
|
||||
out:
|
||||
out_be32(address, old_value);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Verify FPGA addresslines */
|
||||
static int fpga_post_addrline(ulong *address, ulong *base, ulong size)
|
||||
{
|
||||
unsigned long *target;
|
||||
unsigned long *end;
|
||||
unsigned long readback;
|
||||
unsigned long xor;
|
||||
int ret = 0;
|
||||
|
||||
end = (ulong *)((ulong)base + size);
|
||||
xor = 0;
|
||||
|
||||
for (xor = sizeof(ulong); xor > 0; xor <<= 1) {
|
||||
target = (ulong*)((ulong)address ^ xor);
|
||||
if ((target >= base) && (target < end)) {
|
||||
*address = ~*target;
|
||||
readback = *target;
|
||||
|
||||
if (readback == *address) {
|
||||
post_log("Memory (address line) error at %08x"
|
||||
"XOR value %08x !\n",
|
||||
address, target, xor);
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Verify FPGA addresslines */
|
||||
static int fpga_post_dataline(ulong *address)
|
||||
{
|
||||
unsigned long temp32 = 0;
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pattern); i++) {
|
||||
*address = pattern[i];
|
||||
/*
|
||||
* Put a different pattern on the data lines: otherwise they
|
||||
* may float long enough to read back what we wrote.
|
||||
*/
|
||||
*(address + 1) = otherpattern;
|
||||
temp32 = *address;
|
||||
|
||||
if (temp32 != pattern[i]){
|
||||
post_log("Memory (date line) error at %08x, "
|
||||
"wrote %08x, read %08x !\n",
|
||||
address, pattern[i], temp32);
|
||||
ret = 1;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Verify FPGA, get version & memory size */
|
||||
int fpga_post_test(int flags)
|
||||
{
|
||||
uint address;
|
||||
uint old_value;
|
||||
ushort version;
|
||||
uint version;
|
||||
uint read_value;
|
||||
int ret = 0;
|
||||
|
||||
|
|
@ -120,24 +305,57 @@ int fpga_post_test(int flags)
|
|||
|
||||
out_be32((void *)FPGA_SCRATCH_REG, old_value);
|
||||
|
||||
version = in_be16((void *)FPGA_VERSION_REG);
|
||||
post_log("FPGA : version %u.%u\n",
|
||||
(version >> 8) & 0xFF, version & 0xFF);
|
||||
version = in_be32((void *)FPGA_VERSION_REG);
|
||||
post_log("FPGA version %u.%u\n",
|
||||
(version >> 8) & 0xFF, version & 0xFF);
|
||||
|
||||
/* Enable write to FPGA RAM */
|
||||
out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
|
||||
|
||||
read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, 0x4000);
|
||||
post_log("FPGA RAM size: %d bytes\n", read_value);
|
||||
/* get RAM size */
|
||||
read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, FPGA_RAM_SIZE);
|
||||
post_log("FPGA RAM size %d bytes\n", read_value);
|
||||
WATCHDOG_RESET();
|
||||
|
||||
for (address = 0; address < 0x1000; address++) {
|
||||
if (fpga_mem_test((void *)(FPGA_RAM_START + 4*address)) == 1) {
|
||||
ret = 1;
|
||||
goto out;
|
||||
}
|
||||
/* copy fpga memory to DDR2 RAM*/
|
||||
memcpy((void *)FPGA_BUFFER,(void *)FPGA_RAM_START, FPGA_RAM_SIZE);
|
||||
WATCHDOG_RESET();
|
||||
|
||||
/* Test datalines */
|
||||
if (fpga_post_dataline((ulong *)FPGA_RAM_START)) {
|
||||
ret = 1;
|
||||
goto out;
|
||||
}
|
||||
WATCHDOG_RESET();
|
||||
|
||||
/* Test addresslines */
|
||||
if (fpga_post_addrline((ulong *)FPGA_RAM_START,
|
||||
(ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) {
|
||||
ret = 1;
|
||||
goto out;
|
||||
}
|
||||
WATCHDOG_RESET();
|
||||
if (fpga_post_addrline((ulong *)FPGA_RAM_END - sizeof(long),
|
||||
(ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) {
|
||||
ret = 1;
|
||||
goto out;
|
||||
}
|
||||
WATCHDOG_RESET();
|
||||
|
||||
/* Memory Pattern Test */
|
||||
if (fpga_mem_test()) {
|
||||
ret = 1;
|
||||
goto out;
|
||||
}
|
||||
WATCHDOG_RESET();
|
||||
|
||||
/* restore memory */
|
||||
memcpy((void *)FPGA_RAM_START,(void *)FPGA_BUFFER, FPGA_RAM_SIZE);
|
||||
WATCHDOG_RESET();
|
||||
|
||||
out:
|
||||
/* Disable write to RAM */
|
||||
out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) & 0xEFFF);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -28,18 +28,39 @@
|
|||
*/
|
||||
|
||||
#include <post.h>
|
||||
|
||||
#include <watchdog.h>
|
||||
#include <asm/io.h>
|
||||
#include <video.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define GDC_SCRATCH_REG 0xC1FF8044
|
||||
#define GDC_VERSION_REG 0xC1FF8084
|
||||
#define GDC_RAM_START 0xC0000000
|
||||
#define GDC_RAM_END 0xC2000000
|
||||
#define GDC_SCRATCH_REG 0xC1FF8044
|
||||
#define GDC_VERSION_REG 0xC1FF8084
|
||||
#define GDC_HOST_BASE 0xC1FC0000
|
||||
#define GDC_RAM_START 0xC0000000
|
||||
#define GDC_RAM_END (GDC_HOST_BASE - 1)
|
||||
#define GDC_RAM_SIZE (GDC_RAM_END - GDC_RAM_START)
|
||||
|
||||
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC4
|
||||
|
||||
const static unsigned long pattern[] = {
|
||||
0xffffffff,
|
||||
0xaaaaaaaa,
|
||||
0xcccccccc,
|
||||
0xf0f0f0f0,
|
||||
0xff00ff00,
|
||||
0xffff0000,
|
||||
0x0000ffff,
|
||||
0x00ff00ff,
|
||||
0x0f0f0f0f,
|
||||
0x33333333,
|
||||
0x55555555,
|
||||
0x00000000
|
||||
};
|
||||
|
||||
const static unsigned long otherpattern = 0x01234567;
|
||||
|
||||
/* test write/read og a given LIME Register */
|
||||
static int gdc_test_reg_one(uint value)
|
||||
{
|
||||
int ret;
|
||||
|
|
@ -53,17 +74,229 @@ static int gdc_test_reg_one(uint value)
|
|||
read_value = in_be32((void *)GDC_SCRATCH_REG);
|
||||
if (read_value != value) {
|
||||
post_log("GDC SCRATCH test failed write %08X, read %08X\n",
|
||||
value, read_value);
|
||||
value, read_value);
|
||||
}
|
||||
|
||||
return (read_value != value);
|
||||
}
|
||||
|
||||
/* Verify GDC, get memory size */
|
||||
/* test with a given static 32 bit pattern in a given memory addressrange */
|
||||
static int gdc_post_test1(ulong *start, ulong size, ulong val)
|
||||
{
|
||||
int ret = 0;
|
||||
ulong i = 0;
|
||||
ulong *mem = start;
|
||||
ulong readback;
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
mem[i] = val;
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
readback = mem[i];
|
||||
if (readback != val) {
|
||||
post_log("GDC Memory error at %08x, "
|
||||
"wrote %08x, read %08x !\n",
|
||||
mem + i, val, readback);
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* test with dynamic 32 bit pattern in a given memory addressrange */
|
||||
static int gdc_post_test2(ulong *start, ulong size)
|
||||
{
|
||||
int ret = 0;
|
||||
ulong i = 0;
|
||||
ulong *mem = start;
|
||||
ulong readback;
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
mem[i] = 1 << (i % 32);
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
readback = mem[i];
|
||||
if (readback != 1 << (i % 32)) {
|
||||
post_log("GDC Memory error at %08x, "
|
||||
"wrote %08x, read %08x !\n",
|
||||
mem + i, 1 << (i % 32), readback);
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* test with dynamic 32 bit pattern in a given memory addressrange */
|
||||
static int gdc_post_test3(ulong *start, ulong size)
|
||||
{
|
||||
int ret = 0;
|
||||
ulong i = 0;
|
||||
ulong *mem = start;
|
||||
ulong readback;
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
mem[i] = i;
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
readback = mem[i];
|
||||
if (readback != i) {
|
||||
post_log("GDC Memory error at %08x, "
|
||||
"wrote %08x, read %08x !\n",
|
||||
mem + i, i, readback);
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* test with dynamic 32 bit pattern in a given memory addressrange */
|
||||
static int gdc_post_test4(ulong *start, ulong size)
|
||||
{
|
||||
int ret = 0;
|
||||
ulong i = 0;
|
||||
ulong *mem = start;
|
||||
ulong readback;
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
mem[i] = ~i;
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
for (i = 0; i < size / sizeof(ulong); i++) {
|
||||
readback = mem[i];
|
||||
if (readback != ~i) {
|
||||
post_log("GDC Memory error at %08x, "
|
||||
"wrote %08x, read %08x !\n",
|
||||
mem + i, ~i, readback);
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
if (i % 1024 == 0)
|
||||
WATCHDOG_RESET();
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* do some patterntests in a given addressrange */
|
||||
int gdc_mem_test(ulong *start, ulong size)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
/*
|
||||
* check addressrange and do different static and dynamic
|
||||
* pattern tests with it.
|
||||
*/
|
||||
if (((void *)start) + size <= (void *)GDC_RAM_END) {
|
||||
if (ret == 0)
|
||||
ret = gdc_post_test1(start, size, 0x00000000);
|
||||
|
||||
if (ret == 0)
|
||||
ret = gdc_post_test1(start, size, 0xffffffff);
|
||||
|
||||
if (ret == 0)
|
||||
ret = gdc_post_test1(start, size, 0x55555555);
|
||||
|
||||
if (ret == 0)
|
||||
ret = gdc_post_test1(start, size, 0xaaaaaaaa);
|
||||
|
||||
if (ret == 0)
|
||||
ret = gdc_post_test2(start, size);
|
||||
|
||||
if (ret == 0)
|
||||
ret = gdc_post_test3(start, size);
|
||||
|
||||
if (ret == 0)
|
||||
ret = gdc_post_test4(start, size);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* test function of gdc memory addresslines*/
|
||||
static int gdc_post_addrline(ulong *address, ulong *base, ulong size)
|
||||
{
|
||||
ulong *target;
|
||||
ulong *end;
|
||||
ulong readback = 0;
|
||||
ulong xor = 0;
|
||||
int ret = 0;
|
||||
|
||||
end = (ulong *)((ulong)base + size);
|
||||
|
||||
for (xor = sizeof(long); xor > 0; xor <<= 1) {
|
||||
target = (ulong *)((ulong)address ^ xor);
|
||||
if ((target >= base) && (target < end)) {
|
||||
*address = ~*target;
|
||||
readback = *target;
|
||||
}
|
||||
|
||||
if (readback == *address) {
|
||||
post_log("GDC Memory (address line) error at %08x"
|
||||
"XOR value %08x !\n",
|
||||
address, target , xor);
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int gdc_post_dataline(ulong *address)
|
||||
{
|
||||
unsigned long temp32 = 0;
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pattern); i++) {
|
||||
*address = pattern[i];
|
||||
/*
|
||||
* Put a different pattern on the data lines: otherwise they
|
||||
* may float long enough to read back what we wrote.
|
||||
*/
|
||||
*(address + 1) = otherpattern;
|
||||
temp32 = *address;
|
||||
|
||||
if (temp32 != pattern[i]){
|
||||
post_log("GDC Memory (date line) error at %08x, "
|
||||
"wrote %08x, read %08x !\n",
|
||||
address, pattern[i], temp32);
|
||||
ret = 1;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Verify GDC, get memory size, verify GDC memory */
|
||||
int gdc_post_test(int flags)
|
||||
{
|
||||
uint old_value;
|
||||
int ret = 0;
|
||||
uint old_value;
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
|
||||
post_log("\n");
|
||||
old_value = in_be32((void *)GDC_SCRATCH_REG);
|
||||
|
|
@ -84,13 +317,64 @@ int gdc_post_test(int flags)
|
|||
|
||||
old_value = in_be32((void *)GDC_VERSION_REG);
|
||||
post_log("GDC chip version %u.%u, year %04X\n",
|
||||
(old_value >> 8) & 0xFF, old_value & 0xFF,
|
||||
(old_value >> 16) & 0xFFFF);
|
||||
(old_value >> 8) & 0xFF, old_value & 0xFF,
|
||||
(old_value >> 16) & 0xFFFF);
|
||||
|
||||
old_value = get_ram_size((void *)GDC_RAM_START,
|
||||
GDC_RAM_END - GDC_RAM_START);
|
||||
0x02000000);
|
||||
|
||||
debug("GDC RAM size (ist): %d bytes\n", old_value);
|
||||
debug("GDC RAM size (soll): %d bytes\n", GDC_RAM_SIZE);
|
||||
post_log("GDC RAM size: %d bytes\n", old_value);
|
||||
|
||||
/* Test SDRAM datalines */
|
||||
if (gdc_post_dataline((ulong *)GDC_RAM_START)) {
|
||||
ret = 1;
|
||||
goto out;
|
||||
}
|
||||
WATCHDOG_RESET();
|
||||
|
||||
/* Test SDRAM adresslines */
|
||||
if (gdc_post_addrline((ulong *)GDC_RAM_START,
|
||||
(ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
|
||||
ret = 1;
|
||||
goto out;
|
||||
}
|
||||
WATCHDOG_RESET();
|
||||
if (gdc_post_addrline((ulong *)GDC_RAM_END - sizeof(long),
|
||||
(ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
|
||||
ret = 1;
|
||||
goto out;
|
||||
}
|
||||
WATCHDOG_RESET();
|
||||
|
||||
/* memory pattern test */
|
||||
debug("GDC Memory test (flags %8x:%8x)\n", flags,
|
||||
POST_SLOWTEST | POST_MANUAL);
|
||||
|
||||
if (flags & POST_MANUAL) {
|
||||
debug("Full memory test\n");
|
||||
if (gdc_mem_test((ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
|
||||
ret = 1;
|
||||
goto out;
|
||||
}
|
||||
/* load splashscreen again */
|
||||
} else {
|
||||
debug("smart memory test\n");
|
||||
for (i = 0; i < (GDC_RAM_SIZE >> 20) && ret == 0; i++) {
|
||||
if (ret == 0)
|
||||
ret = gdc_mem_test((ulong *)(GDC_RAM_START +
|
||||
(i << 20)),
|
||||
0x800);
|
||||
if (ret == 0)
|
||||
ret = gdc_mem_test((ulong *)(GDC_RAM_START +
|
||||
(i << 20) + 0xff800),
|
||||
0x800);
|
||||
}
|
||||
}
|
||||
WATCHDOG_RESET();
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
#endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC4 */
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@
|
|||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* from dspic.c */
|
||||
extern int dspic_read(ushort reg);
|
||||
extern int dspic_read(ushort reg, ushort *data);
|
||||
|
||||
#define REG_TEMPERATURE 0x12BC
|
||||
#define REG_VOLTAGE_5V 0x12CA
|
||||
|
|
@ -76,31 +76,38 @@ extern int dspic_read(ushort reg);
|
|||
typedef struct sysmon_s sysmon_t;
|
||||
typedef struct sysmon_table_s sysmon_table_t;
|
||||
|
||||
static void sysmon_dspic_init (sysmon_t * this);
|
||||
static int sysmon_dspic_read (sysmon_t * this, uint addr);
|
||||
static void sysmon_backlight_disable (sysmon_table_t * this);
|
||||
static void sysmon_dspic_init(sysmon_t *this);
|
||||
static int sysmon_dspic_read(sysmon_t *this, uint addr, int *val);
|
||||
static int sysmon_dspic_read_sgn(sysmon_t *this, uint addr, int *val);
|
||||
static void sysmon_backlight_disable(sysmon_table_t *this);
|
||||
|
||||
struct sysmon_s
|
||||
{
|
||||
struct sysmon_s {
|
||||
uchar chip;
|
||||
void (*init)(sysmon_t *);
|
||||
int (*read)(sysmon_t *, uint);
|
||||
int (*read)(sysmon_t *, uint, int *);
|
||||
};
|
||||
|
||||
static sysmon_t sysmon_dspic =
|
||||
{CONFIG_SYS_I2C_DSPIC_IO_ADDR, sysmon_dspic_init, sysmon_dspic_read};
|
||||
static sysmon_t sysmon_dspic = {
|
||||
CONFIG_SYS_I2C_DSPIC_IO_ADDR,
|
||||
sysmon_dspic_init,
|
||||
sysmon_dspic_read
|
||||
};
|
||||
|
||||
static sysmon_t * sysmon_list[] =
|
||||
{
|
||||
static sysmon_t sysmon_dspic_sgn = {
|
||||
CONFIG_SYS_I2C_DSPIC_IO_ADDR,
|
||||
sysmon_dspic_init,
|
||||
sysmon_dspic_read_sgn
|
||||
};
|
||||
|
||||
static sysmon_t *sysmon_list[] = {
|
||||
&sysmon_dspic,
|
||||
NULL
|
||||
};
|
||||
|
||||
struct sysmon_table_s
|
||||
{
|
||||
char * name;
|
||||
char * unit_name;
|
||||
sysmon_t * sysmon;
|
||||
struct sysmon_table_s {
|
||||
char *name;
|
||||
char *unit_name;
|
||||
sysmon_t *sysmon;
|
||||
void (*exec_before)(sysmon_table_t *);
|
||||
void (*exec_after)(sysmon_table_t *);
|
||||
|
||||
|
|
@ -118,37 +125,43 @@ struct sysmon_table_s
|
|||
uint addr;
|
||||
};
|
||||
|
||||
static sysmon_table_t sysmon_table[] =
|
||||
{
|
||||
static sysmon_table_t sysmon_table[] = {
|
||||
{
|
||||
"Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable,
|
||||
1, 1, -32768, 32767, 0xFFFF,
|
||||
0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0,
|
||||
0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0,
|
||||
REG_TEMPERATURE,
|
||||
"Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable,
|
||||
1, 1, -32768, 32767, 0xFFFF,
|
||||
0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0,
|
||||
0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0,
|
||||
REG_TEMPERATURE,
|
||||
},
|
||||
|
||||
{
|
||||
"+ 5 V", "V", &sysmon_dspic, NULL, NULL,
|
||||
100, 1000, -0x8000, 0x7FFF, 0xFFFF,
|
||||
0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
|
||||
0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
|
||||
REG_VOLTAGE_5V,
|
||||
"+ 5 V", "V", &sysmon_dspic, NULL, NULL,
|
||||
100, 1000, -0x8000, 0x7FFF, 0xFFFF,
|
||||
0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
|
||||
0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
|
||||
REG_VOLTAGE_5V,
|
||||
},
|
||||
|
||||
{
|
||||
"+ 5 V standby", "V", &sysmon_dspic, NULL, NULL,
|
||||
100, 1000, -0x8000, 0x7FFF, 0xFFFF,
|
||||
0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
|
||||
0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
|
||||
REG_VOLTAGE_5V_STANDBY,
|
||||
"+ 5 V standby", "V", &sysmon_dspic, NULL, NULL,
|
||||
100, 1000, -0x8000, 0x7FFF, 0xFFFF,
|
||||
0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
|
||||
0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
|
||||
REG_VOLTAGE_5V_STANDBY,
|
||||
},
|
||||
|
||||
{
|
||||
"Temperature", "°C", &sysmon_dspic_sgn, NULL, sysmon_backlight_disable,
|
||||
1, 1, -32768, 32767, 0xFFFF,
|
||||
0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0,
|
||||
0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0,
|
||||
REG_TEMPERATURE,
|
||||
},
|
||||
};
|
||||
static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]);
|
||||
|
||||
int sysmon_init_f (void)
|
||||
int sysmon_init_f(void)
|
||||
{
|
||||
sysmon_t ** l;
|
||||
sysmon_t **l;
|
||||
|
||||
for (l = sysmon_list; *l; l++)
|
||||
(*l)->init(*l);
|
||||
|
|
@ -156,12 +169,12 @@ int sysmon_init_f (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void sysmon_reloc (void)
|
||||
void sysmon_reloc(void)
|
||||
{
|
||||
/* Do nothing for now, sysmon_reloc() is required by the sysmon post */
|
||||
}
|
||||
|
||||
static char *sysmon_unit_value (sysmon_table_t *s, uint val)
|
||||
static char *sysmon_unit_value(sysmon_table_t *s, uint val)
|
||||
{
|
||||
static char buf[32];
|
||||
char *p, sign;
|
||||
|
|
@ -176,14 +189,13 @@ static char *sysmon_unit_value (sysmon_table_t *s, uint val)
|
|||
if (unit_val < 0) {
|
||||
sign = '-';
|
||||
unit_val = -unit_val;
|
||||
} else
|
||||
} else {
|
||||
sign = '+';
|
||||
}
|
||||
|
||||
p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div);
|
||||
|
||||
|
||||
frac = unit_val % s->unit_div;
|
||||
|
||||
frac /= (s->unit_div / s->unit_precision);
|
||||
|
||||
decimal = s->unit_precision;
|
||||
|
|
@ -197,58 +209,84 @@ static char *sysmon_unit_value (sysmon_table_t *s, uint val)
|
|||
return buf;
|
||||
}
|
||||
|
||||
static void sysmon_dspic_init (sysmon_t * this)
|
||||
static void sysmon_dspic_init(sysmon_t *this)
|
||||
{
|
||||
}
|
||||
|
||||
static int sysmon_dspic_read (sysmon_t * this, uint addr)
|
||||
static int sysmon_dspic_read(sysmon_t *this, uint addr, int *val)
|
||||
{
|
||||
int res = dspic_read(addr);
|
||||
ushort data;
|
||||
|
||||
/* To fit into the table range we should add 0x8000 */
|
||||
return (res == -1) ? -1 : (res + 0x8000);
|
||||
if (dspic_read(addr, &data) == 0){
|
||||
/* To fit into the table range we should add 0x8000 */
|
||||
*val = data + 0x8000;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static void sysmon_backlight_disable (sysmon_table_t * this)
|
||||
static int sysmon_dspic_read_sgn(sysmon_t *this, uint addr, int *val)
|
||||
{
|
||||
ushort data;
|
||||
|
||||
if (dspic_read(addr, &data) == 0){
|
||||
/* To fit into the table range we should add 0x8000 */
|
||||
*val = (signed short)data + 0x8000;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static void sysmon_backlight_disable(sysmon_table_t *this)
|
||||
{
|
||||
#if defined(CONFIG_VIDEO)
|
||||
board_backlight_switch(this->val_valid_alt);
|
||||
#endif
|
||||
}
|
||||
|
||||
int sysmon_post_test (int flags)
|
||||
int sysmon_post_test(int flags)
|
||||
{
|
||||
int res = 0;
|
||||
sysmon_table_t * t;
|
||||
int val;
|
||||
|
||||
for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) {
|
||||
for (t = sysmon_table; t < sysmon_table + ARRAY_SIZE(sysmon_table); t++) {
|
||||
t->val_valid = 1;
|
||||
if (t->exec_before)
|
||||
t->exec_before(t);
|
||||
|
||||
val = t->sysmon->read(t->sysmon, t->addr);
|
||||
if (val != -1) {
|
||||
t->val_valid = val >= t->val_min && val <= t->val_max;
|
||||
t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt;
|
||||
} else {
|
||||
if (t->sysmon->read(t->sysmon, t->addr, &val) != 0) {
|
||||
t->val_valid = 0;
|
||||
t->val_valid_alt = 0;
|
||||
post_log(": read failed\n");
|
||||
res = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
if (t->val_valid != 0) {
|
||||
t->val_valid = val >= t->val_min && val <= t->val_max;
|
||||
t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt;
|
||||
}
|
||||
|
||||
if (t->exec_after)
|
||||
t->exec_after(t);
|
||||
|
||||
if ((!t->val_valid) || (flags & POST_MANUAL)) {
|
||||
printf("%-17s = %-10s ", t->name, sysmon_unit_value(t, val));
|
||||
printf("allowed range");
|
||||
printf(" %-8s ..", sysmon_unit_value(t, t->val_min));
|
||||
printf(" %-8s", sysmon_unit_value(t, t->val_max));
|
||||
printf(" %s\n", t->val_valid ? "OK" : "FAIL");
|
||||
if ((!t->val_valid) || (flags)) {
|
||||
post_log("\n\t%-17s = %-10s ", t->name, sysmon_unit_value(t, val));
|
||||
post_log("allowed range");
|
||||
post_log(" %-8s ..", sysmon_unit_value(t, t->val_min));
|
||||
post_log(" %-8s", sysmon_unit_value(t, t->val_max));
|
||||
post_log(" %s", t->val_valid ? "OK" : "FAIL");
|
||||
}
|
||||
|
||||
if (!t->val_valid)
|
||||
if (!t->val_valid) {
|
||||
res = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
post_log("\n");
|
||||
|
||||
return res;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -57,8 +57,11 @@ int sysmon1_post_test(int flags)
|
|||
* 3.1. GPIO62 is low
|
||||
* Assuming system voltage failure.
|
||||
*/
|
||||
post_log("Abnormal voltage detected (GPIO62)\n");
|
||||
post_log("sysmon1 Abnormal voltage detected (GPIO62)\n");
|
||||
post_log("POST sysmon1 FAILED\n");
|
||||
return 1;
|
||||
} else {
|
||||
post_log("sysmon1 PASSED\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -117,10 +120,16 @@ int lwmon5_watchdog_post_test(int flags)
|
|||
ulong time;
|
||||
/* 3.3.1. So, the test succeed, save measured time to syslog. */
|
||||
time = in_be32((void *)CONFIG_SYS_WATCHDOG_TIME_ADDR);
|
||||
post_log("hw watchdog time : %u ms, passed ", time);
|
||||
/* 3.3.2. Set scratch register 1 to 0x0000xxxx */
|
||||
watchdog_magic_write(0);
|
||||
return 0;
|
||||
if (time > 90 ) { /* ms*/
|
||||
post_log("hw watchdog time : %u ms, passed ", time);
|
||||
/* 3.3.2. Set scratch register 1 to 0x0000xxxx */
|
||||
watchdog_magic_write(0);
|
||||
return 0;
|
||||
} else {
|
||||
/*test minimum watchdogtime */
|
||||
post_log("hw watchdog time : %u ms, failed ", time);
|
||||
return 2;
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue