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Merge with /home/wd/git/u-boot/master

This commit is contained in:
Wolfgang Denk 2006-06-26 10:02:52 +02:00
parent 386eda0224 f73e73ba0e
commit f0e3d2b422
55 changed files with 3987 additions and 668 deletions
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83
CHANGELOG
View File

@ -16,6 +16,89 @@ Changes since U-Boot 1.1.4:
by default with the Adder87x U-Boot port.
Patch by Bryan O'Donoghue <bodonoghue@codehermit.ie>, 29 May 2006
* VoiceBlue update: use new MTD flash partitioning methods, use more
reasonable TEXT_BASE, update default environment and enable keyed
autoboot.
Patch by Ladislav Michl, 16. Aug 2005
* Add forgotten changes for the PLEB 2 Board.
Patch by David Snowdon, 13. Aug 2005
* Add support for wrPPMC7xx/74xx boards
Patch by Richard Danter, 12 Aug 2005
* Add support for gth2 board
Patch by Thomas Lange, Aug 11 2005
* Add support for CONFIG_SERIAL_MULTI on MPC5xxx
Patch by Martin Krause, 8 Jun 2006
This patch supports two serial consoles on boards with
a MPC5xxx CPU. The console can be switched at runtime
by setting stdin, stdout and stderr to the desired serial
interface (serial0 or serial1). The PSCs to be used as
console port are definded by CONFIG_PSC_CONSOLE
and CONFIG_PSC_CONSOLE2.
See README.serial_multi for details.
* Bugfix in I2C initialisation on S3C2400.
If the bus is blocked because of a previously interrupted
transfer, up to eleven clocks are generated on the I2CSCL
line to complete the transfer and to free the bus.
With this fix pin I2CSCL (PG6) is really configured as GPIO
so the clock pulses are really generated.
Patch by Martin Krause, 04 Apr 2006
* Fix DDR6 errata on TQM834x boards
Patch by Thomas Waehner, 07 Mar 2006
* Remove obsolete flash driver board/tqm5200/flash.c
Patch by Martin Krause, 11 Jan 2006
* Update configuration for CMC-PU2 board
Patch by Martin Krause, 17 Nov 2005
* Add support for PS/2 keyboard on TQM85xx board
Patch by Martin Krause, 07 Nov 2005
Tested on a STK85XX baseboard. Make sure the PS/2 controller
has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3
* Fix TRAB channel switching delay for trab_fkt.bin standalone applikation
In tsc2000_read_channel() the delay after setting the multiplexer
to a temperature channel is increased from 1,5 ms to 10 ms. This
is to allow the multiplexer inputs to stabilize after huge steps
of the input signal level.
Patch by Martin Krause, 08 Nov 2005
* Adjust TQM5200 make targets
Make the automatic CS configuration the default.
The dedicated configurations CONFIG_TQM5200_AA, CONFIG_TQM5200_AB
and CONFIG_TQM5200_AC are removed.
"TQM5200_config" is now the default for STK52XX.200 base boards.
On a STK52XX.100 base board "TQM5200_STK100_config" must be used.
Patch by Martin Krause, 07 Nov 2005
* Fix setting of environment variable "ver" on trab board
The environment variable "ver" is now set before
do_auto_update() is called, so that "ver" can be used
in USB update scripts.
Patch by Martin Krause, 27 Oct 2005
* Fix wrong usage of udelay() in led_blink() on trab board
Patch by Martin Krause, 27 Oct 2005
* Fix udelay bug in vfd.c for trab board
Patch by Martin Krause, 27 Oct 2005
* Disable JFFS2 support for trab board
Patch by Martin Krause, 27 Oct 2005
* Change mtdparts definition on trab board to match current flash map
Patch by Martin Krause, 27 Oct 2005
* Fix memory init problems on MCC200 board
* Fix IxEthDB.h to compile again
Patch by Stefan Roese, 14 Jun 2006

6
CREDITS
View File

@ -105,6 +105,10 @@ N: Magnus Damm
E: damm@opensource.se
D: 8xxrom
N: Richard Danter
E: richard.danter@windriver.com
D: Support for Wind River PPMC 7xx/74xx boards
N: George G. Davis
E: gdavis@mvista.com
D: Board ports for ADS GraphicsClient+ and Intel Assabet
@ -253,7 +257,7 @@ D Support for Intrinsyc CERF PXA250 board.
N: Thomas Lange
E: thomas@corelatus.se
D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
D: Support for GTH, GTH2 and dbau1x00 boards; lots of PCMCIA fixes
N: Marc Leeman
E: marc.leeman@barco.com

1
MAINTAINERS
View File

@ -489,6 +489,7 @@ Wolfgang Denk <wd@denx.de>
Thomas Lange <thomas@corelatus.se>
dbau1x00 MIPS32 Au1000
gth2 MIPS32 Au1000
#########################################################################
# Nios-32 Systems: #

12
MAKEALL
View File

@ -28,7 +28,7 @@ LIST_5xxx=" \
BC3450 cpci5200 EVAL5200 icecube_5100 \
icecube_5200 lite5200b mcc200 o2dnt \
pf5200 PM520 Total5100 Total5200 \
Total5200_Rev2 TQM5200_auto \
Total5200_Rev2 TQM5200 \
"
#########################################################################
@ -142,7 +142,7 @@ LIST_74xx=" \
"
LIST_7xx=" \
BAB7xx CPCI750 ELPPC \
BAB7xx CPCI750 ELPPC ppmc7xx \
"
LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
@ -204,9 +204,9 @@ LIST_ARM11=" \
LIST_pxa=" \
adsvix cerf250 cradle csb226 \
delta innokom lubbock pxa255_idp \
wepep250 xaeniax xm250 xsengine \
zylonite \
delta innokom lubbock pleb2 \
pxa255_idp wepep250 xaeniax xm250 \
xsengine zylonite \
"
LIST_ixp="ixdp425 ixdpg425 pdnb3"
@ -226,7 +226,7 @@ LIST_mips4kc="incaip"
LIST_mips5kc="purple"
LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el"
LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el gth2"
LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"

44
Makefile
View File

@ -356,8 +356,8 @@ smmaco4_config: unconfig
@./mkconfig -a smmaco4 ppc mpc5xxx tqm5200
spieval_config: unconfig
echo "#define CONFIG_CS_AUTOCONF">>include/config.h
echo "... with automatic CS configuration"
@echo "#define CONFIG_CS_AUTOCONF">>include/config.h
@echo "... with automatic CS configuration"
@./mkconfig -a spieval ppc mpc5xxx tqm5200
MINI5200_config \
@ -394,35 +394,20 @@ Total5200_Rev2_lowboot_config: unconfig
}
@./mkconfig -a Total5200 ppc mpc5xxx total5200
TQM5200_auto_config \
TQM5200_AA_config \
TQM5200_AB_config \
TQM5200_AC_config \
TQM5200_config \
TQM5200_STK100_config \
MiniFAP_config: unconfig
@ >include/config.h
@[ -z "$(findstring MiniFAP,$@)" ] || \
{ echo "#define CONFIG_MINIFAP" >>include/config.h ; \
echo "#define CONFIG_TQM5200_AC" >>include/config.h ; \
echo "... TQM5200_AC on MiniFAP" ; \
}
@[ -z "$(findstring AA,$@)" ] || \
{ echo "#define CONFIG_TQM5200_AA" >>include/config.h ; \
echo "... with 4 MB Flash, 16 MB SDRAM, 32 kB EEPROM" ; \
}
@[ -z "$(findstring AB,$@)" ] || \
{ echo "#define CONFIG_TQM5200_AB" >>include/config.h ; \
echo "... with 64 MB Flash, 64 MB SDRAM, 32 kB EEPROM, 512 kB SRAM" ; \
echo "... with Graphics Controller"; \
}
@[ -z "$(findstring AC,$@)" ] || \
{ echo "#define CONFIG_TQM5200_AC" >>include/config.h ; \
echo "... with 4 MB Flash, 128 MB SDRAM" ; \
echo "... with Graphics Controller"; \
}
@[ -z "$(findstring auto,$@)" ] || \
{ echo "#define CONFIG_CS_AUTOCONF" >>include/config.h ; \
echo "... with automatic CS configuration" ; \
@[ -z "$(findstring STK100,$@)" ] || \
{ echo "#define CONFIG_STK52XX_REV100" >>include/config.h ; \
echo "... on a STK52XX.100 base board" ; \
}
@echo "#define CONFIG_CS_AUTOCONF">>include/config.h ;
@echo "... with automatic CS configuration" ;
@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
#########################################################################
@ -1470,6 +1455,9 @@ PCIPPC6_config: unconfig
ZUMA_config: unconfig
@./mkconfig $(@:_config=) ppc 74xx_7xx evb64260
ppmc7xx_config: unconfig
@./mkconfig $(@:_config=) ppc 74xx_7xx ppmc7xx
#========================================================================
# ARM
#========================================================================
@ -1670,6 +1658,11 @@ cm4008_config : unconfig
cm41xx_config : unconfig
@./mkconfig $(@:_config=) arm arm920t cm41xx NULL ks8695
gth2_config : unconfig
@ >include/config.h
@echo "#define CONFIG_GTH2 1" >>include/config.h
@./mkconfig -a gth2 mips mips gth2
#########################################################################
## S3C44B0 Systems
#########################################################################
@ -1727,6 +1720,9 @@ ixdpg425_config : unconfig
lubbock_config : unconfig
@./mkconfig $(@:_config=) arm pxa lubbock
pleb2_config : unconfig
@./mkconfig $(@:_config=) arm pxa pleb2
logodl_config : unconfig
@./mkconfig $(@:_config=) arm pxa logodl

5
README
View File

@ -310,8 +310,9 @@ The following options need to be configured:
CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400,
CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4,
CONFIG_SHANNON, CONFIG_P2_OMAP730, CONFIG_SMDK2400,
CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9
CONFIG_PLEB2, CONFIG_SHANNON, CONFIG_P2_OMAP730,
CONFIG_SMDK2400, CONFIG_SMDK2410, CONFIG_TRAB,
CONFIG_VCMA9
MicroBlaze based boards:
------------------------

41
board/gth2/Makefile Normal file
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@ -0,0 +1,41 @@
#
# (C) Copyright 2005
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o ee_access.o
SOBJS = lowlevel_init.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

42
board/gth2/config.mk Normal file
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@ -0,0 +1,42 @@
#
# (C) Copyright 2004-2005
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMD Alchemy AU1000, MIPS32 core
#
ifeq ($(TBASE),0)
TEXT_BASE = 0
else
ifeq ($(TBASE),1)
TEXT_BASE = 0xbfc10070
else
ifeq ($(TBASE),2)
TEXT_BASE = 0xbfc30070
else
## Only to make ordinary make work
TEXT_BASE = 0x90000000
endif
endif
endif

347
board/gth2/ee_access.c Normal file
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@ -0,0 +1,347 @@
/* Module for handling DALLAS DS2438, smart battery monitor
Chip can store up to 40 bytes of user data in EEPROM,
perform temp, voltage and current measurements.
Chip also contains a unique serial number.
Always read/write LSb first
For documentaion, see data sheet for DS2438, 2438.pdf
By Thomas.Lange@corelatus.com 001025
Copyright (C) 2000-2005 Corelatus AB */
/* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/au1x00.h>
#include <asm/io.h>
#include "ee_dev.h"
#include "ee_access.h"
/* static int Debug = 1; */
#undef E_DEBUG
#define E_DEBUG(fmt,args...) /* */
/* #define E_DEBUG(fmt,args...) printk("EEA:"fmt,##args); */
/* We dont have kernel functions */
#define printk printf
#define KERN_DEBUG
#define KERN_ERR
#define EIO 1
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
/* lookup table ripped from DS app note 17, understanding and using cyclic redundancy checks... */
static u8 crc_lookup[256] = {
0, 94, 188, 226, 97, 63, 221, 131,
194, 156, 126, 32, 163, 253, 31, 65,
157, 195, 33, 127, 252, 162, 64, 30,
95, 1, 227, 189, 62, 96, 130, 220,
35, 125, 159, 193, 66, 28, 254, 160,
225, 191, 93, 3, 128, 222, 60, 98,
190, 224, 2, 92, 223, 129, 99, 61,
124, 34, 192, 158, 29, 67, 161, 255,
70, 24, 250, 164, 39, 121, 155, 197,
132, 218, 56, 102, 229, 187, 89, 7,
219, 133, 103, 57, 186, 228, 6, 88,
25, 71, 165, 251, 120, 38, 196, 154,
101, 59, 217, 135, 4, 90, 184, 230,
167, 249, 27, 69, 198, 152, 122, 36,
248, 166, 68, 26, 153, 199, 37, 123,
58, 100, 134, 216, 91, 5, 231, 185,
140, 210, 48, 110, 237, 179, 81, 15,
78, 16, 242, 172, 47, 113, 147, 205,
17, 79, 173, 243, 112, 46, 204, 146,
211, 141, 111, 49, 178, 236, 14, 80,
175, 241, 19, 77, 206, 144, 114, 44,
109, 51, 209, 143, 12, 82, 176, 238,
50, 108, 142, 208, 83, 13, 239, 177,
240, 174, 76, 18, 145, 207, 45, 115,
202, 148, 118, 40, 171, 245, 23, 73,
8, 86, 180, 234, 105, 55, 213, 139,
87, 9, 235, 181, 54, 104, 138, 212,
149, 203, 41, 119, 244, 170, 72, 22,
233, 183, 85, 11, 136, 214, 52, 106,
43, 117, 151, 201, 74, 20, 246, 168,
116, 42, 200, 150, 21, 75, 169, 247,
182, 232, 10, 84, 215, 137, 107, 53
};
static void
write_gpio_data(int value ){
if(value){
/* Tristate */
gpio_tristate(GPIO_EEDQ);
}
else{
/* Drive 0 */
gpio_clear(GPIO_EEDQ);
}
}
static u8 make_new_crc( u8 Old_crc, u8 New_value ){
/* Compute a new checksum with new byte, using previous checksum as input
See DS app note 17, understanding and using cyclic redundancy checks...
Also see DS2438, page 11 */
return( crc_lookup[Old_crc ^ New_value ]);
}
int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
/* Check if the checksum for this buffer is correct */
u8 Curr_crc=0;
int i;
u8 *Curr_byte = Buffer;
for(i=0;i<Len;i++){
Curr_crc = make_new_crc( Curr_crc, *Curr_byte);
Curr_byte++;
}
E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
if(Curr_crc == Crc){
/* Good */
return(TRUE);
}
printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
return(FALSE);
}
static void
set_idle(void){
/* Send idle and keep start time
Continous 1 is idle */
WRITE_PORT(1);
}
static int
do_cpu_reset(void){
/* Release reset and verify that chip responds with presence pulse */
int Retries=0;
while(Retries<15){
udelay(RESET_LOW_TIME);
/* Send reset */
WRITE_PORT(0);
udelay(RESET_LOW_TIME);
/* Release reset */
WRITE_PORT(1);
/* Wait for EEPROM to drive output */
udelay(PRESENCE_TIMEOUT);
if(!READ_PORT){
/* Ok, EEPROM is driving a 0 */
E_DEBUG("Presence detected\n");
if(Retries){
E_DEBUG("Retries %d\n",Retries);
}
/* Make sure chip releases pin */
udelay(PRESENCE_LOW_TIME);
return 0;
}
Retries++;
}
printk(KERN_ERR"eeprom did not respond when releasing reset\n");
/* Make sure chip releases pin */
udelay(PRESENCE_LOW_TIME);
/* Set to idle again */
set_idle();
return(-EIO);
}
static u8
read_cpu_byte(void){
/* Read a single byte from EEPROM
Read LSb first */
int i;
int Value;
u8 Result=0;
u32 Flags;
E_DEBUG("Reading byte\n");
for(i=0;i<8;i++){
/* Small delay between pulses */
udelay(1);
#ifdef __KERNEL__
/* Disable irq */
save_flags(Flags);
cli();
#endif
/* Pull down pin short time to start read
See page 26 in data sheet */
WRITE_PORT(0);
udelay(READ_LOW);
WRITE_PORT(1);
/* Wait for chip to drive pin */
udelay(READ_TIMEOUT);
Value = READ_PORT;
if(Value)
Value=1;
#ifdef __KERNEL__
/* Enable irq */
restore_flags(Flags);
#endif
/* Wait for chip to release pin */
udelay(TOTAL_READ_LOW-READ_TIMEOUT);
/* LSb first */
Result|=Value<<i;
/* E_DEBUG("Read %d\n",Value); */
}
E_DEBUG("Read byte 0x%x\n",Result);
return(Result);
}
static void
write_cpu_byte(u8 Byte){
/* Write a single byte to EEPROM
Write LSb first */
int i;
int Value;
u32 Flags;
E_DEBUG("Writing byte 0x%x\n",Byte);
for(i=0;i<8;i++){
/* Small delay between pulses */
udelay(1);
Value = Byte&1;
#ifdef __KERNEL__
/* Disable irq */
save_flags(Flags);
cli();
#endif
/* Pull down pin short time for a 1, long time for a 0
See page 26 in data sheet */
WRITE_PORT(0);
if(Value){
/* Write a 1 */
udelay(WRITE_1_LOW);
}
else{
/* Write a 0 */
udelay(WRITE_0_LOW);
}
WRITE_PORT(1);
#ifdef __KERNEL__
/* Enable irq */
restore_flags(Flags);
#endif
if(Value)
/* Wait for chip to read the 1 */
udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
/* E_DEBUG("Wrote %d\n",Value); */
Byte>>=1;
}
}
int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
/* Execute this command string, including
giving reset and setting to idle after command
if Rx_len is set, we read out data from EEPROM */
int i;
E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
if(do_cpu_reset()){
/* Failed! */
return(-EIO);
}
if(Send_skip)
/* Always send SKIP_ROM first to tell chip we are sending a command,
except when we read out rom data for chip */
write_cpu_byte(SKIP_ROM);
/* Always have Tx data */
for(i=0;i<Tx_len;i++){
write_cpu_byte(Tx[i]);
}
if(Rx_len){
for(i=0;i<Rx_len;i++){
Rx[i]=read_cpu_byte();
}
}
set_idle();
E_DEBUG("Command done\n");
return(0);
}
int ee_init_cpu_data(void){
int i;
u8 Tx[10];
/* Leave it floting since altera is driving the same pin */
set_idle();
/* Copy all User EEPROM data to scratchpad */
for(i=0;i<USER_PAGES;i++){
Tx[0]=RECALL_MEMORY;
Tx[1]=EE_USER_PAGE_0+i;
if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
}
/* Make sure chip doesnt store measurements in NVRAM */
Tx[0]=WRITE_SCRATCHPAD;
Tx[1]=0; /* Page */
Tx[2]=9;
if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO);
Tx[0]=COPY_SCRATCHPAD;
if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
for(i=0;i<10;i++){
udelay(1000);
}
return(0);
}

30
board/gth2/ee_access.h Normal file
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@ -0,0 +1,30 @@
/* By Thomas.Lange@Corelatus.com 001025 */
/* Definitions for EEPROM/VOLT METER DS2438 */
/* Copyright (C) 2000-2005 Corelatus AB */
#ifndef INCeeaccessh
#define INCeeaccessh
#include <asm/types.h>
#include "ee_dev.h"
int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip );
int ee_init_cpu_data(void);
int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
/* Defs for altera reg */
#define EE_WRITE_SHIFT 8 /* bits to shift left */
#define EE_READ_SHIFT 16 /* bits to shift left */
#define EE_DONE 0x80000000
#define EE_BUSY 0x40000000
#define EE_ERROR 0x20000000
/* Commands */
#define EE_CMD_NOP 0
#define EE_CMD_INIT_RES 1
#define EE_CMD_WR_BYTE 2
#define EE_CMD_RD_BYTE 3
#endif /* INCeeaccessh */

96
board/gth2/ee_dev.h Normal file
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@ -0,0 +1,96 @@
/* By Thomas.Lange@Corelatus.com 001025 */
/* Definitions for EEPROM/VOLT METER DS2438 */
/* Copyright (C) 2000-2005 Corelatus AB */
/* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef INCeedevh
#define INCeedevh
#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
/* MIPS */
#define WRITE_PORT(Value) write_gpio_data(Value)
#define READ_PORT (gpio_read()&GPIO_EEDQ)
/* 64 bytes chip */
#define EE_CHIP_SIZE 64
/* Board with new current resistor */
#define EE_GTH_0304 1
/* new dsp and 64 MB SDRAM */
#define EE_DSP_64 0x10
/* microsecs */
/* Pull line down at least this long for reset pulse */
#define RESET_LOW_TIME 490
/* Read presence pulse after we release reset pulse */
#define PRESENCE_TIMEOUT 100
#define PRESENCE_LOW_TIME 200
#define WRITE_0_LOW 60
#define WRITE_1_LOW 1
#define TOTAL_WRITE_LOW 60
#define READ_LOW 1
#define READ_TIMEOUT 10
#define TOTAL_READ_LOW 70
/* Rom function commands */
#define READ_ROM 0x33
#define MATCH_ROM 0x55
#define SKIP_ROM 0xCC
#define SEARCH_ROM 0xF0
/* Memory_command_function */
#define WRITE_SCRATCHPAD 0x4E
#define READ_SCRATCHPAD 0xBE
#define COPY_SCRATCHPAD 0x48
#define RECALL_MEMORY 0xB8
#define CONVERT_TEMP 0x44
#define CONVERT_VOLTAGE 0xB4
/* Chip is divided in 8 pages, 8 bytes each */
#define EE_PAGE_SIZE 8
/* All chip data we want are in page 0 */
/* Bytes in page 0 */
#define EE_P0_STATUS 0
#define EE_P0_TEMP_LSB 1
#define EE_P0_TEMP_MSB 2
#define EE_P0_VOLT_LSB 3
#define EE_P0_VOLT_MSB 4
#define EE_P0_CURRENT_LSB 5
#define EE_P0_CURRENT_MSB 6
/* 40 byte user data is located at page 3-7 */
#define EE_USER_PAGE_0 3
#define USER_PAGES 5
/* Layout of gth user pages usage */
/* Bytes 0-16 ethernet addr in ascii ( len 17 ) */
#define EE_ETHERNET_OFFSET 0
#endif /* INCeedevh */

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/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* flash_init()
*
* sets up flash_info and returns size of FLASH (bytes)
*/
unsigned long flash_init (void)
{
printf ("Skipping flash_init\n");
return (0);
}
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
printf ("write_buff not implemented\n");
return (-1);
}

435
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/*
* (C) Copyright 2005
* Thomas.Lange@corelatus.se
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/au1x00.h>
#include <asm/addrspace.h>
#include <asm/mipsregs.h>
#include <watchdog.h>
#include "ee_access.h"
static int wdi_status = 0;
unsigned long mips_io_port_base = 0;
#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096))
void inline log_serial_char(char c){
char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
int serial_log_offset;
u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
serial_log_offset = *serial_log_offsetp;
*(serial_log_buffer + serial_log_offset) = c;
serial_log_offset++;
if(serial_log_offset >= 4096){
serial_log_offset = 4;
}
*serial_log_offsetp = serial_log_offset;
}
void init_log_serial(void){
char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
/* Copy buffer from last run */
memcpy(serial_log_buffer + 4096,
serial_log_buffer,
4096);
memset(serial_log_buffer, 0, 4096);
*serial_log_offsetp = 4;
}
void hw_watchdog_reset(void){
volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
volatile u32 *sys_outputclear = (volatile u32*)SYS_OUTPUTCLR;
if(wdi_status){
*sys_outputset = GPIO_CPU_LED|GPIO_WDI;
wdi_status = 0;
}
else{
*sys_outputclear = GPIO_CPU_LED|GPIO_WDI;
wdi_status = 1;
}
}
long int initdram(int board_type)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */
WATCHDOG_RESET();
return (SDRAM_SIZE);
}
/* In cpu/mips/cpu.c */
void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
void set_ledcard(u32 value){
/* Clock 24 bits to led card */
int i;
volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
/* Start with known values */
*sys_outputclr = GPIO_LEDCLK|GPIO_LEDD;
for(i=0;i<24;i++){
if(value&0x00800000){
*sys_outputset = GPIO_LEDD;
}
else{
*sys_outputclr = GPIO_LEDD;
}
udelay(1);
*sys_outputset = GPIO_LEDCLK;
udelay(1);
*sys_outputclr = GPIO_LEDCLK;
udelay(1);
value<<=1;
}
/* Data is enable output */
*sys_outputset = GPIO_LEDD;
}
int checkboard (void)
{
volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
u32 proc_id;
WATCHDOG_RESET();
*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
proc_id = read_32bit_cp0_register(CP0_PRID);
switch (proc_id >> 24) {
case 0:
puts ("Board: GTH2\n");
printf ("CPU: Au1000 500 MHz, id: 0x%02x, rev: 0x%02x\n",
(proc_id >> 8) & 0xFF, proc_id & 0xFF);
break;
default:
printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
}
#ifdef CONFIG_IDE_PCMCIA
/* PCMCIA is on a 36 bit physical address.
We need to map it into a 32 bit addresses */
write_one_tlb(20, /* index */
0x01ffe000, /* Pagemask, 16 MB pages */
CFG_PCMCIA_IO_BASE, /* Hi */
0x3C000017, /* Lo0 */
0x3C200017); /* Lo1 */
write_one_tlb(21, /* index */
0x01ffe000, /* Pagemask, 16 MB pages */
CFG_PCMCIA_ATTR_BASE, /* Hi */
0x3D000017, /* Lo0 */
0x3D200017); /* Lo1 */
write_one_tlb(22, /* index */
0x01ffe000, /* Pagemask, 16 MB pages */
CFG_PCMCIA_MEM_ADDR, /* Hi */
0x3E000017, /* Lo0 */
0x3E200017); /* Lo1 */
#endif /* CONFIG_IDE_PCMCIA */
/* Wait for GPIO ports to become stable */
udelay(5000); /* FIXME */
/* Release reset of ethernet PHY chips */
/* Always do this, because linux does not know about it */
*sys_outputset = GPIO_ERESET;
/* Kill FPGA:s */
*sys_outputclr = GPIO_CACONFIG|GPIO_DPACONFIG;
udelay(2);
*sys_outputset = GPIO_CACONFIG|GPIO_DPACONFIG;
/* Turn front led yellow */
set_ledcard(0x00100000);
return 0;
}
#define POWER_OFFSET 0xF0000
#define SW_WATCHDOG_REASON 13
#define BOOTDATA_OFFSET 0xF8000
#define MAX_ATTEMPTS 5
#define FAILSAFE_BOOT 1
#define SYSTEM_BOOT 2
#define SYSTEM2_BOOT 3
#define WRITE_FLASH16(a, d) \
do \
{ \
*((volatile u16 *) (a)) = (d);\
} while(0)
static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
{
u16 data;
volatile u16 *flash = (u16 *) (CFG_FLASH_BASE);
switch(System){
case FAILSAFE_BOOT:
printf ("Setting failsafe boot in flash\n");
break;
case SYSTEM_BOOT:
printf ("Setting system boot in flash\n");
break;
case SYSTEM2_BOOT:
printf ("Setting system2 boot in flash\n");
break;
default:
printf ("Invalid system data %u, setting failsafe\n", System);
System = FAILSAFE_BOOT;
}
if ((Count < 1) | (Count > MAX_ATTEMPTS)) {
printf ("Invalid boot count %u, setting 1\n", Count);
Count = 1;
}
printf ("Boot attempt %d\n", Count);
data = (System << 8) | Count;
/* AMD 16 bit */
WRITE_FLASH16 (&flash[0x555], 0xAAAA);
WRITE_FLASH16 (&flash[0x2AA], 0x5555);
WRITE_FLASH16 (&flash[0x555], 0xA0A0);
WRITE_FLASH16 (addr, data);
}
static int random_system(void){
/* EEPROM read failed. Just try to choose one
system release and hope it works */
/* FIXME */
return(SYSTEM_BOOT);
}
static int switch_system(int old_system){
u8 Rx[10];
u8 Tx[5];
int valid_release;
if(old_system==FAILSAFE_BOOT){
/* Find out which system release to use */
/* Copy from nvram to scratchpad */
Tx[0] = RECALL_MEMORY;
Tx[1] = 7; /* Page */
if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
printf ("EE user page 7 recall failed\n");
return (random_system());
}
Tx[0] = READ_SCRATCHPAD;
if (ee_do_cpu_command (Tx, 2, Rx, 9, 1)) {
printf ("EE user page 7 read failed\n");
return (random_system());
}
/* Crc in 9:th byte */
if (!ee_crc_ok (Rx, 8, *(Rx + 8))) {
printf ("EE read failed, page 7. CRC error\n");
return (random_system());
}
valid_release = Rx[7];
if((valid_release==0xFF)|
((valid_release&1) == 0)){
return(SYSTEM_BOOT);
}
else{
return(SYSTEM2_BOOT);
}
}
else{
return(FAILSAFE_BOOT);
}
}
static void check_boot_tries (void)
{
/* Count the number of boot attemps
switch system if too many */
int i;
volatile u16 *addr;
volatile u16 data;
u8 system = FAILSAFE_BOOT;
u8 count;
addr = (u16 *) (CFG_FLASH_BASE + BOOTDATA_OFFSET);
if (*addr == 0xFFFF) {
printf ("*** No bootdata exists. ***\n");
write_bootdata (addr, FAILSAFE_BOOT, 1);
} else {
/* Search for latest written bootdata */
i = 0;
while ((*(addr + 1) != 0xFFFF) & (i < 8000)) {
addr++;
i++;
}
if (i >= 8000) {
/* Whoa, dont write any more */
printf ("*** No bootdata found. Not updating flash***\n");
} else {
/* See how many times we have tried to boot real system */
data = *addr;
system = data >> 8;
count = data & 0xFF;
if ((system != SYSTEM_BOOT) &
(system != SYSTEM2_BOOT) &
(system != FAILSAFE_BOOT)) {
printf ("*** Wrong system %d\n", system);
system = FAILSAFE_BOOT;
count = 1;
} else {
switch (count) {
case 0:
case 1:
case 2:
case 3:
case 4:
/* Try same system again if needed */
count++;
break;
case 5:
/* Switch system and reset tries */
count = 1;
system = switch_system(system);
printf ("***Too many boot attempts, switching system***\n");
break;
default:
/* Switch system, start over and hope it works */
printf ("***Unexpected data on addr 0x%x, %u***\n",
(u32) addr, data);
count = 1;
system = switch_system(system);
}
}
write_bootdata (addr + 1, system, count);
}
}
switch(system){
case FAILSAFE_BOOT:
printf ("Booting failsafe system\n");
setenv ("bootargs", "panic=1 root=/dev/hda7");
setenv ("bootcmd", "ide reset;disk 0x81000000 0:5;run addmisc;bootm");
break;
case SYSTEM_BOOT:
printf ("Using normal system\n");
setenv ("bootargs", "panic=1 root=/dev/hda4");
setenv ("bootcmd", "ide reset;disk 0x81000000 0:2;run addmisc;bootm");
break;
case SYSTEM2_BOOT:
printf ("Using normal system2\n");
setenv ("bootargs", "panic=1 root=/dev/hda9");
setenv ("bootcmd", "ide reset;disk 0x81000000 0:8;run addmisc;bootm");
break;
default:
printf ("Invalid system %d\n", system);
printf ("Hanging\n");
while(1);
}
}
int misc_init_r(void){
u8 Rx[80];
u8 Tx[5];
int page;
int read = 0;
WATCHDOG_RESET();
if (ee_init_cpu_data ()) {
printf ("EEPROM init failed\n");
return (0);
}
/* Check which release to boot */
check_boot_tries ();
/* Read the pages where ethernet address is stored */
for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) {
/* Copy from nvram to scratchpad */
Tx[0] = RECALL_MEMORY;
Tx[1] = page;
if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
printf ("EE user page %d recall failed\n", page);
return (0);
}
Tx[0] = READ_SCRATCHPAD;
if (ee_do_cpu_command (Tx, 2, Rx + read, 9, 1)) {
printf ("EE user page %d read failed\n", page);
return (0);
}
/* Crc in 9:th byte */
if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) {
printf ("EE read failed, page %d. CRC error\n", page);
return (0);
}
read += 8;
}
/* Add eos after eth addr */
Rx[17] = 0;
printf ("Ethernet addr read from eeprom: %s\n\n", Rx);
if ((Rx[2] != ':') |
(Rx[5] != ':') |
(Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
printf ("*** ethernet addr invalid, using default ***\n");
} else {
setenv ("ethaddr", Rx);
}
return (0);
}

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/* Memory sub-system initialization code */
#include <config.h>
#include <version.h>
#include <asm/regdef.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
#define CP0_Config0 $16
#define MEM_1MS ((CFG_MHZ) * 1000)
#define GPIO_RJ1LY (1<<22)
#define GPIO_CFRESET (1<<10)
.text
.set noreorder
.set mips32
.globl lowlevel_init
lowlevel_init:
/*
* Step 2) Establish Status Register
* (set BEV, clear ERL, clear EXL, clear IE)
*/
li t1, 0x00400000
mtc0 t1, CP0_STATUS
/*
* Step 3) Establish CP0 Config0
* (set OD, set K0=3)
*/
li t1, 0x00080003
mtc0 t1, CP0_CONFIG
/*
* Step 4) Disable Watchpoint facilities
*/
li t1, 0x00000000
mtc0 t1, CP0_WATCHLO
mtc0 t1, CP0_IWATCHLO
/*
* Step 5) Disable the performance counters
*/
mtc0 zero, CP0_PERFORMANCE
nop
/*
* Step 6) Establish EJTAG Debug register
*/
mtc0 zero, CP0_DEBUG
nop
/*
* Step 7) Establish Cause
* (set IV bit)
*/
li t1, 0x00800000
mtc0 t1, CP0_CAUSE
/* Establish Wired (and Random) */
mtc0 zero, CP0_WIRED
nop
/* No workaround if running from ram */
lui t0, 0xffc0
lui t3, 0xbfc0
and t1, ra, t0
bne t1, t3, noCacheJump
nop
/*** From AMD YAMON ***/
/*
* Step 8) Initialize the caches
*/
li t0, (16*1024)
li t1, 32
li t2, 0x80000000
addu t3, t0, t2
cacheloop:
cache 0, 0(t2)
cache 1, 0(t2)
addu t2, t1
bne t2, t3, cacheloop
nop
/* Save return address */
move t3, ra
/* Run from cacheable space now */
bal cachehere
nop
cachehere:
li t1, ~0x20000000 /* convert to KSEG0 */
and t0, ra, t1
addi t0, 5*4 /* 5 insns beyond cachehere */
jr t0
nop
/* Restore return address */
move ra, t3
/*
* Step 9) Initialize the TLB
*/
li t0, 0 # index value
li t1, 0x00000000 # entryhi value
li t2, 32 # 32 entries
tlbloop:
/* Probe TLB for matching EntryHi */
mtc0 t1, CP0_ENTRYHI
tlbp
nop
/* Examine Index[P], 1=no matching entry */
mfc0 t3, CP0_INDEX
li t4, 0x80000000
and t3, t4, t3
addiu t1, t1, 1 # increment t1 (asid)
beq zero, t3, tlbloop
nop
/* Initialize the TLB entry */
mtc0 t0, CP0_INDEX
mtc0 zero, CP0_ENTRYLO0
mtc0 zero, CP0_ENTRYLO1
mtc0 zero, CP0_PAGEMASK
tlbwi
/* Do it again */
addiu t0, t0, 1
bne t0, t2, tlbloop
nop
/* First setup pll:s to make serial work ok */
/* We have a 12.5 MHz crystal */
li t0, SYS_CPUPLL
li t1, 0x28 /* CPU clock, 500 MHz */
sw t1, 0(t0)
sync
nop
nop
/* wait 1mS for clocks to settle */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
/* Setup AUX PLL */
li t0, SYS_AUXPLL
li t1, 0
sw t1, 0(t0) /* aux pll */
sync
/* Static memory controller */
/* RCE0 - can not change while fetching, do so from icache */
move t2, ra /* Store return address */
bal getAddr
nop
getAddr:
move t1, ra
move ra, t2 /* Move return addess back */
cache 0x14,0(t1)
cache 0x14,32(t1)
/*** /From YAMON ***/
noCacheJump:
/* Static memory controller */
/* RCE0 AMD 29LV800 Flash */
li t0, MEM_STCFG0
li t1, 0x00000243
sw t1, 0(t0)
li t0, MEM_STTIME0
li t1, 0x040181D7 /* FIXME */
sw t1, 0(t0)
li t0, MEM_STADDR0
li t1, 0x11E03F80
sw t1, 0(t0)
/* RCE1 PCMCIA 250ns */
li t0, MEM_STCFG1
li t1, 0x00000002
sw t1, 0(t0)
li t0, MEM_STTIME1
li t1, 0x280E3E07
sw t1, 0(t0)
li t0, MEM_STADDR1
li t1, 0x10000000
sw t1, 0(t0)
/* RCE2 CP Altera */
li t0, MEM_STCFG2
li t1, 0x00000280 /* BE, EW */
sw t1, 0(t0)
li t0, MEM_STTIME2
li t1, 0x0303000c
sw t1, 0(t0)
li t0, MEM_STADDR2
li t1, 0x10c03f80 /* 1 MB */
sw t1, 0(t0)
/* RCE3 DP Altera */
li t0, MEM_STCFG3
li t1, 0x00000280 /* BE, EW */
sw t1, 0(t0)
li t0, MEM_STTIME3
li t1, 0x0303000c
sw t1, 0(t0)
li t0, MEM_STADDR3
li t1, 0x10e03f80 /* 1 MB */
sw t1, 0(t0)
sync
/* Set peripherals to a known state */
li t0, IC0_CFG0CLR
li t1, 0xFFFFFFFF
sw t1, 0(t0)
li t0, IC0_CFG0CLR
sw t1, 0(t0)
li t0, IC0_CFG1CLR
sw t1, 0(t0)
li t0, IC0_CFG2CLR
sw t1, 0(t0)
li t0, IC0_SRCSET
sw t1, 0(t0)
li t0, IC0_ASSIGNSET
sw t1, 0(t0)
li t0, IC0_WAKECLR
sw t1, 0(t0)
li t0, IC0_RISINGCLR
sw t1, 0(t0)
li t0, IC0_FALLINGCLR
sw t1, 0(t0)
li t0, IC0_TESTBIT
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, IC1_CFG0CLR
li t1, 0xFFFFFFFF
sw t1, 0(t0)
li t0, IC1_CFG0CLR
sw t1, 0(t0)
li t0, IC1_CFG1CLR
sw t1, 0(t0)
li t0, IC1_CFG2CLR
sw t1, 0(t0)
li t0, IC1_SRCSET
sw t1, 0(t0)
li t0, IC1_ASSIGNSET
sw t1, 0(t0)
li t0, IC1_WAKECLR
sw t1, 0(t0)
li t0, IC1_RISINGCLR
sw t1, 0(t0)
li t0, IC1_FALLINGCLR
sw t1, 0(t0)
li t0, IC1_TESTBIT
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, SYS_FREQCTRL0
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_FREQCTRL1
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_CLKSRC
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_PININPUTEN
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, 0xB1100100
li t1, 0x00000000
sw t1, 0(t0)
li t0, 0xB1400100
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_WAKEMSK
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_WAKESRC
li t1, 0x00000000
sw t1, 0(t0)
/* wait 1mS before setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
/* SDCS 0 SDRAM */
li t0, MEM_SDMODE0
li t1, 0x592CD1
sw t1, 0(t0)
li t0, MEM_SDMODE1
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_SDMODE2
li t1, 0x00000000
sw t1, 0(t0)
/* 64 MB SDRAM at addr 0 */
li t0, MEM_SDADDR0
li t1, 0x001003F0
sw t1, 0(t0)
li t0, MEM_SDADDR1
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_SDADDR2
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, MEM_SDREFCFG
li t1, 0x880007A1 /* Disable */
sw t1, 0(t0)
sync
li t0, MEM_SDPRECMD
sw zero, 0(t0)
sync
li t0, MEM_SDAUTOREF
sw zero, 0(t0)
sync
sw zero, 0(t0)
sync
li t0, MEM_SDREFCFG
li t1, 0x8A0007A1 /* Enable */
sw t1, 0(t0)
sync
li t0, MEM_SDWRMD0
li t1, 0x00000023
sw t1, 0(t0)
sync
/* wait 1mS after setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
/* Setup GPIO pins */
li t0, SYS_PINFUNC
li t1, 0x00007025 /* 0x8080 */
sw t1, 0(t0)
li t0, SYS_TRIOUTCLR
li t1, 0xFFFFFFFF /* 0x1FFF */
sw t1, 0(t0)
/* Turn yellow front led on */
/* Release reset on CF */
li t0, SYS_OUTPUTCLR
li t1, GPIO_RJ1LG
sw t1, 0(t0)
li t0, SYS_OUTPUTSET
li t1, GPIO_RJ1LY|GPIO_CFRESET
sw t1, 0(t0)
sync
j clearmem
nop
.globl memtest
memtest:
/* Fill memory with address */
li t0, 0x80000000
li t1, 0xFFF000 /* 64 MB */
mt0: sw t0, 0(t0)
add t1, -1
add t0, 4
bne t1, zero, mt0
nop
nop
/* Verify addr */
li t0, 0x80000000
li t1, 0xFFF000 /* 64 MB */
mt1: lw t2, 0(t0)
bne t0, t2, memhang
add t1, -1
add t0, 4
bne t1, zero, mt1
nop
nop
.globl clearmem
clearmem:
/* Clear memory */
li t0, 0x80000000
li t1, 0xFFF000 /* 64 MB */
mtc: sw zero, 0(t0)
add t1, -1
add t0, 4
bne t1, zero, mtc
nop
nop
memtestend:
j ra
nop
memhang:
b memhang
nop

68
board/gth2/u-boot.lds Normal file
View File

@ -0,0 +1,68 @@
/*
* (C) Copyright 2003-2005
* Wolfgang Denk Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.sdata : { *(.sdata) }
_gp = ALIGN(16);
__got_start = .;
.got : { *(.got) }
__got_end = .;
.sdata : { *(.sdata) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
. = ALIGN(4);
.sbss : { *(.sbss) }
.bss : { *(.bss) }
uboot_end = .;
}

8
board/mcc200/mcc200.c
View File

@ -28,7 +28,11 @@
#include <mpc5xxx.h>
#include <pci.h>
#include "mt48lc8m32b2-6-7.h"
/* Two MT48LC8M32B2 for 32 MB */
/* #include "mt48lc8m32b2-6-7.h" */
/* One MT48LC16M32S2 for 64 MB */
#include "mt48lc16m32s2-75.h"
DECLARE_GLOBAL_DATA_PTR;
@ -74,6 +78,8 @@ static void sdram_start (int hi_addr)
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
udelay(10);
}
#endif

43
board/mcc200/mt48lc16m32s2-75.h Normal file
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@ -0,0 +1,43 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 0 /* is SDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x00CD0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xD2322800
#define SDRAM_CONFIG2 0x8AD70000
#elif defined(CONFIG_MGT5100)
/* Settings for XLB = 66 MHz */
#define SDRAM_MODE 0x008D0000
#define SDRAM_CONTROL 0x504F0000
#define SDRAM_CONFIG1 0xC2222600
#define SDRAM_CONFIG2 0x88B70004
#define SDRAM_ADDRSEL 0x02000000
#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif

47
board/ppmc7xx/Makefile Normal file
View File

@ -0,0 +1,47 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := ppmc7xx.o pci.o flash.o
SOBJS := init.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

33
board/ppmc7xx/config.mk Normal file
View File

@ -0,0 +1,33 @@
#
# (C) Copyright 2005
# Richard Danter, Wind River Systems
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
#
#
TEXT_BASE = 0xFFF00000
TEXT_END = 0xFFF40000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

494
board/ppmc7xx/flash.c Normal file
View File

@ -0,0 +1,494 @@
/*
* flash.c
* -------
*
* Flash programming routines for the Wind River PPMC 74xx/7xx
* based on flash.c from the TQM8260 board.
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
#include <common.h>
#include <asm/processor.h>
#include <74xx_7xx.h>
#define DWORD unsigned long long
/* Local function prototypes */
static int write_dword (flash_info_t* info, ulong dest, unsigned char *pdata);
static void write_via_fpu (volatile DWORD* addr, DWORD* data);
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
/*-----------------------------------------------------------------------
*/
void flash_reset (void)
{
unsigned long msr;
DWORD cmd_reset = 0x00F000F000F000F0LL;
if (flash_info[0].flash_id != FLASH_UNKNOWN) {
msr = get_msr ();
set_msr (msr | MSR_FP);
write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
set_msr (msr);
}
}
/*-----------------------------------------------------------------------
*/
ulong flash_get_size (ulong baseaddr, flash_info_t * info)
{
int i;
unsigned long msr;
DWORD flashtest;
DWORD cmd_select[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
0x0090009000900090LL };
/* Enable FPU */
msr = get_msr ();
set_msr (msr | MSR_FP);
/* Write auto-select command sequence */
write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
/* Restore FPU */
set_msr (msr);
/* Read manufacturer ID */
flashtest = *(volatile DWORD*)baseaddr;
switch ((int)flashtest) {
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
default:
/* No, faulty or unknown flash */
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0);
}
/* Read device ID */
flashtest = *(volatile DWORD*)(baseaddr + 8);
switch ((long)flashtest) {
case AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00400000;
break;
case AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00400000;
break;
case AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00800000;
break;
case AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00800000;
break;
case AMD_ID_DL322T:
info->flash_id += FLASH_AMDL322T;
info->sector_count = 71;
info->size = 0x01000000;
break;
case AMD_ID_DL322B:
info->flash_id += FLASH_AMDL322B;
info->sector_count = 71;
info->size = 0x01000000;
break;
case AMD_ID_DL323T:
info->flash_id += FLASH_AMDL323T;
info->sector_count = 71;
info->size = 0x01000000;
break;
case AMD_ID_DL323B:
info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x01000000;
break;
case AMD_ID_LV640U:
info->flash_id += FLASH_AM640U;
info->sector_count = 128;
info->size = 0x02000000;
break;
default:
/* Unknown flash type */
info->flash_id = FLASH_UNKNOWN;
return (0);
}
if ((long)flashtest == AMD_ID_LV640U) {
/* set up sector start adress table (uniform sector type) */
for (i = 0; i < info->sector_count; i++)
info->start[i] = baseaddr + (i * 0x00040000);
} else if (info->flash_id & FLASH_BTYPE) {
/* set up sector start adress table (bottom sector type) */
info->start[0] = baseaddr + 0x00000000;
info->start[1] = baseaddr + 0x00010000;
info->start[2] = baseaddr + 0x00018000;
info->start[3] = baseaddr + 0x00020000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
}
} else {
/* set up sector start adress table (top sector type) */
i = info->sector_count - 1;
info->start[i--] = baseaddr + info->size - 0x00010000;
info->start[i--] = baseaddr + info->size - 0x00018000;
info->start[i--] = baseaddr + info->size - 0x00020000;
for (; i >= 0; i--) {
info->start[i] = baseaddr + i * 0x00040000;
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
if (*(volatile DWORD*)(info->start[i] + 16) & 0x0001000100010001LL) {
info->protect[i] = 1; /* D0 = 1 if protected */
} else {
info->protect[i] = 0;
}
}
flash_reset ();
return (info->size);
}
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0 = 0;
int i;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here (only one bank) */
size_b0 = flash_get_size (CFG_FLASH_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 >> 20);
}
/*
* protect monitor and environment sectors
*/
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
#endif
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
#endif
return (size_b0);
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf ("AMD ");
break;
case FLASH_MAN_FUJ:
printf ("FUJITSU ");
break;
default:
printf ("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM800T:
printf ("29LV800T (8 M, top sector)\n");
break;
case FLASH_AM800B:
printf ("29LV800T (8 M, bottom sector)\n");
break;
case FLASH_AM160T:
printf ("29LV160T (16 M, top sector)\n");
break;
case FLASH_AM160B:
printf ("29LV160B (16 M, bottom sector)\n");
break;
case FLASH_AMDL322T:
printf ("29DL322T (32 M, top sector)\n");
break;
case FLASH_AMDL322B:
printf ("29DL322B (32 M, bottom sector)\n");
break;
case FLASH_AMDL323T:
printf ("29DL323T (32 M, top sector)\n");
break;
case FLASH_AMDL323B:
printf ("29DL323B (32 M, bottom sector)\n");
break;
case FLASH_AM640U:
printf ("29LV640D (64 M, uniform sector)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " "
);
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect, l_sect;
ulong start, now, last;
unsigned long msr;
DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
0x0080008000800080LL, 0x00AA00AA00AA00AALL,
0x0055005500550055LL, 0x0030003000300030LL };
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect])
prot++;
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Enable FPU */
msr = get_msr();
set_msr ( msr | MSR_FP );
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[0] );
write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[1] );
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[2] );
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[3] );
write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[4] );
udelay (1000);
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
write_via_fpu ((DWORD*)info->start[sect], &cmd_erase[5] );
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* Restore FPU */
set_msr (msr);
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL )
!= 0x0080008000800080LL )
{
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
serial_putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
flash_reset ();
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong dp;
static unsigned char bb[8];
int i, l, rc, cc = cnt;
dp = (addr & ~7); /* get lower dword aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - dp) != 0) {
for (i = 0; i < 8; i++)
bb[i] = (i < l || (i - l) >= cc) ? *(char*)(dp + i) : *src++;
if ((rc = write_dword (info, dp, bb)) != 0) {
return (rc);
}
dp += 8;
cc -= 8 - l;
}
/*
* handle word aligned part
*/
while (cc >= 8) {
if ((rc = write_dword (info, dp, src)) != 0) {
return (rc);
}
dp += 8;
src += 8;
cc -= 8;
}
if (cc <= 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
for (i = 0; i < 8; i++) {
bb[i] = (i < cc) ? *src++ : *(char*)(dp + i);
}
return (write_dword (info, dp, bb));
}
/*-----------------------------------------------------------------------
* Write a dword to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
{
ulong start;
unsigned long msr;
int flag, i;
DWORD data;
DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
0x00A000A000A000A0LL };
for (data = 0, i = 0; i < 8; i++)
data = (data << 8) + *pdata++;
/* Check if Flash is (sufficiently) erased */
if ((*(DWORD*)dest & data) != data) {
return (2);
}
/* Enable FPU */
msr = get_msr();
set_msr( msr | MSR_FP );
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[0] );
write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_write[1] );
write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[2] );
write_via_fpu ((DWORD*)dest, &data );
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts ();
/* Restore FPU */
set_msr(msr);
/* data polling for D7 */
start = get_timer (0);
while (*(volatile DWORD*)dest != data ) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/
static void write_via_fpu (volatile DWORD* addr, DWORD* data)
{
__asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
__asm__ __volatile__ ("eieio");
}

336
board/ppmc7xx/init.S Normal file
View File

@ -0,0 +1,336 @@
/*
* init.S
* ------
*
* Wind River PPMC 7xx/74xx init code.
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*
* NOTE: The following code was generated automatically by Workbench
* from the ppmc7400_107.reg register file.
*/
#include <ppc_asm.tmpl>
.globl board_asm_init
board_asm_init:
lis r4,0xFEC0
ori r4,r4,0x0000
lis r5,0xFEE0
ori r5,r5,0x0000
lis r3,0x8000 # ADDR_00
ori r3,r3,0x0000
stwbrx r3,0,r4
li r3,0x1057 # VENDOR
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_02
ori r3,r3,0x0002
stwbrx r3,0,r4
li r3,0x0004 # ID
li r8, 0x2
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_04
ori r3,r3,0x0004
stwbrx r3,0,r4
li r3,0x0006 # PCICMD
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_06
ori r3,r3,0x0006
stwbrx r3,0,r4
li r3,0x00A0 # PCISTAT
li r8, 0x2
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_08
ori r3,r3,0x0008
stwbrx r3,0,r4
li r3,0x10 # REVID
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_09
ori r3,r3,0x0009
stwbrx r3,0,r4
li r3,0x00 # PROGIR
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_0A
ori r3,r3,0x000A
stwbrx r3,0,r4
li r3,0x00 # SUBCCODE
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_0B
ori r3,r3,0x000B
stwbrx r3,0,r4
li r3,0x06 # PBCCR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_0C
ori r3,r3,0x000C
stwbrx r3,0,r4
li r3,0x08 # PCLSR
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_0D
ori r3,r3,0x000D
stwbrx r3,0,r4
li r3,0x00 # PLTR
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_0E
ori r3,r3,0x000E
stwbrx r3,0,r4
li r3,0x00 # HEADTYPE
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_0F
ori r3,r3,0x000F
stwbrx r3,0,r4
li r3,0x00 # BISTCTRL
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_10
ori r3,r3,0x0010
stwbrx r3,0,r4
lis r3,0x0000 # LMBAR
ori r3,r3,0x0008
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_14
ori r3,r3,0x0014
stwbrx r3,0,r4
lis r3,0xF000 # PCSRBAR
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_3C
ori r3,r3,0x003C
stwbrx r3,0,r4
li r3,0x00 # ILR
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_3D
ori r3,r3,0x003D
stwbrx r3,0,r4
li r3,0x01 # INTPIN
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_3E
ori r3,r3,0x003E
stwbrx r3,0,r4
li r3,0x00 # MIN_GNT
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_3F
ori r3,r3,0x003F
stwbrx r3,0,r4
li r3,0x00 # MAX_LAT
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_40
ori r3,r3,0x0040
stwbrx r3,0,r4
li r3,0x00 # BUSNB
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_41
ori r3,r3,0x0041
stwbrx r3,0,r4
li r3,0x00 # SBUSNB
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_46
ori r3,r3,0x0046
stwbrx r3,0,r4
# li r3,0xE080 # PCIARB
li r3,-0x1F80 # PCIARB
li r8, 0x2
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_70
ori r3,r3,0x0070
stwbrx r3,0,r4
li r3,0x0000 # PMCR1
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_72
ori r3,r3,0x0072
stwbrx r3,0,r4
li r3,0xC0 # PMCR2
stb r3,0x2(r5)
lis r3,0x8000 # ADDR_73
ori r3,r3,0x0073
stwbrx r3,0,r4
li r3,0xEF # ODCR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_74
ori r3,r3,0x0074
stwbrx r3,0,r4
li r3,0x7D00 # CLKDCR
li r8, 0x0
sthbrx r3,r8,r5
lis r3,0x8000 # ADDR_76
ori r3,r3,0x0076
stwbrx r3,0,r4
li r3,0x00 # MDCR
stb r3,0x2(r5)
lis r6,0xFCE0
ori r6,r6,0x0000 # r6 is the EUMBAR Base Address
lis r3,0x8000 # ADDR_78
ori r3,r3,0x0078
stwbrx r3,0,r4
lis r3,0xFCE0 # EUMBBAR
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_80
ori r3,r3,0x0080
stwbrx r3,0,r4
lis r3,0xFFFF # MSADDR1
ori r3,r3,0x4000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_84
ori r3,r3,0x0084
stwbrx r3,0,r4
lis r3,0xFFFF # MSADDR2
ori r3,r3,0xFFFF
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_88
ori r3,r3,0x0088
stwbrx r3,0,r4
lis r3,0x0303 # EMSADDR1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_8C
ori r3,r3,0x008C
stwbrx r3,0,r4
lis r3,0x0303 # EMSADDR2
ori r3,r3,0x0303
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_90
ori r3,r3,0x0090
stwbrx r3,0,r4
lis r3,0xFFFF # EMEADDR1
ori r3,r3,0x7F3F
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_94
ori r3,r3,0x0094
stwbrx r3,0,r4
lis r3,0xFFFF # EMEADDR2
ori r3,r3,0xFFFF
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_98
ori r3,r3,0x0098
stwbrx r3,0,r4
lis r3,0x0303 # EXTEMEM1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_9C
ori r3,r3,0x009C
stwbrx r3,0,r4
lis r3,0x0303 # EXTEMEM2
ori r3,r3,0x0303
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_A0
ori r3,r3,0x00A0
stwbrx r3,0,r4
li r3,0x03 # MEMBNKEN
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_A3
ori r3,r3,0x00A3
stwbrx r3,0,r4
li r3,0x00 # MEMPMODE
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_B8
ori r3,r3,0x00B8
stwbrx r3,0,r4
li r3,0x00 # ECCCNT
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_B9
ori r3,r3,0x00B9
stwbrx r3,0,r4
li r3,0x00 # ECCTRG
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_C0
ori r3,r3,0x00C0
stwbrx r3,0,r4
li r3,0xFF # ERRENR1
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_C1
ori r3,r3,0x00C1
stwbrx r3,0,r4
li r3,0x00 # ERRDR1
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_C3
ori r3,r3,0x00C3
stwbrx r3,0,r4
li r3,0x50 # IPBESR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_C4
ori r3,r3,0x00C4
stwbrx r3,0,r4
li r3,0xBF # ERRENR2
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_C5
ori r3,r3,0x00C5
stwbrx r3,0,r4
li r3,0x00 # ERRDR2
stb r3,0x1(r5)
lis r3,0x8000 # ADDR_C7
ori r3,r3,0x00C7
stwbrx r3,0,r4
li r3,0x00 # PCIBESR
stb r3,0x3(r5)
lis r3,0x8000 # ADDR_C8
ori r3,r3,0x00C8
stwbrx r3,0,r4
lis r3,0x0000 # BERRADDR
ori r3,r3,0xE0FE
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_E0
ori r3,r3,0x00E0
stwbrx r3,0,r4
li r3,0xC0 # AMBOR
stb r3,0x0(r5)
lis r3,0x8000 # ADDR_F4
ori r3,r3,0x00F4
stwbrx r3,0,r4
lis r3,0x0000 # MCCR2
ori r3,r3,0x020C
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_F8
ori r3,r3,0x00F8
stwbrx r3,0,r4
lis r3,0x0230 # MCCR3
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_FC
ori r3,r3,0x00FC
stwbrx r3,0,r4
lis r3,0x2532 # MCCR4
ori r3,r3,0x2220
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_F0
ori r3,r3,0x00F0
stwbrx r3,0,r4
lis r3,0xFFC8 # MCCR1
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_A8
ori r3,r3,0x00A8
stwbrx r3,0,r4
lis r3,0xFF14 # PICR1
ori r3,r3,0x1CC8
li r8, 0x0
stwbrx r3,r8,r5
lis r3,0x8000 # ADDR_AC
ori r3,r3,0x00AC
stwbrx r3,0,r4
lis r3,0x0000 # PICR2
ori r3,r3,0x0000
li r8, 0x0
stwbrx r3,r8,r5
blr

97
board/ppmc7xx/pci.c Normal file
View File

@ -0,0 +1,97 @@
/*
* (C) Copyright 2002 ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* PCI initialisation for the MPC10x.
*/
#include <common.h>
#include <pci.h>
#include <mpc106.h>
#ifdef CONFIG_PCI
struct pci_controller local_hose;
void pci_init_board(void)
{
struct pci_controller* hose = (struct pci_controller *)&local_hose;
u16 reg16;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0,
CFG_PCI_MEMORY_BUS,
CFG_PCI_MEMORY_PHYS,
CFG_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
CFG_PCI_MEM_BUS,
CFG_PCI_MEM_PHYS,
CFG_PCI_MEM_SIZE,
PCI_REGION_MEM);
/* ISA/PCI memory space */
pci_set_region(hose->regions + 2,
CFG_ISA_MEM_BUS,
CFG_ISA_MEM_PHYS,
CFG_ISA_MEM_SIZE,
PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region(hose->regions + 3,
CFG_PCI_IO_BUS,
CFG_PCI_IO_PHYS,
CFG_PCI_IO_SIZE,
PCI_REGION_IO);
/* ISA/PCI I/O space */
pci_set_region(hose->regions + 4,
CFG_ISA_IO_BUS,
CFG_ISA_IO_PHYS,
CFG_ISA_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 5;
pci_setup_indirect(hose,
MPC106_REG_ADDR,
MPC106_REG_DATA);
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
/* Initialises the MPC10x PCI Configuration regs. */
pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
/* Clear non-reserved bits in status register */
pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
}
#endif /* CONFIG_PCI */

104
board/ppmc7xx/ppmc7xx.c Normal file
View File

@ -0,0 +1,104 @@
/*
* ppmc7xx.c
* ---------
*
* Main board-specific routines for Wind River PPMC 7xx/74xx board.
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
#include <common.h>
#include <command.h>
/* Define some MPC107 (memory controller) registers */
#define MPC107_EUMB_GCR 0xfce41020
#define MPC107_EUMB_IACKR 0xfce600a0
/* Function prototypes */
extern void unlock_ram_in_cache( void );
extern void _start_warm(void);
/*
* initdram()
*
* This function normally initialises the (S)DRAM of the system. For this board
* the SDRAM was already initialised by board_asm_init (see init.S) so we just
* return the size of RAM.
*/
long initdram( int board_type )
{
return CFG_SDRAM_SIZE;
}
/*
* after_reloc()
*
* This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
* us an opportunity to do some additional setup before the rest of the system
* is initialised. We don't need to do anything, so we just call board_init_r()
* which should never return.
*/
void after_reloc( ulong dest_addr, gd_t* gd )
{
/* Jump to the main U-Boot board init code */
board_init_r( gd, dest_addr );
}
/*
* checkboard()
*
* We could do some board level checks here, such as working out what version
* it is, but for this board we simply display it's name (on the console).
*/
int checkboard( void )
{
puts( "Board: Wind River PPMC 7xx/74xx\n" );
return 0;
}
/*
* misc_init_r
*
* Used for other setup which needs to be done late in the bring-up phase.
*/
int misc_init_r( void )
{
/* Reset the EPIC and clear pending interrupts */
out32r(MPC107_EUMB_GCR, 0xa0000000);
while( in32r( MPC107_EUMB_GCR ) & 0x80000000 );
out32r( MPC107_EUMB_GCR, 0x20000000 );
while( in32r( MPC107_EUMB_IACKR ) != 0xff );
/* Enable the I-Cache */
icache_enable();
return 0;
}
/*
* do_reset()
*
* Shell command to reset the board.
*/
void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
{
printf( "Resetting...\n" );
/* Disabe and invalidate cache */
icache_disable();
dcache_disable();
/* Jump to warm start (in RAM) */
_start_warm();
/* Should never get here */
while(1);
}

135
board/ppmc7xx/u-boot.lds Normal file
View File

@ -0,0 +1,135 @@
/*
* (C) Copyright 2001
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
/* common/environment.o(.text) */
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

1
board/tqm5200/Makefile
View File

@ -25,7 +25,6 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
#OBJS := $(BOARD).o flash.o
OBJS := $(BOARD).o cmd_stk52xx.o
$(LIB): $(OBJS) $(SOBJS)

497
board/tqm5200/flash.c
View File

@ -1,497 +0,0 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*
* CPU to flash interface is 32-bit, so make declaration accordingly
*/
typedef unsigned long FLASH_PORT_WIDTH;
typedef volatile unsigned long FLASH_PORT_WIDTHV;
#define FPW FLASH_PORT_WIDTH
#define FPWV FLASH_PORT_WIDTHV
#define FLASH_CYCLE1 0x0555
#define FLASH_CYCLE2 0x02aa
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(FPWV *addr, flash_info_t *info);
static void flash_reset(flash_info_t *info);
static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
static flash_info_t *flash_get_info(ulong base);
/*-----------------------------------------------------------------------
* flash_init()
*
* sets up flash_info and returns size of FLASH (bytes)
*/
unsigned long flash_init (void)
{
unsigned long size = 0;
extern void flash_preinit(void);
ulong flashbase = CFG_FLASH_BASE;
flash_preinit();
/* Init: no FLASHes known */
memset(&flash_info[0], 0, sizeof(flash_info_t));
flash_info[0].size =
flash_get_size((FPW *)flashbase, &flash_info[0]);
size = flash_info[0].size;
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
flash_get_info(CFG_MONITOR_BASE));
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR+CFG_ENV_SIZE-1,
flash_get_info(CFG_ENV_ADDR));
#endif
return size ? size : 1;
}
/*-----------------------------------------------------------------------
*/
static void flash_reset(flash_info_t *info)
{
FPWV *base = (FPWV *)(info->start[0]);
/* Put FLASH back in read mode */
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
*base = (FPW)0x00FF00FF; /* Intel Read Mode */
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
*base = (FPW)0x00F000F0; /* AMD Read Mode */
}
/*-----------------------------------------------------------------------
*/
static flash_info_t *flash_get_info(ulong base)
{
int i;
flash_info_t * info;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i];
if (info->size && info->start[0] <= base &&
base <= info->start[0] + info->size - 1)
break;
}
return i == CFG_MAX_FLASH_BANKS ? 0 : info;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
case FLASH_MAN_STM: printf ("STM "); break;
case FLASH_MAN_INTEL: printf ("INTEL "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AMLV128U:
printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
break;
case FLASH_AM160B:
printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20,
info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
if ((i % 5) == 0) {
printf ("\n ");
}
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
return;
}
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
ulong flash_get_size (FPWV *addr, flash_info_t *info)
{
int i;
ulong base = (ulong)addr;
/* Write auto select command: read Manufacturer ID */
/* Write auto select command sequence and test FLASH answer */
addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
/* The manufacturer codes are only 1 byte, so just use 1 byte.
* This works for any bus width and any FLASH device width.
*/
udelay(100);
switch (addr[0] & 0xff) {
case (uchar)AMD_MANUFACT:
debug ("Manufacturer: AMD (Spansion)\n");
info->flash_id = FLASH_MAN_AMD;
break;
case (uchar)INTEL_MANUFACT:
debug ("Manufacturer: Intel (not supported yet)\n");
info->flash_id = FLASH_MAN_INTEL;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
break;
}
/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
case (FPW)AMD_ID_LV160B:
debug ("Chip: AM29LV160MB\n");
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00400000;
/*
* The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
* the other ones are 64 kB
*/
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
info->start[2] = base + 0x0000C000;
info->start[3] = base + 0x00010000;
for( i = 4; i < info->sector_count; i++ )
info->start[i] =
base + (i * 2 * (64 << 10)) - 0x00060000;
break; /* => 4 MB */
case AMD_ID_MIRROR:
debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
addr[14], addr[15]);
switch(addr[14]) {
case AMD_ID_LV128U_2:
if (addr[15] != AMD_ID_LV128U_3) {
debug ("Chip: AM29LVxxxM -> unknown\n");
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
} else {
debug ("Chip: AM29LV128M\n");
info->flash_id += FLASH_AMLV128U;
info->sector_count = 256;
info->size = 0x02000000;
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base;
base += 0x20000;
}
}
break; /* => 32 MB */
default:
debug ("Chip: *** unknown ***\n");
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
break;
}
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
}
/* Put FLASH back in read mode */
flash_reset(info);
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
vu_long *addr = (vu_long*)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
addr[0x0555] = 0x00800080;
addr[0x0555] = 0x00AA00AA;
addr[0x02AA] = 0x00550055;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_long*)(info->start[sect]);
addr[0] = 0x00300030;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (vu_long*)(info->start[l_sect]);
while ((addr[0] & 0x00800080) != 0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (volatile unsigned long *)info->start[0];
addr[0] = 0x00F000F0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
/*
* Get lower word aligned address. Assumes 32 bit flash bus width.
*/
wp = (addr & ~3);
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word_amd(info, (FPW *)wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash for AMD FLASH
* A word is 16 or 32 bits, whichever the bus width of the flash bank
* (not an individual chip) is.
*
* returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
{
ulong start;
int flag;
FPWV *base; /* first address in flash bank */
/* Check if Flash is (sufficiently) erased */
if ((*dest & data) != data) {
return (2);
}
base = (FPWV *)(info->start[0]);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
*dest = data; /* start programming the data */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
start = get_timer (0);
/* data polling for D7 */
while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
*dest = (FPW)0x00F000F0; /* reset bank */
return (1);
}
}
return (0);
}

20
board/tqm5200/tqm5200.c
View File

@ -254,13 +254,7 @@ int checkboard (void)
puts ("Board: AEVFIFO\n");
return 0;
#endif
#if defined (CONFIG_TQM5200_AA)
puts ("Board: TQM5200-AA (TQ-Components GmbH)\n");
#elif defined (CONFIG_TQM5200_AB)
puts ("Board: TQM5200-AB (TQ-Components GmbH)\n");
#elif defined (CONFIG_TQM5200_AC)
puts ("Board: TQM5200-AC (TQ-Components GmbH)\n");
#elif defined (CONFIG_TQM5200)
#if defined (CONFIG_TQM5200)
puts ("Board: TQM5200 (TQ-Components GmbH)\n");
#endif
#if defined (CONFIG_STK52XX)
@ -572,17 +566,7 @@ static const SMI_REGS init_regs [] =
void video_get_info_str (int line_number, char *info)
{
if (line_number == 1) {
#if defined (CONFIG_TQM5200_AA)
strcpy (info, " Board: TQM5200-AA (TQ-Components GmbH)");
#elif defined (CONFIG_TQM5200_AB)
strcpy (info, " Board: TQM5200-AB (TQ-Components GmbH)");
#elif defined (CONFIG_TQM5200_AC)
strcpy (info, " Board: TQM5200-AC (TQ-Components GmbH)");
#elif defined (CONFIG_TQM5200)
strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
#else
#error No supported board selected
#endif
strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
#if defined (CONFIG_STK52XX)
} else if (line_number == 2) {
strcpy (info, " on a STK52XX baseboard");

24
board/tqm834x/tqm834x.c
View File

@ -406,4 +406,28 @@ static void set_ddr_config(void) {
(DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
(DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
SYNC;
/* Workaround for DDR6 Erratum
* see MPC8349E Device Errata Rev.8, 2/2006
* This workaround influences the MPC internal "input enables"
* dependent on CAS latency and MPC revision. According to errata
* sheet the internal reserved registers for this workaround are
* not available from revision 2.0 and up.
*/
/* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
* (0x200)
*/
if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
/* There is a internal reserved register at IMMRBAR+0x2F00
* which has to be written with a certain value defined by
* errata sheet.
*/
#if defined(DDR_CASLAT_20)
*((u8 *)im + 0x2f00) = 0x201c0000;
#else
*((u8 *)im + 0x2f00) = 0x202c0000;
#endif
}
}

14
board/tqm85xx/tqm85xx.c
View File

@ -27,6 +27,9 @@
* MA 02111-1307 USA
*/
#ifdef CONFIG_PS2MULT
void ps2mult_early_init(void);
#endif
#include <common.h>
#include <pci.h>
@ -410,3 +413,14 @@ void pci_init_board (void)
pci_mpc85xx_init (&hose);
#endif /* CONFIG_PCI */
}
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
#ifdef CONFIG_PS2MULT
ps2mult_early_init();
#endif /* CONFIG_PS2MULT */
return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */

1
board/trab/cmd_trab.c
View File

@ -729,6 +729,7 @@ static void led_blink (void)
/* blink LED. This function does not return! */
while (1) {
reset_timer_masked ();
led_set (1);
udelay (1000000 / LED_BLINK_FREQ / 2);
led_set (0);

13
board/trab/trab.c
View File

@ -161,6 +161,19 @@ int misc_init_r (void)
uchar *str;
int i;
#ifdef CONFIG_VERSION_VARIABLE
{
/* Set version variable. Please note, that this variable is
* also set in main_loop() later in the boot process. The
* version variable has to be set this early, because so it
* could be used in script files on an usb stick, which
* might be called during do_auto_update() */
extern char version_string[];
setenv ("ver", version_string);
}
#endif /* CONFIG_VERSION_VARIABLE */
#ifdef CONFIG_AUTO_UPDATE
extern int do_auto_update(void);
/* this has priority over all else */

2
board/trab/tsc2000.c
View File

@ -223,7 +223,7 @@ u16 tsc2000_read_channel (unsigned int channel)
u16 res;
tsc2000_set_mux(channel);
udelay(3 * TSC2000_DELAY_BASE);
udelay(20 * TSC2000_DELAY_BASE);
tsc2000_write(TSC2000_REG_ADC, 0x2036);
adc_wait_conversion_done ();

6
board/trab/vfd.c
View File

@ -358,6 +358,8 @@ void transfer_pic(int display, unsigned char *adr, int height, int width)
*/
int vfd_init_clocks (void)
{
int i;
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
@ -367,7 +369,9 @@ int vfd_init_clocks (void)
*/
gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pullups */
gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as inputs */
udelay (10); /* allow signals to settle */
/* allow signals to settle */
for (i=0; i<10000; i++) /* udelay isn't working yet at this point! */
__asm("NOP");
vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */
VFD_DISABLE; /* activate blank for the vfd */

2
board/voiceblue/config.mk
View File

@ -12,5 +12,5 @@ ifeq ($(VOICEBLUE_SMALL_FLASH),y)
TEXT_BASE = 0x20012000
else
# Running in SDRAM...
TEXT_BASE = 0x13000000
TEXT_BASE = 0x13FD0000
endif

7
common/cmd_ide.c
View File

@ -855,7 +855,7 @@ output_data_short(int dev, ulong *sect_buf, int words)
/* We only need to swap data if we are running on a big endian cpu. */
/* But Au1x00 cpu:s already swaps data in big endian mode! */
#if defined(__LITTLE_ENDIAN) || defined(CONFIG_AU1X00)
#if defined(__LITTLE_ENDIAN) || ( defined(CONFIG_AU1X00) && !defined(CONFIG_GTH2) )
#define input_swap_data(x,y,z) input_data(x,y,z)
#else
static void
@ -881,8 +881,13 @@ input_swap_data(int dev, ulong *sect_buf, int words)
debug("in input swap data base for read is %lx\n", (unsigned long) pbuf);
while (words--) {
#ifdef __MIPS__
*dbuf++ = swab16p((u16*)pbuf);
*dbuf++ = swab16p((u16*)pbuf);
#else
*dbuf++ = ld_le16(pbuf);
*dbuf++ = ld_le16(pbuf);
#endif /* !MIPS */
}
#endif
}

4
common/serial.c
View File

@ -41,7 +41,7 @@ struct serial_device *default_serial_console (void)
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
return &serial_scc_device;
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP)
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
return &serial0_device;
#else
#error No default console
@ -75,7 +75,7 @@ void serial_initialize (void)
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP)
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
serial_register(&serial0_device);
serial_register(&serial1_device);
#endif

3
cpu/74xx_7xx/cpu.c
View File

@ -215,7 +215,8 @@ soft_restart(unsigned long addr)
#if !defined(CONFIG_PCIPPC2) && \
!defined(CONFIG_BAB7xx) && \
!defined(CONFIG_ELPPC)
!defined(CONFIG_ELPPC) && \
!defined(CONFIG_PPMC7XX)
/* no generic way to do board reset. simply call soft_reset. */
void
do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

3
cpu/74xx_7xx/start.S
View File

@ -756,7 +756,8 @@ in_ram:
#if defined(CONFIG_AMIGAONEG3SE) || \
defined(CONFIG_DB64360) || \
defined(CONFIG_DB64460) || \
defined(CONFIG_CPCI750)
defined(CONFIG_CPCI750) || \
defined(CONFIG_PPMC7XX)
mr r4, r9 /* Use RAM copy of the global data */
#endif
bl after_reloc

2
cpu/arm920t/s3c24x0/i2c.c
View File

@ -153,7 +153,7 @@ void i2c_init (int speed, int slaveadd)
#endif
#ifdef CONFIG_S3C2400
/* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00000c00;
gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00001000;
#endif
/* toggle I2CSCL until bus idle */

181
cpu/mpc5xxx/serial.c
View File

@ -23,6 +23,9 @@
* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
* changes based on the file arch/ppc/mbxboot/m8260_tty.c from the
* Linux/PPC sources (m8260_tty.c had no copyright info in it).
*
* Martin Krause, 8 Jun 2006
* Added CONFIG_SERIAL_MULTI support
*/
/*
@ -33,6 +36,10 @@
#include <common.h>
#include <mpc5xxx.h>
#if defined (CONFIG_SERIAL_MULTI)
#include <serial.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_PSC_CONSOLE)
@ -55,9 +62,41 @@ DECLARE_GLOBAL_DATA_PTR;
#error CONFIG_PSC_CONSOLE must be in 1 ... 6
#endif
#if defined(CONFIG_SERIAL_MULTI) && !defined(CONFIG_PSC_CONSOLE2)
#error you must define CONFIG_PSC_CONSOLE2 if CONFIG_SERIAL_MULTI is set
#endif
#if defined(CONFIG_SERIAL_MULTI)
#if CONFIG_PSC_CONSOLE2 == 1
#define PSC_BASE2 MPC5XXX_PSC1
#elif CONFIG_PSC_CONSOLE2 == 2
#define PSC_BASE2 MPC5XXX_PSC2
#elif CONFIG_PSC_CONSOLE2 == 3
#define PSC_BASE2 MPC5XXX_PSC3
#elif defined(CONFIG_MGT5100)
#error CONFIG_PSC_CONSOLE2 must be in 1, 2 or 3
#elif CONFIG_PSC_CONSOLE2 == 4
#define PSC_BASE2 MPC5XXX_PSC4
#elif CONFIG_PSC_CONSOLE2 == 5
#define PSC_BASE2 MPC5XXX_PSC5
#elif CONFIG_PSC_CONSOLE2 == 6
#define PSC_BASE2 MPC5XXX_PSC6
#else
#error CONFIG_PSC_CONSOLE2 must be in 1 ... 6
#endif
#endif /* CONFIG_SERIAL_MULTI */
#if defined(CONFIG_SERIAL_MULTI)
int serial_init_dev (unsigned long dev_base)
#else
int serial_init (void)
#endif
{
#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
#else
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#endif
unsigned long baseclk;
int div;
@ -100,13 +139,24 @@ int serial_init (void)
return (0);
}
void
serial_putc(const char c)
#if defined(CONFIG_SERIAL_MULTI)
void serial_putc_dev (unsigned long dev_base, const char c)
#else
void serial_putc(const char c)
#endif
{
#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
#else
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#endif
if (c == '\n')
#if defined(CONFIG_SERIAL_MULTI)
serial_putc_dev (dev_base, '\r');
#else
serial_putc('\r');
#endif
/* Wait for last character to go. */
while (!(psc->psc_status & PSC_SR_TXEMP))
@ -115,18 +165,32 @@ serial_putc(const char c)
psc->psc_buffer_8 = c;
}
void
serial_puts (const char *s)
#if defined(CONFIG_SERIAL_MULTI)
void serial_puts_dev (unsigned long dev_base, const char *s)
#else
void serial_puts (const char *s)
#endif
{
while (*s) {
#if defined(CONFIG_SERIAL_MULTI)
serial_putc_dev (dev_base, *s++);
#else
serial_putc (*s++);
#endif
}
}
int
serial_getc(void)
#if defined(CONFIG_SERIAL_MULTI)
int serial_getc_dev (unsigned long dev_base)
#else
int serial_getc(void)
#endif
{
#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
#else
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#endif
/* Wait for a character to arrive. */
while (!(psc->psc_status & PSC_SR_RXRDY))
@ -135,18 +199,32 @@ serial_getc(void)
return psc->psc_buffer_8;
}
int
serial_tstc(void)
#if defined(CONFIG_SERIAL_MULTI)
int serial_tstc_dev (unsigned long dev_base)
#else
int serial_tstc(void)
#endif
{
#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
#else
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#endif
return (psc->psc_status & PSC_SR_RXRDY);
}
void
serial_setbrg(void)
#if defined(CONFIG_SERIAL_MULTI)
void serial_setbrg_dev (unsigned long dev_base)
#else
void serial_setbrg(void)
#endif
{
#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
#else
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#endif
unsigned long baseclk, div;
#if defined(CONFIG_MGT5100)
@ -160,4 +238,87 @@ serial_setbrg(void)
psc->ctur = (div >> 8) & 0xFF;
psc->ctlr = div & 0xff;
}
#if defined(CONFIG_SERIAL_MULTI)
int serial0_init(void)
{
return (serial_init_dev(PSC_BASE));
}
int serial1_init(void)
{
return (serial_init_dev(PSC_BASE2));
}
void serial0_setbrg (void)
{
serial_setbrg_dev(PSC_BASE);
}
void serial1_setbrg (void)
{
serial_setbrg_dev(PSC_BASE2);
}
void serial0_putc(const char c)
{
serial_putc_dev(PSC_BASE,c);
}
void serial1_putc(const char c)
{
serial_putc_dev(PSC_BASE2, c);
}
void serial0_puts(const char *s)
{
serial_puts_dev(PSC_BASE, s);
}
void serial1_puts(const char *s)
{
serial_puts_dev(PSC_BASE2, s);
}
int serial0_getc(void)
{
return(serial_getc_dev(PSC_BASE));
}
int serial1_getc(void)
{
return(serial_getc_dev(PSC_BASE2));
}
int serial0_tstc(void)
{
return (serial_tstc_dev(PSC_BASE));
}
int serial1_tstc(void)
{
return (serial_tstc_dev(PSC_BASE2));
}
struct serial_device serial0_device =
{
"serial0",
"UART0",
serial0_init,
serial0_setbrg,
serial0_getc,
serial0_tstc,
serial0_putc,
serial0_puts,
};
struct serial_device serial1_device =
{
"serial1",
"UART1",
serial1_init,
serial1_setbrg,
serial1_getc,
serial1_tstc,
serial1_putc,
serial1_puts,
};
#endif /* CONFIG_SERIAL_MULTI */
#endif /* CONFIG_PSC_CONSOLE */

26
doc/README.serial_multi
View File

@ -52,3 +52,29 @@ PPC4XX Specific
setenv stdout serial0
setenv stderr serial0
setenv stdin serial0
MPC5xxx Specific
================
Up to two PSCs can be used as console.
Support for hardware handshake has not been implemented yet.
*) The first (default) console port is defined by:
#define CONFIG_PSC_CONSOLE <PSC number>
*) The second (alternative) console port is defined by:
#define CONFIG_PSC_CONSOLE2 <PSC number>
*) Commands to switch to the second console:
setenv stdout serial1
setenv stderr serial1
setenv stdin serial1
*) Commands to switch to the first console:
setenv stdout serial0
setenv stderr serial0
setenv stdin serial0
*) If a file descriptor is set to "serial" then the
current serial device will be used.

6
drivers/keyboard.c
View File

@ -33,7 +33,7 @@
#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
#ifdef CONFIG_MPC5xxx
#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC85xx)
int ps2ser_check(void);
#endif
@ -75,7 +75,7 @@ static void kbd_put_queue(char data)
/* test if a character is in the queue */
static int kbd_testc(void)
{
#ifdef CONFIG_MPC5xxx
#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC85xx)
/* no ISR is used, so received chars must be polled */
ps2ser_check();
#endif
@ -90,7 +90,7 @@ static int kbd_getc(void)
{
char c;
while(in_pointer==out_pointer) {
#ifdef CONFIG_MPC5xxx
#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC85xx)
/* no ISR is used, so received chars must be polled */
ps2ser_check();
#endif

2
drivers/pci.c
View File

@ -163,7 +163,7 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
#endif
for (bdf = PCI_BDF(bus,0,0);
#ifdef CONFIG_ELPPC
#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
#else
bdf < PCI_BDF(bus+1,0,0);

55
drivers/ps2ser.c
View File

@ -20,6 +20,9 @@
#include <asm/io.h>
#include <asm/atomic.h>
#include <ps2mult.h>
#ifdef CFG_NS16550
#include <ns16550.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@ -45,13 +48,24 @@ DECLARE_GLOBAL_DATA_PTR;
#else
#error CONFIG_PS2SERIAL must be in 1 ... 6
#endif
#endif /* CONFIG_MPC5xxx */
#elif defined(CONFIG_MPC85xx)
#if CONFIG_PS2SERIAL == 1
#define COM_BASE (CFG_CCSRBAR+0x4500)
#elif CONFIG_PS2SERIAL == 2
#define COM_BASE (CFG_CCSRBAR+0x4600)
#else
#error CONFIG_PS2SERIAL must be in 1 ... 2
#endif
#endif /* CONFIG_MPC5xxx / CONFIG_MPC85xx */
static int ps2ser_getc_hw(void);
static void ps2ser_interrupt(void *dev_id);
extern struct serial_state rs_table[]; /* in serial.c */
#ifndef CONFIG_MPC5xxx
#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC85xx)
static struct serial_state *state;
#endif
@ -106,7 +120,23 @@ int ps2ser_init(void)
return (0);
}
#else /* !CONFIG_MPC5xxx */
#elif defined(CONFIG_MPC85xx)
int ps2ser_init(void)
{
NS16550_t com_port = (NS16550_t)COM_BASE;
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE | LCR_8N1;
com_port->dll = (CFG_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
com_port->dlm = ((CFG_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
com_port->lcr = LCR_8N1;
com_port->mcr = (MCR_DTR | MCR_RTS);
com_port->fcr = (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR);
return (0);
}
#else /* !CONFIG_MPC5xxx && !CONFIG_MPC85xx */
static inline unsigned int ps2ser_in(int offset)
{
@ -150,12 +180,14 @@ int ps2ser_init(void)
return 0;
}
#endif /* CONFIG_MPC5xxx */
#endif /* CONFIG_MPC5xxx / CONFIG_MPC85xx / other */
void ps2ser_putc(int chr)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#elif defined(CONFIG_MPC85xx)
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
#ifdef DEBUG
printf(">>>> 0x%02x\n", chr);
@ -165,6 +197,9 @@ void ps2ser_putc(int chr)
while (!(psc->psc_status & PSC_SR_TXRDY));
psc->psc_buffer_8 = chr;
#elif defined(CONFIG_MPC85xx)
while ((com_port->lsr & LSR_THRE) == 0);
com_port->thr = chr;
#else
while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
@ -176,6 +211,8 @@ static int ps2ser_getc_hw(void)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#elif defined(CONFIG_MPC85xx)
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
int res = -1;
@ -183,6 +220,10 @@ static int ps2ser_getc_hw(void)
if (psc->psc_status & PSC_SR_RXRDY) {
res = (psc->psc_buffer_8);
}
#elif defined(CONFIG_MPC85xx)
if (com_port->lsr & LSR_DR) {
res = com_port->rbr;
}
#else
if (ps2ser_in(UART_LSR) & UART_LSR_DR) {
res = (ps2ser_in(UART_RX));
@ -238,6 +279,8 @@ static void ps2ser_interrupt(void *dev_id)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#elif defined(CONFIG_MPC85xx)
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
int chr;
int status;
@ -246,6 +289,8 @@ static void ps2ser_interrupt(void *dev_id)
chr = ps2ser_getc_hw();
#ifdef CONFIG_MPC5xxx
status = psc->psc_status;
#elif defined(CONFIG_MPC85xx)
status = com_port->lsr;
#else
status = ps2ser_in(UART_IIR);
#endif
@ -260,6 +305,8 @@ static void ps2ser_interrupt(void *dev_id)
}
#ifdef CONFIG_MPC5xxx
} while (status & PSC_SR_RXRDY);
#elif defined(CONFIG_MPC85xx)
} while (status & LSR_DR);
#else
} while (status & UART_IIR_RDI);
#endif

5
include/asm-mips/au1x00.h
View File

@ -119,6 +119,11 @@ static __inline__ int au_ffs(int x)
return __ilog2(x & -x) + 1;
}
#define gpio_set(Value) outl(Value, SYS_OUTPUTSET)
#define gpio_clear(Value) outl(Value, SYS_OUTPUTCLR)
#define gpio_read() inl(SYS_PINSTATERD)
#define gpio_tristate(Value) outl(Value, SYS_TRIOUTCLR)
#endif /* !ASSEMBLY */
#ifdef CONFIG_PM

31
include/configs/TQM5200.h
View File

@ -37,7 +37,6 @@
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
@ -83,7 +82,7 @@
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_NET_MULTI 1
#define CONFIG_EEPRO100
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#endif /* CONFIG_STK52XX */
@ -192,16 +191,6 @@
#undef CONFIG_BOOTARGS
#if defined (CONFIG_TQM5200_AA)
# define CONFIG_U_BOOT_SUFFIX "-AA\0"
#elif defined (CONFIG_TQM5200_AB)
# define CONFIG_U_BOOT_SUFFIX "-AB\0"
#elif defined (CONFIG_TQM5200_AC)
# define CONFIG_U_BOOT_SUFFIX "-AC\0"
#else
# define CONFIG_U_BOOT_SUFFIX "\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
@ -218,7 +207,7 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
"load=tftp 200000 ${u-boot}\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
@ -284,13 +273,6 @@
#endif
/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
CFG_I2C_SLAVE }
#elif defined (CONFIG_TQM5200_AC)
#define I2C_ADDR_LIST { CFG_I2C_SLAVE }
#endif
#if defined (CONFIG_MINIFAP)
#undef I2C_ADDR_LIST
#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
@ -493,13 +475,9 @@
* SRAM - Do not map below 2 GB in address space, because this area is used
* for SDRAM autosizing.
*/
#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF)
#if defined (CONFIG_CS_AUTOCONF)
#define CFG_CS2_START 0xE5000000
#ifdef CONFIG_TQM5200_AB
#define CFG_CS2_SIZE 0x80000 /* 512 kByte */
#else /* CONFIG_CS_AUTOCONF */
#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
#endif
#define CFG_CS2_CFG 0x0004D930
#endif
@ -507,8 +485,7 @@
* Grafic controller - Do not map below 2 GB in address space, because this
* area is used for SDRAM autosizing.
*/
#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \
defined (CONFIG_CS_AUTOCONF)
#if defined (CONFIG_CS_AUTOCONF)
#define SM501_FB_BASE 0xE0000000
#define CFG_CS1_START (SM501_FB_BASE)
#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */

7
include/configs/TQM85xx.h
View File

@ -177,6 +177,13 @@
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
/* PS/2 Keyboard */
#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
#define CONFIG_BOARD_EARLY_INIT_R 1
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER

11
include/configs/cmc_pu2.h
View File

@ -108,7 +108,7 @@
/* still about 20 kB free with this defined */
#define CFG_LONGHELP
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTDELAY 1
#ifdef CONFIG_HARD_I2C
#define CONFIG_COMMANDS \
@ -206,15 +206,6 @@ struct bd_info_ext {
#error CONFIG_USE_IRQ not supported
#endif
#define CFG_DEVICE_NULLDEV 1 /* enble null device */
#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
#define CONFIG_AUTOBOOT_STOP_STR "R" /* default password */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CONFIG_EXTRA_ENV_SETTINGS \
"net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \
"addmtd;bootm\0" \

195
include/configs/gth2.h Normal file
View File

@ -0,0 +1,195 @@
/*
* (C) Copyright 2005
* Thomas.Lange@corelatus.se
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file contains the configuration parameters for the gth2 board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_GTH2 1
#define CONFIG_AU1X00 1 /* alchemy series cpu */
#define CONFIG_AU1000 1
#define CONFIG_MISC_INIT_R 1
#define CONFIG_ETHADDR DE:AD:BE:EF:01:02 /* Ethernet address */
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */
#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */
#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */
#define CONFIG_BAUDRATE 115200
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 115200 }
/* Only interrupt boot if space is pressed */
/* If a long serial cable is connected but */
/* other end is dead, garbage will be read */
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n"
#define CONFIG_AUTOBOOT_DELAY_STR "d"
#define CONFIG_AUTOBOOT_STOP_STR " "
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_BOOTARGS "panic=1"
#define CONFIG_EXTRA_ENV_SETTINGS \
"addmisc=setenv bootargs $(bootargs) " \
"ethaddr=$(ethaddr) \0" \
"netboot=bootp;run addmisc;bootm\0" \
""
/* Boot from Compact flash partition 2 as default */
#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm"
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \
~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \
CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT ))
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "GTH2 # " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args*/
#define CFG_MALLOC_LEN 128*1024
#define CFG_BOOTPARAMS_LEN 128*1024
#define CFG_MHZ 500
#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
#define CFG_LOAD_ADDR 0x81000000 /* default load address */
#define CFG_MEMTEST_START 0x80100000
#define CFG_MEMTEST_END 0x83000000
#define CONFIG_HW_WATCHDOG 1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
#define PHYS_FLASH 0xbfc00000 /* Flash Bank #1 */
/* The following #defines are needed to get flash environment right */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (192 << 10)
#define CFG_INIT_SP_OFFSET 0x400000
/* We boot from this flash, selected with dip switch */
#define CFG_FLASH_BASE PHYS_FLASH
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
#define CFG_ENV_IS_NOWHERE 1
/* Address and size of Primary Environment Sector */
#define CFG_ENV_ADDR 0xB0030000
#define CFG_ENV_SIZE 0x10000
#define CONFIG_FLASH_16BIT
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_NET_MULTI
#define CONFIG_MEMSIZE_IN_BYTES
/*---ATA PCMCIA ------------------------------------*/
#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
#define CFG_PCMCIA_MEM_ADDR 0x20000000
#define CFG_PCMCIA_IO_BASE 0x28000000
#define CFG_PCMCIA_ATTR_BASE 0x30000000
#define CONFIG_PCMCIA_SLOT_A
#define CONFIG_ATAPI 1
#define CONFIG_MAC_PARTITION 1
/* We run CF in "true ide" mode or a harddrive via pcmcia */
#define CONFIG_IDE_PCMCIA 1
/* We only support one slot for now */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define CFG_ATA_IDE0_OFFSET 0
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_IO_BASE
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET 0
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET 0
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET 0x0200
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384
#define CFG_ICACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
#define GPIO_CACONFIG (1<<0)
#define GPIO_DPACONFIG (1<<6)
#define GPIO_ERESET (1<<11)
#define GPIO_EEDQ (1<<17)
#define GPIO_WDI (1<<18)
#define GPIO_RJ1LY (1<<22)
#define GPIO_RJ1LG (1<<23)
#define GPIO_LEDCLK (1<<29)
#define GPIO_LEDD (1<<30)
#define GPIO_CPU_LED (1<<31)
#endif /* __CONFIG_H */

419
include/configs/ppmc7xx.h Normal file
View File

@ -0,0 +1,419 @@
/*
* ppmc7xx.h
* ---------
*
* Wind River PPMC 7xx/74xx board configuration file.
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_PPMC7XX
/*===================================================================
*
* User configurable settings - Modify to your preference
*
*===================================================================
*/
/*
* Debug
*
* DEBUG - Define this is you want extra debug info
* GTREGREAD - Required to build with debug
* do_bdinfo - Required to build with debug
*/
#undef DEBUG
#define GTREGREAD(x) 0xFFFFFFFF
#define do_bdinfo(a,b,c,d)
/*
* CPU type
*
* CONFIG_7xx - We have a 750 or 755 CPU
* CONFIG_74xx - We have a 7400 CPU
* CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
* CONFIG_BUS_CLK - System bus clock in Hz
*/
#define CONFIG_7xx
#undef CONFIG_74xx
#undef CONFIG_ALTIVEC
#define CONFIG_BUS_CLK 66000000
/*
* Monitor configuration
*
* CONFIG_COMMANDS - List of command sets to include in shell
*
* The following command sets have been tested and known to work:
*
* CFG_CMD_CACHE - Cache control commands
* CFG_CMD_MEMORY - Memory display, change and test commands
* CFG_CMD_FLASH - Erase and program flash
* CFG_CMD_ENV - Environment commands
* CFG_CMD_RUN - Run commands stored in env vars
* CFG_CMD_ELF - Load ELF files
* CFG_CMD_NET - Networking/file download commands
* CFG_CMD_PING - ICMP Echo Request command
* CFG_CMD_PCI - PCI Bus scanning command
*/
#define CONFIG_COMMANDS ( (CFG_CMD_DFL & ~(CFG_CMD_KGDB)) | \
CFG_CMD_FLASH | \
CFG_CMD_ENV | \
CFG_CMD_RUN | \
CFG_CMD_ELF | \
CFG_CMD_NET | \
CFG_CMD_PING | \
CFG_CMD_PCI)
/*
* Serial configuration
*
* CONFIG_CONS_INDEX - Serial console port number (COM1)
* CONFIG_BAUDRATE - Serial speed
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 9600
/*
* PCI config
*
* CONFIG_PCI - Enable PCI bus
* CONFIG_PCI_PNP - Enable Plug & Play support
* CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
*/
#define CONFIG_PCI
#define CONFIG_PCI_PNP
#undef CONFIG_PCI_SCAN_SHOW
/*
* Network config
*
* CONFIG_NET_MULTI - Support for multiple network interfaces
* CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
* CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
*/
#define CONFIG_NET_MULTI
#define CONFIG_EEPRO100
#define CONFIG_EEPRO100_SROM_WRITE
/*
* Enable extra init functions
*
* CONFIG_MISC_INIT_F - Call pre-relocation init functions
* CONFIG_MISC_INIT_R - Call post relocation init functions
*/
#undef CONFIG_MISC_INIT_F
#define CONFIG_MISC_INIT_R
/*
* Boot config
*
* CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
* CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
*/
#define CONFIG_BOOTCOMMAND \
"bootp;" \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
"bootm"
#define CONFIG_BOOTDELAY 5
/*===================================================================
*
* Board configuration settings - You should not need to modify these
*
*===================================================================
*/
#include <cmd_confdefs.h>
/*
* Memory map
*
* This board runs in a standard CHRP (Map-B) configuration.
*
* Type Start End Size Width Chip Sel
* ----------- ----------- ----------- ------- ------- --------
* SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
* User LED's 0x78000000 RCS3
* UART 0x7C000000 RCS2
* Mailbox 0xFF000000 RCS1
* Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
*
* Flash sectors are laid out as follows.
*
* Sector Start End Size Comments
* ------- ----------- ----------- ------- -----------
* 0 0xFFC00000 0xFFC3FFFF 256KB
* 1 0xFFC40000 0xFFC7FFFF 256KB
* 2 0xFFC80000 0xFFCBFFFF 256KB
* 3 0xFFCC0000 0xFFCFFFFF 256KB
* 4 0xFFD00000 0xFFD3FFFF 256KB
* 5 0xFFD40000 0xFFD7FFFF 256KB
* 6 0xFFD80000 0xFFDBFFFF 256KB
* 7 0xFFDC0000 0xFFDFFFFF 256KB
* 8 0xFFE00000 0xFFE3FFFF 256KB
* 9 0xFFE40000 0xFFE7FFFF 256KB
* 10 0xFFE80000 0xFFEBFFFF 256KB
* 11 0xFFEC0000 0xFFEFFFFF 256KB
* 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
* 13 0xFFF40000 0xFFF7FFFF 256KB
* 14 0xFFF80000 0xFFFBFFFF 256KB
* 15 0xFFFC0000 0xFFFDFFFF 128KB
* 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
* 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
* 18 0xFFFF0000 0xFFFFFFFF 64KB
*/
/*
* SDRAM config - see memory map details above.
*
* CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
* CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 0x04000000
/*
* Flash config - see memory map details above.
*
* CFG_FLASH_BASE - Start address of flash memory
* CFG_FLASH_SIZE - Total size of contiguous flash mem
* CFG_FLASH_ERASE_TOUT - Erase timeout in ms
* CFG_FLASH_WRITE_TOUT - Write timeout in ms
* CFG_MAX_FLASH_BANKS - Number of banks of flash on board
* CFG_MAX_FLASH_SECT - Number of sectors in a bank
*/
#define CFG_FLASH_BASE 0xFFC00000
#define CFG_FLASH_SIZE 0x00400000
#define CFG_FLASH_ERASE_TOUT 250000
#define CFG_FLASH_WRITE_TOUT 5000
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MAX_FLASH_SECT 19
/*
* Monitor config - see memory map details above
*
* CFG_MONITOR_BASE - Base address of monitor code
* CFG_MALLOC_LEN - Size of malloc pool (128KB)
*/
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MALLOC_LEN 0x20000
/*
* Command shell settings
*
* CFG_BARGSIZE - Boot Argument buffer size
* CFG_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
* CFG_CBSIZE - Console Buffer (input) size
* CFG_LOAD_ADDR - Default load address
* CFG_LONGHELP - Provide more detailed help
* CFG_MAXARGS - Number of args accepted by monitor commands
* CFG_MEMTEST_START - Start address of test to run on RAM
* CFG_MEMTEST_END - End address of RAM test
* CFG_PBSIZE - Print Buffer (output) size
* CFG_PROMPT - Prompt string
*/
#define CFG_BARGSIZE 1024
#define CFG_BOOTMAPSZ 0x800000
#define CFG_CBSIZE 1024
#define CFG_LOAD_ADDR 0x100000
#define CFG_LONGHELP
#define CFG_MAXARGS 16
#define CFG_MEMTEST_START 0x00040000
#define CFG_MEMTEST_END 0x00040100
#define CFG_PBSIZE 1024
#define CFG_PROMPT "=> "
/*
* Environment config - see memory map details above
*
* CFG_ENV_IS_IN_FLASH - The env variables are stored in flash
* CFG_ENV_ADDR - Address of the sector containing env vars
* CFG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
* CFG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR 0xFFFE0000
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_ADDR_REDUND 0xFFFE8000
#define CFG_ENV_SIZE_REDUND 0x1000
#define CFG_ENV_SECT_SIZE 0x8000
/*
* Initial RAM config
*
* Since the main system RAM is initialised very early, we place the INIT_RAM
* in the main system RAM just above the exception vectors. The contents are
* copied to top of RAM by the init code.
*
* CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect
* CFG_INIT_RAM_END - Size of Init RAM
* CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
* CFG_GBL_DATA_OFFSET - Start of global data, top of stack
*/
#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000)
#define CFG_INIT_RAM_END 0x4000
#define CFG_GBL_DATA_SIZE 128
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/*
* Initial BAT config
*
* BAT0 - System SDRAM
* BAT1 - LED's and Serial Port
* BAT2 - PCI Memory
* BAT3 - PCI I/O including Flash Memory
*/
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
#define CFG_DBAT0L CFG_IBAT0L
#define CFG_DBAT0U CFG_IBAT0U
#define CFG_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
/*
* Cache config
*
* CFG_CACHELINE_SIZE - Size of a cache line (CPU specific)
* CFG_L2 - L2 cache enabled if defined
* L2_INIT - L2 cache init flags
* L2_ENABLE - L2 cache enable flags
*/
#define CFG_CACHELINE_SIZE 32
#undef CFG_L2
#define L2_INIT 0
#define L2_ENABLE 0
/*
* Clocks config
*
* CFG_BUS_HZ - Bus clock frequency in Hz
* CFG_BUS_CLK - As above (?)
* CFG_HZ - Decrementer freq in Hz
*/
#define CFG_BUS_HZ CONFIG_BUS_CLK
#define CFG_BUS_CLK CONFIG_BUS_CLK
#define CFG_HZ 1000
/*
* Serial port config
*
* CFG_BAUDRATE_TABLE - List of valid baud rates
* CFG_NS16550 - Include the NS16550 driver
* CFG_NS16550_SERIAL - Include the serial (wrapper) driver
* CFG_NS16550_CLK - Frequency of reference clock
* CFG_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
* CFG_NS16550_COM1 - Base address of 1st serial port
*/
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_CLK 3686400
#define CFG_NS16550_REG_SIZE -8
#define CFG_NS16550_COM1 0x7C000000
/*
* PCI Config - Address Map B (CHRP)
*/
#define CFG_PCI_MEMORY_BUS 0x00000000
#define CFG_PCI_MEMORY_PHYS 0x00000000
#define CFG_PCI_MEMORY_SIZE 0x40000000
#define CFG_PCI_MEM_BUS 0x80000000
#define CFG_PCI_MEM_PHYS 0x80000000
#define CFG_PCI_MEM_SIZE 0x7D000000
#define CFG_ISA_MEM_BUS 0x00000000
#define CFG_ISA_MEM_PHYS 0xFD000000
#define CFG_ISA_MEM_SIZE 0x01000000
#define CFG_PCI_IO_BUS 0x00800000
#define CFG_PCI_IO_PHYS 0xFE800000
#define CFG_PCI_IO_SIZE 0x00400000
#define CFG_ISA_IO_BUS 0x00000000
#define CFG_ISA_IO_PHYS 0xFE000000
#define CFG_ISA_IO_SIZE 0x00800000
#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
#define CFG_ISA_IO CFG_ISA_IO_PHYS
#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
/*
* Extra init functions
*
* CFG_BOARD_ASM_INIT - Call assembly init code
*/
#define CFG_BOARD_ASM_INIT
/*
* Boot flags
*
* BOOTFLAG_COLD - Indicates a power-on boot
* BOOTFLAG_WARM - Indicates a software reset
*/
#define BOOTFLAG_COLD 0x01
#define BOOTFLAG_WARM 0x02
#endif /* __CONFIG_H */

28
include/configs/spieval.h
View File

@ -191,16 +191,6 @@
#undef CONFIG_BOOTARGS
#if defined (CONFIG_TQM5200_AA)
# define CONFIG_U_BOOT_SUFFIX "-AA\0"
#elif defined (CONFIG_TQM5200_AB)
# define CONFIG_U_BOOT_SUFFIX "-AB\0"
#elif defined (CONFIG_TQM5200_AC)
# define CONFIG_U_BOOT_SUFFIX "-AC\0"
#else
# define CONFIG_U_BOOT_SUFFIX "\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
@ -217,7 +207,7 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
"load=tftp 200000 ${u-boot}\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
@ -283,13 +273,6 @@
#endif
/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
CFG_I2C_SLAVE }
#elif defined (CONFIG_TQM5200_AC)
#define I2C_ADDR_LIST { CFG_I2C_SLAVE }
#endif
#if defined (CONFIG_MINIFAP)
#undef I2C_ADDR_LIST
#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
@ -478,13 +461,9 @@
* SRAM - Do not map below 2 GB in address space, because this area is used
* for SDRAM autosizing.
*/
#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF)
#if defined (CONFIG_CS_AUTOCONF)
#define CFG_CS2_START 0xE5000000
#ifdef CONFIG_TQM5200_AB
#define CFG_CS2_SIZE 0x80000 /* 512 kByte */
#else /* CONFIG_CS_AUTOCONF */
#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
#endif
#define CFG_CS2_CFG 0x0004D930
#endif
@ -492,8 +471,7 @@
* Grafic controller - Do not map below 2 GB in address space, because this
* area is used for SDRAM autosizing.
*/
#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \
defined (CONFIG_CS_AUTOCONF)
#if defined (CONFIG_CS_AUTOCONF)
#define SM501_FB_BASE 0xE0000000
#define CFG_CS1_START (SM501_FB_BASE)
#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */

6
include/configs/trab.h
View File

@ -165,7 +165,6 @@
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_FAT | \
CFG_CMD_JFFS2 | \
CFG_CMD_NFS | \
CFG_CMD_SNTP | \
CFG_CMD_USB )
@ -179,7 +178,6 @@
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_FAT | \
CFG_CMD_JFFS2 | \
CFG_CMD_NFS | \
CFG_CMD_SNTP | \
CFG_CMD_USB )
@ -389,10 +387,10 @@
#define MTDIDS_DEFAULT "nor0=0"
/* production flash layout */
#define MTDPARTS_DEFAULT "mtdparts=0:32k(Firmware1)ro," \
#define MTDPARTS_DEFAULT "mtdparts=0:16k(Firmware1)ro," \
"16k(Env1)," \
"16k(Env2)," \
"320k(Firmware2)ro," \
"336k(Firmware2)ro," \
"896k(Kernel)," \
"5376k(Root-FS)," \
"1408k(JFFS2)," \

56
include/configs/voiceblue.h
View File

@ -47,6 +47,8 @@
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*
* Physical Memory Map
*/
@ -94,7 +96,6 @@
#define CONFIG_ENV_OVERWRITE
#define CFG_JFFS_CUSTOM_PART /* see board/voiceblue/jffs2parts.c */
#endif
/*
@ -104,9 +105,11 @@
#ifdef VOICEBLUE_SMALL_FLASH
#define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)
#define CONFIG_STACKSIZE SZ_8K
#define PHYS_SDRAM_1_RESERVED 0
#else
#define CFG_MALLOC_LEN SZ_4M
#define CONFIG_STACKSIZE SZ_1M
#define PHYS_SDRAM_1_RESERVED (CFG_MONITOR_LEN + CFG_MALLOC_LEN + CONFIG_STACKSIZE)
#endif
/*
@ -174,6 +177,7 @@
#define CONFIG_BOOTCOMMAND "run nboot"
#define CONFIG_PREBOOT "run setup"
#define CONFIG_EXTRA_ENV_SETTINGS \
"silent=1\0" \
"ospart=0\0" \
"swapos=no\0" \
"setpart=" \
@ -185,15 +189,37 @@
"fi\0" \
"setup=setenv bootargs console=ttyS0,$baudrate " \
"mtdparts=$mtdparts\0" \
"nfsargs=run setpart; setenv bootargs $bootargs " \
"root=/dev/nfs ip=dhcp\0" \
"nfsargs=setenv bootargs $bootargs " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
"nfsroot=$rootpath root=/dev/nfs\0" \
"flashargs=run setpart; setenv bootargs $bootargs " \
"root=/dev/mtdblock$partition ro " \
"rootfstype=jffs2\0" \
"nboot=run nfsargs; bootp; tftp; bootm\0" \
"fboot=run flashargs; fsload /boot/uImage; bootm\0"
"initrdargs=setenv bootargs $bootargs " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
"fboot=run flashargs; fsload /boot/uImage; bootm\0" \
"iboot=bootp; run initrdargs; tftp; bootm\0" \
"nboot=bootp; run nfsargs; tftp; bootm\0"
#endif
#ifndef VOICEBLUE_SMALL_FLASH
#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
#if 1 /* feel free to disable for development */
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
#define CONFIG_AUTOBOOT_PROMPT "\nVoiceBlue Enterprise - booting...\n"
#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */
#endif
/*
* JFFS2 partitions (mtdparts command line support)
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=omapflash.0"
#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:128k(uboot),64k(env),64k(r_env),16256k(data1),-(data2)"
#endif /* VOICEBLUE_SMALL_FLASH */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@ -213,7 +239,7 @@
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START PHYS_SDRAM_1
#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - PHYS_SDRAM_1_RESERVED
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
@ -247,22 +273,4 @@
#define VOICEBLUE_LED_REG 0x04030000
/*
* JFFS2 partitions
*
*/
/* No command line, one static partition */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV "nor0"
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET 0x00040000
/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=voiceblue-0"
#define MTDPARTS_DEFAULT "mtdparts=voiceblue-0:128k(uboot),64k(env),64k(renv),-(jffs2)"
*/
#endif /* __CONFIG_H */

22
include/ns16550.h
View File

@ -7,6 +7,9 @@
* added prototypes for ns16550.c
* reduced no of com ports to 2
* modifications (c) Rob Taylor, Flying Pig Systems. 2000.
*
* added support for port on 64-bit bus
* by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
*/
#if (CFG_NS16550_REG_SIZE == 1)
@ -82,6 +85,25 @@ struct NS16550 {
int pad10:24;
#endif
} __attribute__ ((packed));
#elif (CFG_NS16550_REG_SIZE == -8)
struct NS16550 {
unsigned char rbr; /* 0 */
unsigned char pad0[7];
unsigned char ier; /* 1 */
unsigned char pad1[7];
unsigned char fcr; /* 2 */
unsigned char pad2[7];
unsigned char lcr; /* 3 */
unsigned char pad3[7];
unsigned char mcr; /* 4 */
unsigned char pad4[7];
unsigned char lsr; /* 5 */
unsigned char pad5[7];
unsigned char msr; /* 6 */
unsigned char pad6[7];
unsigned char scr; /* 7 */
unsigned char pad7[7];
} __attribute__ ((packed));
#else
#error "Please define NS16550 registers size."
#endif

2
include/serial.h
View File

@ -23,7 +23,7 @@ extern struct serial_device serial_scc_device;
extern struct serial_device * default_serial_console (void);
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP)
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#endif