ppc4xx: Netstal HCU5 board: added various fixes and POST
- Moved some common code to nestal/common/nm_bsp.c. - Added support for the vxWorks EDR. - Enable trace for Lauterbach, if present. - Added support for POST. - Stylistic cleanups (multi-line comments/ enforce 80 colomn width) Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
This commit is contained in:
Niklaus Giger
Stefan Roese
parent
4371090e5d
commit
efeff5382b
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@ -23,9 +23,10 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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vpath hcu_flash.c ../common
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vpath nm_bsp.c ../common
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# NOBJS : Netstal common objects
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NOBJS = hcu_flash.o
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NOBJS = hcu_flash.o nm_bsp.o
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COBJS = $(BOARD).o sdram.o
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SOBJS = init.o
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@ -10,9 +10,6 @@ TODO:
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- Fix RTS/CTS problem (HW?)
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CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after
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Switching to interrupt driven serial input mode
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- Make vxWorks start from u-boot. Possible reasons
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- Does vxWorks need an entry for the Machine Check interrupt like this
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tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ?
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Caveats:
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--------
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@ -1,5 +1,5 @@
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/*
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*(C) Copyright 2005-2007 Netstal Maschinen AG
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*(C) Copyright 2005-2008 Netstal Maschinen AG
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* Niklaus Giger (Niklaus.Giger@netstal.com)
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*
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* This source code is free software; you can redistribute it
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@ -21,13 +21,11 @@
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#include <common.h>
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#include <asm/processor.h>
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#include <ppc440.h>
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#include <asm/mmu.h>
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#include <net.h>
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#include <asm/io.h>
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#include "../common/nm.h"
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DECLARE_GLOBAL_DATA_PTR;
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void hcu_led_set(u32 value);
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extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
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#undef BOOTSTRAP_OPTION_A_ACTIVE
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@ -42,23 +40,10 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
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#define SDR0_ECID2 0x0082
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#define SDR0_ECID3 0x0083
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#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000)
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#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000)
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#define SYS_SLOT_ADDRESS (CFG_CPLD + 0x00400000)
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#define DEFAULT_ETH_ADDR "ethaddr"
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/* ethaddr for first or etha1ddr for second ethernet */
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enum {
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/* HW_GENERATION_HCU1 is no longer supported */
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HW_GENERATION_HCU2 = 0x10,
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HW_GENERATION_HCU3 = 0x10,
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HW_GENERATION_HCU4 = 0x20,
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HW_GENERATION_HCU5 = 0x30,
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HW_GENERATION_MCU = 0x08,
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HW_GENERATION_MCU20 = 0x0a,
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HW_GENERATION_MCU25 = 0x09,
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};
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#define HCU_DIGITAL_IO_REGISTER (CFG_CPLD + 0x0500000)
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#define HCU_SW_INSTALL_REQUESTED 0x10
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/*
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* This function is run very early, out of flash, and before devices are
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@ -72,7 +57,6 @@ enum {
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int board_early_init_f(void)
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{
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u32 reg;
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#ifdef BOOTSTRAP_OPTION_A_ACTIVE
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/* Booting with Bootstrap Option A
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@ -113,10 +97,9 @@ int board_early_init_f(void)
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mtdcr(ebccfga, xbcfg);
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mtdcr(ebccfgd, 0xb8400000);
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/*--------------------------------------------------------------------
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/*
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* Setup the GPIO pins
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*-------------------------------------------------------------------*/
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/* test-only: take GPIO init from pcs440ep ???? in config file */
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*/
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out32(GPIO0_OR, 0x00000000);
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out32(GPIO0_TCR, 0x7C2FF1CF);
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out32(GPIO0_OSRL, 0x40055000);
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@ -143,9 +126,9 @@ int board_early_init_f(void)
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out32(GPIO1_ISR3L, 0x00000000);
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out32(GPIO1_ISR3H, 0x00000000);
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/*--------------------------------------------------------------------
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
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@ -172,12 +155,6 @@ int board_early_init_f(void)
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mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */
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mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
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/* PCI arbiter enabled */
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mfsdr(sdr_pci0, reg);
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mtsdr(sdr_pci0, 0x80000000 | reg);
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pci_pre_init(0);
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/* setup BOOT FLASH */
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mtsdr(SDR0_CUST0, 0xC0082350);
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@ -192,33 +169,27 @@ int board_pre_init(void)
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#endif
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int sys_install_requested(void)
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{
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u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
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return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
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}
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int checkboard(void)
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{
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unsigned int j;
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u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
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u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
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u16 generation = *boardVersReg & 0xf0;
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u16 index = *boardVersReg & 0x0f;
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u16 generation = in_be16(boardVersReg) & 0xf0;
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u16 index = in_be16(boardVersReg) & 0x0f;
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u32 ecid0, ecid1, ecid2, ecid3;
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printf("Netstal Maschinen AG: ");
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if (generation == HW_GENERATION_HCU3)
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printf("HCU3: index %d", index);
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else if (generation == HW_GENERATION_HCU4)
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printf("HCU4: index %d", index);
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else if (generation == HW_GENERATION_HCU5)
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printf("HCU5: index %d", index);
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printf(" HW 0x%02x\n", *hwVersReg & 0xff);
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nm_show_print(generation, index, in_be16(hwVersReg) & 0xff);
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mfsdr(SDR0_ECID0, ecid0);
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mfsdr(SDR0_ECID1, ecid1);
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mfsdr(SDR0_ECID2, ecid2);
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mfsdr(SDR0_ECID3, ecid3);
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printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
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for (j = 0;j < 6; j++) {
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hcu_led_set(1 << j);
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udelay(200 * 1000);
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}
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return 0;
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}
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@ -228,97 +199,47 @@ u32 hcu_led_get(void)
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return in16(SYS_IO_ADDRESS) & 0x3f;
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}
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/*---------------------------------------------------------------------------+
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/*
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* hcu_led_set value to be placed into the LEDs (max 6 bit)
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*---------------------------------------------------------------------------*/
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*/
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void hcu_led_set(u32 value)
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{
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out16(SYS_IO_ADDRESS, value);
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}
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/*---------------------------------------------------------------------------+
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/*
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* get_serial_number
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*---------------------------------------------------------------------------*/
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static u32 get_serial_number(void)
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*/
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u32 get_serial_number(void)
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{
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u32 *serial = (u32 *)CFG_FLASH_BASE;
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if (*serial == 0xffffffff)
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if (in_be32(serial) == 0xffffffff)
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return 0;
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return *serial;
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return in_be32(serial);
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}
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/*---------------------------------------------------------------------------+
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/*
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* hcu_get_slot
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*---------------------------------------------------------------------------*/
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*/
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u32 hcu_get_slot(void)
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{
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u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
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return (*slot) & 0x7f;
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return in_be16(slot) & 0x7f;
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}
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/*---------------------------------------------------------------------------+
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/*
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* misc_init_r.
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*---------------------------------------------------------------------------*/
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*/
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int misc_init_r(void)
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{
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char *s = getenv(DEFAULT_ETH_ADDR);
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char *e;
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int i;
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u32 serial = get_serial_number();
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unsigned long usb2d0cr = 0;
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unsigned long usb2phy0cr, usb2h0cr = 0;
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unsigned long sdr0_pfc1;
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for (i = 0; i < 6; ++i) {
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gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
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if (s)
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s = (*e) ? e + 1 : e;
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}
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if (gd->bd->bi_enetaddr[3] == 0 &&
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gd->bd->bi_enetaddr[4] == 0 &&
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gd->bd->bi_enetaddr[5] == 0) {
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char ethaddr[22];
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/* Must be in sync with CONFIG_ETHADDR */
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gd->bd->bi_enetaddr[0] = 0x00;
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gd->bd->bi_enetaddr[1] = 0x60;
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gd->bd->bi_enetaddr[2] = 0x13;
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gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
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gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
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gd->bd->bi_enetaddr[5] = hcu_get_slot();
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sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
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gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
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gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
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gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
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printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
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ethaddr, serial);
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setenv(DEFAULT_ETH_ADDR, ethaddr);
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}
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/* IP-Adress update */
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{
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IPaddr_t ipaddr;
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char *ipstring;
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ipstring = getenv("ipaddr");
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if (ipstring == 0)
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ipaddr = string_to_ip("172.25.1.99");
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else
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ipaddr = string_to_ip(ipstring);
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if ((ipaddr & 0xff) != (32 + hcu_get_slot())) {
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char tmp[22];
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ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot();
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ip_to_string (ipaddr, tmp);
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printf("%s: enforce %s\n", __FUNCTION__, tmp);
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setenv("ipaddr", tmp);
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}
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}
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#ifdef CFG_ENV_IS_IN_FLASH
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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@ -326,11 +247,13 @@ int misc_init_r(void)
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0xffffffff,
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&flash_info[0]);
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#ifdef CFG_ENV_ADDR_REDUND
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/* Env protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR_REDUND,
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CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
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&flash_info[0]);
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#endif
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#endif
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/*
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@ -355,7 +278,8 @@ int misc_init_r(void)
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
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/* An 8-bit/60MHz interface is the only possible alternative
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when connecting the Device to the PHY */
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* when connecting the Device to the PHY
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*/
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usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
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usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
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@ -376,14 +300,37 @@ int misc_init_r(void)
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mtsdr(SDR0_SRST1, 0x00000000);
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udelay(1000);
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mtsdr(SDR0_SRST0, 0x00000000);
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printf("USB: Host(int phy) Device(ext phy)\n");
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common_misc_init_r();
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set_params_for_sw_install( sys_install_requested(), "hcu5" );
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/* We cannot easily enable trace before, as there are other
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* routines messing around with sdr0_pfc1. And I do not need it.
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*/
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if (mfspr(dbcr0) & 0x80000000) {
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/* External debugger alive
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* enable trace facilty for Lauterback
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* CCR0[DAPUIB]=0 Enable broadcast of instruction data
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* to auxiliary processor interface
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* CCR0[DTB]=0 Enable broadcast of trace information
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* SDR0_PFC0[TRE] Trace signals are enabled instead of
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* GPIO49-63
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*/
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mtspr(ccr0, mfspr(ccr0) &~ 0x00108000);
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mtsdr(SDR0_PFC0, sdr0_pfc1 | 0x00000100);
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}
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return 0;
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}
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#ifdef CONFIG_PCI
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int board_with_pci(void)
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{
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u32 reg;
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#if defined(CONFIG_PCI)
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/*************************************************************************
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mfsdr(sdr_pci0, reg);
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return (reg & SDR0_XCR_PAE_MASK);
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}
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/*
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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@ -394,81 +341,64 @@ int misc_init_r(void)
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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*/
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int pci_pre_init(struct pci_controller *hose)
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{
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unsigned long addr;
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/*-------------------------------------------------------------------+
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* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
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* Workaround: Disable write pipelining to DDR SDRAM by setting
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* PLB0_ACR[WRP] = 0.
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*-------------------------------------------------------------------*/
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if (!board_with_pci()) { return 0; }
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/*-------------------------------------------------------------------+
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| Set priority for all PLB3 devices to 0.
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| Set PLB3 arbiter to fair mode.
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+-------------------------------------------------------------------*/
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/*
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* Set priority for all PLB3 devices to 0.
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* Set PLB3 arbiter to fair mode.
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*/
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mfsdr(sdr_amp1, addr);
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mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(plb3_acr);
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/* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
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mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
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/*-------------------------------------------------------------------+
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| Set priority for all PLB4 devices to 0.
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+-------------------------------------------------------------------*/
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/*
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* Set priority for all PLB4 devices to 0.
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*/
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mfsdr(sdr_amp0, addr);
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mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
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/* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
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mtdcr(plb4_acr, addr); /* Sequoia */
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/*-------------------------------------------------------------------+
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| Set Nebula PLB4 arbiter to fair mode.
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+-------------------------------------------------------------------*/
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/* Segment0 */
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addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
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addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
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addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
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/* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */
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addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */
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/* mtdcr(plb0_acr, addr); */ /* Sequoia */
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/*
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* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
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* Workaround: Disable write pipelining to DDR SDRAM by setting
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* PLB0_ACR[WRP] = 0.
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*/
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mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
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/* Segment1 */
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addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
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addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
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addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
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addr = (addr & ~plb1_acr_wrp_mask) ;
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/* mtdcr(plb1_acr, addr); */ /* Sequoia */
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mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
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return 1;
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return board_with_pci();
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}
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/*************************************************************************
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/*
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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*/
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void pci_target_init(struct pci_controller *hose)
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{
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/*-------------------------------------------------------------+
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if (!board_with_pci()) { return; }
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/*
|
||||
* Set up Direct MMIO registers
|
||||
*-------------------------------------------------------------*/
|
||||
/*-------------------------------------------------------------+
|
||||
| PowerPC440EPX PCI Master configuration.
|
||||
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
|
||||
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
|
||||
| 0xA0000000-0xDFFFFFFF
|
||||
| Use byte reversed out routines to handle endianess.
|
||||
| Make this region non-prefetchable.
|
||||
+-------------------------------------------------------------*/
|
||||
*
|
||||
* PowerPC440EPX PCI Master configuration.
|
||||
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
|
||||
* PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
|
||||
* 0xA0000000-0xDFFFFFFF
|
||||
* Use byte reversed out routines to handle endianess.
|
||||
* Make this region non-prefetchable.
|
||||
*/
|
||||
/* PMM0 Mask/Attribute - disabled b4 setting */
|
||||
out32r(PCIX0_PMM0MA, 0x00000000);
|
||||
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
|
||||
|
|
@ -492,9 +422,9 @@ void pci_target_init(struct pci_controller *hose)
|
|||
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
|
||||
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
|
||||
|
||||
/*------------------------------------------------------------------+
|
||||
/*
|
||||
* Set up Configuration registers
|
||||
*------------------------------------------------------------------*/
|
||||
*/
|
||||
|
||||
/* Program the board's subsystem id/vendor id */
|
||||
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
|
|
@ -513,26 +443,27 @@ void pci_target_init(struct pci_controller *hose)
|
|||
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
/*
|
||||
* pci_master_init
|
||||
*
|
||||
************************************************************************/
|
||||
*/
|
||||
void pci_master_init(struct pci_controller *hose)
|
||||
{
|
||||
unsigned short temp_short;
|
||||
if (!board_with_pci()) { return; }
|
||||
|
||||
/*---------------------------------------------------------------+
|
||||
| Write the PowerPC440 EP PCI Configuration regs.
|
||||
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
|
||||
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
|
||||
+--------------------------------------------------------------*/
|
||||
/*---------------------------------------------------------------
|
||||
* Write the PowerPC440 EP PCI Configuration regs.
|
||||
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
|
||||
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
|
||||
*--------------------------------------------------------------*/
|
||||
pci_read_config_word(0, PCI_COMMAND, &temp_short);
|
||||
pci_write_config_word(0, PCI_COMMAND,
|
||||
temp_short | PCI_COMMAND_MASTER |
|
||||
PCI_COMMAND_MEMORY);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
/*
|
||||
* is_pci_host
|
||||
*
|
||||
* This routine is called to determine if a pci scan should be
|
||||
|
|
@ -545,10 +476,31 @@ void pci_master_init(struct pci_controller *hose)
|
|||
*
|
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
*/
|
||||
int is_pci_host(struct pci_controller *hose)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
#if defined(CONFIG_POST)
|
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||
* Called from board_init_f().
|
||||
*/
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
return 0; /* No hotkeys supported */
|
||||
}
|
||||
#endif /* CONFIG_POST */
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 val[4];
|
||||
int rc;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
}
|
||||
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
||||
|
|
|
|||
|
|
@ -39,41 +39,68 @@
|
|||
tlbtab:
|
||||
tlbtab_start
|
||||
|
||||
/* vxWorks needs this entry for the Machine Check interrupt, */
|
||||
/* tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */
|
||||
/* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
|
||||
tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
/* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
|
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0,
|
||||
AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
/* TLB#2: TLB-entry for EBC */
|
||||
tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
|
||||
/*
|
||||
* BOOT_CS (FLASH) must be second. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
* TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be
|
||||
* off to use the speed up boot process. It is patched after relocation
|
||||
* to enable SA_I
|
||||
*/
|
||||
tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
|
||||
tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1,
|
||||
AC_R|AC_W|AC_X|SA_G)
|
||||
|
||||
/* TLB-entry for PCI Memory */
|
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform.
|
||||
* They are dynamically generated in the SPD DDR(2) detection
|
||||
* routine.
|
||||
*/
|
||||
|
||||
/* TLB-entry for EBC (CFG_CPLD) */
|
||||
/* tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */
|
||||
/* CAN */
|
||||
tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
/* IMC + CPLD */
|
||||
tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
/* IMC-Fast */
|
||||
tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
/* TLB#4: */
|
||||
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1,
|
||||
AC_R|AC_W|SA_G|SA_I )
|
||||
/* TLB#5: */
|
||||
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1,
|
||||
AC_R|AC_W|SA_G|SA_I )
|
||||
/* TLB#6: */
|
||||
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1,
|
||||
AC_R|AC_W|SA_G|SA_I )
|
||||
|
||||
/* TLB-entry for Internal Registers & OCM */
|
||||
tlbentry( CFG_PCI_BASE, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
|
||||
/* TLB#7: */
|
||||
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,
|
||||
AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
/*TLB-entry PCI registers*/
|
||||
/* TLB#8: */
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
/* TLB-entry for peripherals */
|
||||
/* TLB#9: */
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
|
||||
/* TLB for SDRAM will be added by initdram (sdram.c) */
|
||||
/* CAN */
|
||||
/* TLB#10: */
|
||||
tlbentry( CFG_CS_1, SZ_1K, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
/* TLB#11: CPLD and IMC-Standard 32 MB */
|
||||
tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
/* TLB#12: */
|
||||
tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1,
|
||||
AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
/* IMC-Fast 32 MB */
|
||||
/* TLB#13: */
|
||||
tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
/* TLB#14: */
|
||||
tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3, 1,
|
||||
AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
tlbtab_end
|
||||
|
|
|
|||
|
|
@ -62,11 +62,8 @@ void dflush(void);
|
|||
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */
|
||||
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
|
||||
#ifdef CFG_ENABLE_SDRAM_CACHE
|
||||
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on DDR2 */
|
||||
#else
|
||||
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */
|
||||
#endif
|
||||
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
|
||||
/* disable caching on DDR2 */
|
||||
|
||||
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
|
||||
|
||||
|
|
@ -157,38 +154,36 @@ static void blank_string(int size)
|
|||
/*---------------------------------------------------------------------------+
|
||||
* program_ecc.
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void program_ecc(unsigned long start_address, unsigned long num_bytes,
|
||||
unsigned long tlb_word2_i_value)
|
||||
static void program_ecc(unsigned long start_address, unsigned long num_bytes)
|
||||
{
|
||||
unsigned long current_address= start_address;
|
||||
int loopi = 0;
|
||||
u32 val;
|
||||
|
||||
char str[] = "ECC generation -";
|
||||
char slash[] = "\\|/-\\|/-";
|
||||
#if defined(CONFIG_PRAM)
|
||||
u32 *magic;
|
||||
|
||||
/* Check whether vxWorks is using EDR logging, if yes zero */
|
||||
/* also PostMortem and user reserved memory */
|
||||
magic= in_be32(start_address + num_bytes -
|
||||
(CONFIG_PRAM*1024) + sizeof(u32));
|
||||
|
||||
debug("\n%s: CONFIG_PRAM %d kB magic 0x%x 0x%p -> 0x%x\n", __FUNCTION__,
|
||||
CONFIG_PRAM,
|
||||
start_address + num_bytes - (CONFIG_PRAM*1024) + sizeof(u32),
|
||||
magic, in_be32(magic));
|
||||
if (in_be32(magic) == 0xbeefbabe)
|
||||
num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
|
||||
#endif
|
||||
|
||||
|
||||
sync();
|
||||
eieio();
|
||||
|
||||
puts(str);
|
||||
|
||||
if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
|
||||
/* ECC bit set method for non-cached memory */
|
||||
/* This takes various seconds */
|
||||
for(current_address = 0; current_address < num_bytes;
|
||||
current_address += sizeof(u32)) {
|
||||
*(u32 *)current_address = 0;
|
||||
if ((current_address % (2 << 20)) == 0) {
|
||||
putc('\b');
|
||||
putc(slash[loopi++ % 8]);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* ECC bit set method for cached memory */
|
||||
/* Fast method, no noticeable delay */
|
||||
dcbz_area(start_address, num_bytes);
|
||||
dflush();
|
||||
}
|
||||
/* ECC bit set method for cached memory */
|
||||
/* Fast method, no noticeable delay */
|
||||
dcbz_area(start_address, num_bytes);
|
||||
dflush();
|
||||
blank_string(strlen(str));
|
||||
|
||||
/* Clear error status */
|
||||
|
|
@ -196,7 +191,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes,
|
|||
mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
|
||||
|
||||
/*
|
||||
* Clear possible errors
|
||||
* Clear possible ECC errors
|
||||
* If not done, then we could get an interrupt later on when
|
||||
* exceptions are enabled.
|
||||
*/
|
||||
|
|
@ -212,6 +207,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes,
|
|||
|
||||
#endif
|
||||
|
||||
|
||||
/***********************************************************************
|
||||
*
|
||||
* initdram -- 440EPx's DDR controller is a DENALI Core
|
||||
|
|
@ -233,23 +229,22 @@ long int initdram (int board_type)
|
|||
mtsdram(DDR0_04, 0x0A020200);
|
||||
mtsdram(DDR0_05, 0x02020307);
|
||||
switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) {
|
||||
case 0:
|
||||
dram_size = 128 * 1024 * 1024 ;
|
||||
mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */
|
||||
mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */
|
||||
mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */
|
||||
break;
|
||||
case 1:
|
||||
dram_size = 256 * 1024 * 1024 ;
|
||||
mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */
|
||||
mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */
|
||||
mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */
|
||||
break;
|
||||
case 0:
|
||||
default:
|
||||
sdram_panic(INVALID_HW_CONFIG);
|
||||
dram_size = 128 * 1024 * 1024 ;
|
||||
mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */
|
||||
mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */
|
||||
mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */
|
||||
break;
|
||||
}
|
||||
mtsdram(DDR0_07, 0x00090100);
|
||||
|
||||
/*
|
||||
* TCPD=200 cycles of clock input is required to lock the DLL.
|
||||
* CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
|
||||
|
|
@ -288,7 +283,7 @@ long int initdram (int board_type)
|
|||
* Program tlb entries for this size (dynamic)
|
||||
*/
|
||||
remove_tlb(CFG_SDRAM_BASE, 256 << 20);
|
||||
program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
|
||||
program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
|
||||
|
||||
/*
|
||||
* Setup 2nd TLB with same physical address but different virtual
|
||||
|
|
@ -296,13 +291,11 @@ long int initdram (int board_type)
|
|||
*/
|
||||
program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
|
||||
|
||||
/* Diminish RAM to initialize */
|
||||
dram_size = dram_size - 32 ;
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
/*
|
||||
* If ECC is enabled, initialize the parity bits.
|
||||
*/
|
||||
program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0);
|
||||
program_ecc(CFG_DDR_CACHED_ADDR, dram_size);
|
||||
#endif
|
||||
|
||||
return (dram_size);
|
||||
|
|
|
|||
Loading…
Reference in New Issue