PXA: cradle: Fix for reloc
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
This commit is contained in:
Marek Vasut
parent
d94bbbeb16
commit
eb0e11bd2a
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@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := cradle.o flash.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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rm -f $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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@ -1,2 +0,0 @@
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CONFIG_SYS_TEXT_BASE = 0xa0f80000
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#CONFIG_SYS_TEXT_BASE = 0
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@ -185,6 +185,10 @@ int
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board_init (void)
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/**********************************************************/
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{
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/* We have RAM, disable cache */
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dcache_disable();
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icache_disable();
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led_code (0xf, YELLOW);
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/* arch number of HHP Cradle */
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@ -206,24 +210,18 @@ board_init (void)
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return 1;
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}
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int
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/**********************************************************/
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dram_init (void)
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/**********************************************************/
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extern void pxa_dram_init(void);
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int dram_init(void)
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{
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pxa_dram_init();
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
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gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
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gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
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gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
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return (PHYS_SDRAM_1_SIZE +
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PHYS_SDRAM_2_SIZE +
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PHYS_SDRAM_3_SIZE +
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PHYS_SDRAM_4_SIZE );
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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}
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#ifdef CONFIG_CMD_NET
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@ -1,515 +0,0 @@
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/*
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* Most of this taken from Redboot hal_platform_setup.h with cleanup
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/pxa-regs.h>
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DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
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/* wait for coprocessor write complete */
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.macro CPWAIT reg
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mrc p15,0,\reg,c2,c0,0
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mov \reg,\reg
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sub pc,pc,#4
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.endm
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.macro SET_LED val
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ldr r6, =GPCR2
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ldr r7, =0
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str r7, [r6]
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ldr r6, =GPSR2
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ldr r7, =\val
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str r7, [r6]
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.endm
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.globl lowlevel_init
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lowlevel_init:
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mov r10, lr
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/* Set up GPIO pins first */
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ldr r0, =GPSR0
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ldr r1, =CONFIG_SYS_GPSR0_VAL
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str r1, [r0]
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ldr r0, =GPSR1
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ldr r1, =CONFIG_SYS_GPSR1_VAL
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str r1, [r0]
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ldr r0, =GPSR2
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ldr r1, =CONFIG_SYS_GPSR2_VAL
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str r1, [r0]
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ldr r0, =GPCR0
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ldr r1, =CONFIG_SYS_GPCR0_VAL
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str r1, [r0]
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ldr r0, =GPCR1
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ldr r1, =CONFIG_SYS_GPCR1_VAL
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str r1, [r0]
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ldr r0, =GPCR2
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ldr r1, =CONFIG_SYS_GPCR2_VAL
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str r1, [r0]
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ldr r0, =GRER0
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ldr r1, =CONFIG_SYS_GRER0_VAL
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str r1, [r0]
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ldr r0, =GRER1
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ldr r1, =CONFIG_SYS_GRER1_VAL
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str r1, [r0]
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ldr r0, =GRER2
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ldr r1, =CONFIG_SYS_GRER2_VAL
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str r1, [r0]
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ldr r0, =GFER0
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ldr r1, =CONFIG_SYS_GFER0_VAL
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str r1, [r0]
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ldr r0, =GFER1
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ldr r1, =CONFIG_SYS_GFER1_VAL
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str r1, [r0]
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ldr r0, =GFER2
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ldr r1, =CONFIG_SYS_GFER2_VAL
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str r1, [r0]
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ldr r0, =GPDR0
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ldr r1, =CONFIG_SYS_GPDR0_VAL
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str r1, [r0]
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ldr r0, =GPDR1
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ldr r1, =CONFIG_SYS_GPDR1_VAL
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str r1, [r0]
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ldr r0, =GPDR2
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ldr r1, =CONFIG_SYS_GPDR2_VAL
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str r1, [r0]
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ldr r0, =GAFR0_L
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ldr r1, =CONFIG_SYS_GAFR0_L_VAL
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str r1, [r0]
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ldr r0, =GAFR0_U
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ldr r1, =CONFIG_SYS_GAFR0_U_VAL
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str r1, [r0]
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ldr r0, =GAFR1_L
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ldr r1, =CONFIG_SYS_GAFR1_L_VAL
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str r1, [r0]
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ldr r0, =GAFR1_U
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ldr r1, =CONFIG_SYS_GAFR1_U_VAL
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str r1, [r0]
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ldr r0, =GAFR2_L
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ldr r1, =CONFIG_SYS_GAFR2_L_VAL
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str r1, [r0]
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ldr r0, =GAFR2_U
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ldr r1, =CONFIG_SYS_GAFR2_U_VAL
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str r1, [r0]
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/* enable GPIO pins */
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ldr r0, =PSSR
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ldr r1, =CONFIG_SYS_PSSR_VAL
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str r1, [r0]
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SET_LED 1
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ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */
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ldr r2, =CONFIG_SYS_MSC1_VAL /* high - bank 3 Ethernet Controller */
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str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */
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ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */
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/*********************************************************************
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Initlialize Memory Controller
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See PXA250 Operating System Developer's Guide
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pause for 200 uSecs- allow internal clocks to settle
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*Note: only need this if hard reset... doing it anyway for now
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*/
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@ Step 1
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@ ---- Wait 200 usec
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ldr r3, =OSCR @ reset the OS Timer Count to zero
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mov r2, #0
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str r2, [r3]
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ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
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1:
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ldr r2, [r3]
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cmp r4, r2
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bgt 1b
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SET_LED 2
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mem_init:
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@ get memory controller base address
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ldr r1, =MEMC_BASE
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@****************************************************************************
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@ Step 2
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@
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@ Step 2a
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@ write msc0, read back to ensure data latches
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@
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ldr r2, =CONFIG_SYS_MSC0_VAL
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str r2, [r1, #MSC0_OFFSET]
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ldr r2, [r1, #MSC0_OFFSET]
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@ write msc1
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ldr r2, =CONFIG_SYS_MSC1_VAL
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str r2, [r1, #MSC1_OFFSET]
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ldr r2, [r1, #MSC1_OFFSET]
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@ write msc2
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ldr r2, =CONFIG_SYS_MSC2_VAL
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str r2, [r1, #MSC2_OFFSET]
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ldr r2, [r1, #MSC2_OFFSET]
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@ Step 2b
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@ write mecr
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ldr r2, =CONFIG_SYS_MECR_VAL
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str r2, [r1, #MECR_OFFSET]
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@ write mcmem0
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ldr r2, =CONFIG_SYS_MCMEM0_VAL
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str r2, [r1, #MCMEM0_OFFSET]
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@ write mcmem1
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ldr r2, =CONFIG_SYS_MCMEM1_VAL
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str r2, [r1, #MCMEM1_OFFSET]
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@ write mcatt0
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ldr r2, =CONFIG_SYS_MCATT0_VAL
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str r2, [r1, #MCATT0_OFFSET]
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@ write mcatt1
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ldr r2, =CONFIG_SYS_MCATT1_VAL
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str r2, [r1, #MCATT1_OFFSET]
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@ write mcio0
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ldr r2, =CONFIG_SYS_MCIO0_VAL
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str r2, [r1, #MCIO0_OFFSET]
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@ write mcio1
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ldr r2, =CONFIG_SYS_MCIO1_VAL
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str r2, [r1, #MCIO1_OFFSET]
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/*SET_LED 3 */
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@ Step 2c
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@ fly-by-dma is defeatured on this part
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@ write flycnfg
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@ldr r2, =CONFIG_SYS_FLYCNFG_VAL
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@str r2, [r1, #FLYCNFG_OFFSET]
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/* FIXME Does this sequence really make sense */
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#ifdef REDBOOT_WAY
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@ Step 2d
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@ get the mdrefr settings
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ldr r3, =CONFIG_SYS_MDREFR_VAL
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@ extract DRI field (we need a valid DRI field)
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@
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ldr r2, =0xFFF
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@ valid DRI field in r3
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@
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and r3, r3, r2
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@ get the reset state of MDREFR
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@
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ldr r4, [r1, #MDREFR_OFFSET]
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@ clear the DRI field
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@
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bic r4, r4, r2
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@ insert the valid DRI field loaded above
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@
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orr r4, r4, r3
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@ write back mdrefr
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@
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str r4, [r1, #MDREFR_OFFSET]
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@ *Note: preserve the mdrefr value in r4 *
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/*SET_LED 4 */
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@****************************************************************************
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@ Step 3
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@
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@ NO SRAM
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mov pc, r10
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@****************************************************************************
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@ Step 4
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@
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@ Assumes previous mdrefr value in r4, if not then read current mdrefr
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@ clear the free-running clock bits
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@ (clear K0Free, K1Free, K2Free
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@
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bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
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@ set K0RUN for CPLD clock
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@
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orr r4, r4, #0x00002000
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@ set K1RUN if bank 0 installed
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@
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orr r4, r4, #0x00010000
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@ write back mdrefr
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@
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str r4, [r1, #MDREFR_OFFSET]
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ldr r4, [r1, #MDREFR_OFFSET]
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@ deassert SLFRSH
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@
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bic r4, r4, #0x00400000
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@ write back mdrefr
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@
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str r4, [r1, #MDREFR_OFFSET]
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@ assert E1PIN
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@
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orr r4, r4, #0x00008000
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@ write back mdrefr
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@
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str r4, [r1, #MDREFR_OFFSET]
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ldr r4, [r1, #MDREFR_OFFSET]
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nop
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nop
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#else
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@ Step 2d
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@ get the mdrefr settings
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ldr r3, =CONFIG_SYS_MDREFR_VAL
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@ write back mdrefr
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@
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str r4, [r1, #MDREFR_OFFSET]
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@ Step 4
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@ set K0RUN for CPLD clock
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@
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orr r4, r4, #0x00002000
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@ set K1RUN for bank 0
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@
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orr r4, r4, #0x00010000
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@ write back mdrefr
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@
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str r4, [r1, #MDREFR_OFFSET]
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ldr r4, [r1, #MDREFR_OFFSET]
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@ deassert SLFRSH
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@
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bic r4, r4, #0x00400000
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@ write back mdrefr
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@
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str r4, [r1, #MDREFR_OFFSET]
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@ assert E1PIN
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@
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orr r4, r4, #0x00008000
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@ write back mdrefr
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@
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str r4, [r1, #MDREFR_OFFSET]
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ldr r4, [r1, #MDREFR_OFFSET]
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nop
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nop
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#endif
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@ Step 4d
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@ fetch platform value of mdcnfg
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@
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ldr r2, =CONFIG_SYS_MDCNFG_VAL
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@ disable all sdram banks
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@
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bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
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bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
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@ program banks 0/1 for bus width
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@
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bic r2, r2, #MDCNFG_DWID0 @0=32-bit
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@ write initial value of mdcnfg, w/o enabling sdram banks
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@
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str r2, [r1, #MDCNFG_OFFSET]
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@ Step 4e
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@ pause for 200 uSecs
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@
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ldr r3, =OSCR @ reset the OS Timer Count to zero
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mov r2, #0
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str r2, [r3]
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ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
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1:
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ldr r2, [r3]
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cmp r4, r2
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bgt 1b
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/*SET_LED 5 */
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/* Why is this here??? */
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mov r0, #0x78 @turn everything off
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mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
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@ Step 4f
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@ Access memory *not yet enabled* for CBR refresh cycles (8)
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@ - CBR is generated for all banks
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ldr r2, =CONFIG_SYS_DRAM_BASE
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str r2, [r2]
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str r2, [r2]
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str r2, [r2]
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str r2, [r2]
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str r2, [r2]
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str r2, [r2]
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str r2, [r2]
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str r2, [r2]
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@ Step 4g
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@get memory controller base address
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@
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ldr r1, =MEMC_BASE
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@fetch current mdcnfg value
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@
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ldr r3, [r1, #MDCNFG_OFFSET]
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@enable sdram bank 0 if installed (must do for any populated bank)
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@
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orr r3, r3, #MDCNFG_DE0
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@write back mdcnfg, enabling the sdram bank(s)
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@
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str r3, [r1, #MDCNFG_OFFSET]
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@ Step 4h
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@ write mdmrs
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@
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ldr r2, =CONFIG_SYS_MDMRS_VAL
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str r2, [r1, #MDMRS_OFFSET]
|
||||
|
||||
@ Done Memory Init
|
||||
|
||||
/*SET_LED 6 */
|
||||
|
||||
@********************************************************************
|
||||
@ Disable (mask) all interrupts at the interrupt controller
|
||||
@
|
||||
|
||||
@ clear the interrupt level register (use IRQ, not FIQ)
|
||||
@
|
||||
mov r1, #0
|
||||
ldr r2, =ICLR
|
||||
str r1, [r2]
|
||||
|
||||
@ Set interrupt mask register
|
||||
@
|
||||
ldr r1, =CONFIG_SYS_ICMR_VAL
|
||||
ldr r2, =ICMR
|
||||
str r1, [r2]
|
||||
|
||||
@ ********************************************************************
|
||||
@ Disable the peripheral clocks, and set the core clock
|
||||
@
|
||||
|
||||
@ Turn Off ALL on-chip peripheral clocks for re-configuration
|
||||
@
|
||||
ldr r1, =CKEN
|
||||
mov r2, #0
|
||||
str r2, [r1]
|
||||
|
||||
@ set core clocks
|
||||
@
|
||||
ldr r2, =CONFIG_SYS_CCCR_VAL
|
||||
ldr r1, =CCCR
|
||||
str r2, [r1]
|
||||
|
||||
#ifdef ENABLE32KHZ
|
||||
@ enable the 32Khz oscillator for RTC and PowerManager
|
||||
@
|
||||
ldr r1, =OSCC
|
||||
mov r2, #OSCC_OON
|
||||
str r2, [r1]
|
||||
|
||||
@ NOTE: spin here until OSCC.OOK get set,
|
||||
@ meaning the PLL has settled.
|
||||
@
|
||||
60:
|
||||
ldr r2, [r1]
|
||||
ands r2, r2, #1
|
||||
beq 60b
|
||||
#endif
|
||||
|
||||
@ Turn on needed clocks
|
||||
@
|
||||
ldr r1, =CKEN
|
||||
ldr r2, =CONFIG_SYS_CKEN_VAL
|
||||
str r2, [r1]
|
||||
|
||||
/*SET_LED 7 */
|
||||
|
||||
/* Is this needed???? */
|
||||
#define NODEBUG
|
||||
#ifdef NODEBUG
|
||||
/*Disable software and data breakpoints */
|
||||
mov r0,#0
|
||||
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
|
||||
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
|
||||
mcr p15,0,r0,c14,c4,0 /* dbcon */
|
||||
|
||||
/*Enable all debug functionality */
|
||||
mov r0,#0x80000000
|
||||
mcr p14,0,r0,c10,c0,0 /* dcsr */
|
||||
|
||||
#endif
|
||||
|
||||
/*SET_LED 8 */
|
||||
|
||||
mov pc, r10
|
||||
|
||||
@ End lowlevel_init
|
||||
|
|
@ -39,7 +39,7 @@
|
|||
|
||||
/* we will never enable dcache, because we have to setup MMU first */
|
||||
#define CONFIG_SYS_NO_DCACHE
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
|
|
@ -126,15 +126,9 @@
|
|||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */
|
||||
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
|
||||
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
|
||||
#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
|
||||
#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
|
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
|
||||
|
|
@ -289,9 +283,9 @@
|
|||
* Clocks, power control and interrupts
|
||||
*/
|
||||
#define CONFIG_SYS_PSSR_VAL 0x00000020
|
||||
#define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
|
||||
#define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
|
||||
#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
|
||||
#define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */
|
||||
#define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */
|
||||
#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
|
||||
|
||||
/* FIXME
|
||||
*
|
||||
|
|
@ -319,6 +313,8 @@
|
|||
#define CONFIG_SYS_MDMRS_VAL 0x00000000
|
||||
#define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */
|
||||
#endif
|
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
|
||||
#define CONFIG_SYS_SXCNFG_VAL 0x00000000
|
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
|
||||
|
|
|
|||
|
|
@ -458,6 +458,9 @@
|
|||
|
||||
#define CONFIG_SYS_PSSR_VAL 0x20
|
||||
|
||||
#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
|
||||
#define CONFIG_SYS_CKEN 0x0
|
||||
|
||||
/*
|
||||
* Memory settings
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue