Merge with /home/sr/git/u-boot
This commit is contained in:
Wolfgang Denk
commit
e6b6d16de7
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@ -2,6 +2,13 @@
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Changes for U-Boot 1.1.4:
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======================================================================
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* Changes to Yellowstone & Yosemite 440EP/GR eval boards:
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- Changed GPIO setup to enable another address line in order to
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address 64M of FLASH.
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- Added function sdram_tr1_set to auto calculate the tr1 value for
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the DDR.
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Patch by Steven Blakeslee, 12 Dec 2005
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* MPC5200: Set PCI retry counter to 0 = infinite retry;
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The default of 255 is too short for slow devices.
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Patch by Martin Nykodym, 12 Dec 2005
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@ -59,10 +59,10 @@ int board_early_init_f(void)
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* Setup the GPIO pins
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*-------------------------------------------------------------------*/
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/*CPLD cs */
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/*setup Address lines for flash sizes larger than 16Meg. */
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out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
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/*setup Address lines for flash size 64Meg. */
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out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
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/*setup emac */
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
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@ -129,7 +129,7 @@ int board_early_init_f(void)
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#endif
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/*get rid of flash write protect */
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*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
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*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
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return 0;
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}
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@ -207,9 +207,85 @@ int checkboard(void)
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* PLB @ 133 MHz
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*
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************************************************************************/
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#define NUM_TRIES 64
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#define NUM_READS 10
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void sdram_tr1_set(int ram_address, int* tr1_value)
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{
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int i;
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int j, k;
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volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
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int first_good = -1, last_bad = 0x1ff;
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unsigned long test[NUM_TRIES] = {
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
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/* go through all possible SDRAM0_TR1[RDCT] values */
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for (i=0; i<=0x1ff; i++) {
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/* set the current value for TR1 */
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mtsdram(mem_tr1, (0x80800800 | i));
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/* write values */
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for (j=0; j<NUM_TRIES; j++) {
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ram_pointer[j] = test[j];
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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}
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/* read values back */
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for (j=0; j<NUM_TRIES; j++) {
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for (k=0; k<NUM_READS; k++) {
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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if (ram_pointer[j] != test[j])
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break;
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}
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/* read error */
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if (k != NUM_READS) {
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break;
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}
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}
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/* we have a SDRAM0_TR1[RDCT] that is part of the window */
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if (j == NUM_TRIES) {
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if (first_good == -1)
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first_good = i; /* found beginning of window */
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} else { /* bad read */
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/* if we have not had a good read then don't care */
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if(first_good != -1) {
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/* first failure after a good read */
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last_bad = i-1;
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break;
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}
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}
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}
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/* return the current value for TR1 */
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*tr1_value = (first_good + last_bad) / 2;
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}
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void sdram_init(void)
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{
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register uint reg;
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int tr1_bank1, tr1_bank2;
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/*--------------------------------------------------------------------
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* Setup some default
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@ -221,7 +297,7 @@ void sdram_init(void)
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mtsdram(mem_wddctr, 0x40000000); /* ?? */
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/*clear this first, if the DDR is enabled by a debugger
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then you can not make changes. */
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then you can not make changes. */
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mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
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/*--------------------------------------------------------------------
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@ -234,7 +310,6 @@ void sdram_init(void)
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mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
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mtsdram(mem_tr0, 0x410a4012); /* ?? */
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mtsdram(mem_tr1, 0x8080080b); /* ?? */
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mtsdram(mem_rtr, 0x04080000); /* ?? */
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mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
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mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
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@ -250,6 +325,10 @@ void sdram_init(void)
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if (reg & 0x80000000)
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break;
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}
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sdram_tr1_set(0x00000000, &tr1_bank1);
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sdram_tr1_set(0x08000000, &tr1_bank2);
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mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
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}
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/*************************************************************************
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@ -59,10 +59,10 @@ int board_early_init_f(void)
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* Setup the GPIO pins
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*-------------------------------------------------------------------*/
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/*CPLD cs */
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/*setup Address lines for flash sizes larger than 16Meg. */
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out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
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/*setup Address lines for flash size 64Meg. */
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out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
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/*setup emac */
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
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@ -125,7 +125,7 @@ int board_early_init_f(void)
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*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
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/*get rid of flash write protect */
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*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
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*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
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return 0;
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}
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@ -203,9 +203,85 @@ int checkboard(void)
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* PLB @ 133 MHz
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*
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************************************************************************/
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#define NUM_TRIES 64
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#define NUM_READS 10
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void sdram_tr1_set(int ram_address, int* tr1_value)
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{
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int i;
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int j, k;
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volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
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int first_good = -1, last_bad = 0x1ff;
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unsigned long test[NUM_TRIES] = {
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
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/* go through all possible SDRAM0_TR1[RDCT] values */
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for (i=0; i<=0x1ff; i++) {
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/* set the current value for TR1 */
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mtsdram(mem_tr1, (0x80800800 | i));
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/* write values */
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for (j=0; j<NUM_TRIES; j++) {
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ram_pointer[j] = test[j];
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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}
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/* read values back */
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for (j=0; j<NUM_TRIES; j++) {
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for (k=0; k<NUM_READS; k++) {
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/* clear any cache at ram location */
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__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
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if (ram_pointer[j] != test[j])
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break;
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}
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/* read error */
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if (k != NUM_READS) {
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break;
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}
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}
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/* we have a SDRAM0_TR1[RDCT] that is part of the window */
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if (j == NUM_TRIES) {
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if (first_good == -1)
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first_good = i; /* found beginning of window */
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} else { /* bad read */
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/* if we have not had a good read then don't care */
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if(first_good != -1) {
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/* first failure after a good read */
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last_bad = i-1;
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break;
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}
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}
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}
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/* return the current value for TR1 */
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*tr1_value = (first_good + last_bad) / 2;
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}
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void sdram_init(void)
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{
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register uint reg;
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int tr1_bank1, tr1_bank2;
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/*--------------------------------------------------------------------
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* Setup some default
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@ -217,7 +293,7 @@ void sdram_init(void)
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mtsdram(mem_wddctr, 0x40000000); /* ?? */
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/*clear this first, if the DDR is enabled by a debugger
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then you can not make changes. */
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then you can not make changes. */
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mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
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/*--------------------------------------------------------------------
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@ -230,7 +306,6 @@ void sdram_init(void)
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mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
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mtsdram(mem_tr0, 0x410a4012); /* ?? */
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mtsdram(mem_tr1, 0x8080080b); /* ?? */
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mtsdram(mem_rtr, 0x04080000); /* ?? */
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mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
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mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
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@ -246,6 +321,10 @@ void sdram_init(void)
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if (reg & 0x80000000)
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break;
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}
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sdram_tr1_set(0x00000000, &tr1_bank1);
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sdram_tr1_set(0x08000000, &tr1_bank2);
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mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
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}
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/*************************************************************************
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