Fix ATC board configuration and flash driver
This commit is contained in:
wdenk
parent
9c62cc58b8
commit
e600962991
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@ -292,9 +292,8 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
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/* The manufacturer codes are only 1 byte, so just use 1 byte.
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* This works for any bus width and any FLASH device width.
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*/
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udelay(1000000);//psl
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//psl switch (addr[1] & 0xff) {
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switch (addr[0] & 0xff) {//psl
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udelay(100);
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switch (addr[0] & 0xff) {
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case (uchar)AMD_MANUFACT:
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info->flash_id = FLASH_MAN_AMD;
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@ -312,7 +311,6 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
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}
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/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
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//psl if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) {
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if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
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case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
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@ -519,46 +517,46 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
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*/
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
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{
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FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
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int bytes; /* number of bytes to program in current word */
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int left; /* number of bytes left to program */
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int i, res;
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FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
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int bytes; /* number of bytes to program in current word */
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int left; /* number of bytes left to program */
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int i, res;
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for (left = cnt, res = 0;
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left > 0 && res == 0;
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addr += sizeof(data), left -= sizeof(data) - bytes) {
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for (left = cnt, res = 0;
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left > 0 && res == 0;
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addr += sizeof(data), left -= sizeof(data) - bytes) {
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bytes = addr & (sizeof(data) - 1);
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addr &= ~(sizeof(data) - 1);
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bytes = addr & (sizeof(data) - 1);
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addr &= ~(sizeof(data) - 1);
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/* combine source and destination data so can program
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* an entire word of 16 or 32 bits
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*/
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for (i = 0; i < sizeof(data); i++) {
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data <<= 8;
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if (i < bytes || i - bytes >= left )
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data += *((uchar *)addr + i);
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else
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data += *src++;
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/* combine source and destination data so can program
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* an entire word of 16 or 32 bits
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*/
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for (i = 0; i < sizeof(data); i++) {
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data <<= 8;
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if (i < bytes || i - bytes >= left )
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data += *((uchar *)addr + i);
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else
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data += *src++;
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}
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/* write one word to the flash */
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD:
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res = write_word_amd(info, (FPWV *)addr, data);
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break;
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case FLASH_MAN_INTEL:
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res = write_word_intel(info, (FPWV *)addr, data);
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break;
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default:
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/* unknown flash type, error! */
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printf ("missing or unknown FLASH type\n");
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res = 1; /* not really a timeout, but gives error */
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break;
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}
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}
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/* write one word to the flash */
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD:
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res = write_word_amd(info, (FPWV *)addr, data);
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break;
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case FLASH_MAN_INTEL:
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res = write_word_intel(info, (FPWV *)addr, data);
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break;
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default:
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/* unknown flash type, error! */
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printf ("missing or unknown FLASH type\n");
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res = 1; /* not really a timeout, but gives error */
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break;
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}
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}
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return (res);
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return (res);
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}
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/*-----------------------------------------------------------------------
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@ -573,43 +571,43 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
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*/
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static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
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{
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ulong start;
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int flag;
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int res = 0; /* result, assume success */
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FPWV *base; /* first address in flash bank */
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ulong start;
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int flag;
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int res = 0; /* result, assume success */
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FPWV *base; /* first address in flash bank */
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/* Check if Flash is (sufficiently) erased */
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if ((*dest & data) != data) {
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return (2);
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}
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base = (FPWV *)(info->start[0]);
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
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base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
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base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
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*dest = data; /* start programming the data */
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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start = get_timer (0);
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/* data polling for D7 */
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while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
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if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
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*dest = (FPW)0x00F000F0; /* reset bank */
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res = 1;
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/* Check if Flash is (sufficiently) erased */
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if ((*dest & data) != data) {
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return (2);
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}
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}
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return (res);
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base = (FPWV *)(info->start[0]);
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
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base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
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base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
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*dest = data; /* start programming the data */
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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start = get_timer (0);
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/* data polling for D7 */
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while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
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if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
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*dest = (FPW)0x00F000F0; /* reset bank */
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res = 1;
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}
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}
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return (res);
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}
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/*-----------------------------------------------------------------------
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@ -624,42 +622,42 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
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*/
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static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
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{
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ulong start;
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int flag;
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int res = 0; /* result, assume success */
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ulong start;
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int flag;
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int res = 0; /* result, assume success */
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/* Check if Flash is (sufficiently) erased */
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if ((*dest & data) != data) {
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return (2);
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}
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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*dest = (FPW)0x00500050; /* clear status register */
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*dest = (FPW)0x00FF00FF; /* make sure in read mode */
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*dest = (FPW)0x00400040; /* program setup */
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*dest = data; /* start programming the data */
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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start = get_timer (0);
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while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
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if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
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*dest = (FPW)0x00B000B0; /* Suspend program */
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res = 1;
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/* Check if Flash is (sufficiently) erased */
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if ((*dest & data) != data) {
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return (2);
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}
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}
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if (res == 0 && (*dest & (FPW)0x00100010))
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res = 1; /* write failed, time out error is close enough */
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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*dest = (FPW)0x00500050; /* clear status register */
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*dest = (FPW)0x00FF00FF; /* make sure in read mode */
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*dest = (FPW)0x00500050; /* clear status register */
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*dest = (FPW)0x00FF00FF; /* make sure in read mode */
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*dest = (FPW)0x00400040; /* program setup */
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return (res);
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*dest = data; /* start programming the data */
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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start = get_timer (0);
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while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
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if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
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*dest = (FPW)0x00B000B0; /* Suspend program */
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res = 1;
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}
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}
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if (res == 0 && (*dest & (FPW)0x00100010))
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res = 1; /* write failed, time out error is close enough */
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*dest = (FPW)0x00500050; /* clear status register */
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*dest = (FPW)0x00FF00FF; /* make sure in read mode */
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return (res);
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}
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@ -232,7 +232,7 @@
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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@ -242,7 +242,7 @@
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#if 1
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/* environment is in Flash */
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#define CFG_ENV_IS_IN_FLASH 1
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# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
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# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x30000)
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# define CFG_ENV_SIZE 0x10000
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# define CFG_ENV_SECT_SIZE 0x10000
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#else
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