Patch by Andrea Marson, 11 Jun 2004:
Update for PPChameleon board: - support for SysClk @ 25MHz - support for Silicon Motion SM712 VGA controller - some clean ups
This commit is contained in:
wdenk
parent
93f6a6771b
commit
e55ca7e262
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@ -2,6 +2,12 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Patch by Andrea Marson, 11 Jun 2004:
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Update for PPChameleon board:
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- support for SysClk @ 25MHz
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- support for Silicon Motion SM712 VGA controller
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- some clean ups
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* Patches by Richard Woodruff, 10 Jun 2004:
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- fix problems with examples/stubs.c for GCC >= 3.4
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- fix problems with gd initialization
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10
CREDITS
10
CREDITS
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@ -254,6 +254,11 @@ N: Dan Malek
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E: dan@netx4.com
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D: FADSROM, the grandfather of all of this
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N: Andrea "llandre" Marson
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E: andrea.marson@dave-tech.it
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D: Port to PPChameleonEVB board
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W: www.dave-tech.it
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N: Reinhard Meyer
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E: r.meyer@emk-elektronik.de
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D: Port to EMK TOP860 Module
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@ -338,6 +343,11 @@ N: Kurt Stremerch
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E: kurt@exys.be
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D: Support for Exys XSEngine board
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N: Andrea Scian
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E: andrea.scian@dave-tech.it
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D: Port to B2 board
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W: www.dave-tech.it
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N: Rob Taylor
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E: robt@flyingpig.com
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D: Port to MBX860T and Sandpoint8240
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@ -185,6 +185,10 @@ Eran Man <eran@nbase.co.il>
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EVB64260_750CX MPC750CX
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Andrea "llandre" Marson <andrea.marson@dave-tech.it>
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PPChameleonEVB PPC405EP
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Reinhard Meyer <r.meyer@emk-elektronik.de>
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TOP860 MPC860T
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@ -373,6 +377,10 @@ Robert Schwebel <r.schwebel@pengutronix.de>
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csb226 xscale
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innokom xscale
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Andrea Scian <andrea.scian@dave-tech.it>
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B2 ARM7TDMI (S3C44B0X)
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Alex Züpke <azu@sysgo.de>
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lart SA1100
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20
Makefile
20
Makefile
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@ -606,7 +606,7 @@ wtk_config: unconfig
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#########################################################################
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## PPC4xx Systems
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#########################################################################
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xtract_4xx = $(subst _MODEL_BA,,$(subst _MODEL_ME,,$(subst _MODEL_HI,,$(subst _config,,$1))))
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xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(subst _config,,$1))))))
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ADCIOP_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx adciop esd
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@ -706,10 +706,12 @@ PLU405_config: unconfig
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PMC405_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd
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PPChameleonEVB_MODEL_BA_config \
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PPChameleonEVB_MODEL_ME_config \
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PPChameleonEVB_MODEL_HI_config \
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PPChameleonEVB_config: unconfig
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PPChameleonEVB_BA_25_config \
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PPChameleonEVB_ME_25_config \
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PPChameleonEVB_HI_25_config \
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PPChameleonEVB_BA_33_config \
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PPChameleonEVB_ME_33_config \
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PPChameleonEVB_HI_33_config: unconfig
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@ >include/config.h
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@[ -z "$(findstring _MODEL_BA,$@)" ] || \
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{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \
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@ -723,6 +725,14 @@ PPChameleonEVB_config: unconfig
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{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \
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echo "... HIGH-END model" ; \
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}
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@[ -z "$(findstring _25,$@)" ] || \
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{ echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \
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echo " SysClk = 25MHz" ; \
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}
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@[ -z "$(findstring _33,$@)" ] || \
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{ echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \
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echo " SysClk = 33MHz" ; \
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}
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@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
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VOH405_config: unconfig
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@ -29,22 +29,9 @@
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#include <command.h>
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#include <malloc.h>
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/* ------------------------------------------------------------------------- */
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#if 0
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#define FPGA_DEBUG
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#endif
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/* fpga configuration data - gzip compressed and generated by bin2c */
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const unsigned char fpgadata[] =
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{
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#include "fpgadata.c"
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};
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/*
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* include common fpga code (for esd boards)
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*/
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#include "../common/fpga.c"
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/* Prototypes */
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@ -60,13 +47,13 @@ int board_early_init_f (void)
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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* IRQ 25 (EXT IRQ 0)
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* IRQ 26 (EXT IRQ 1)
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* IRQ 27 (EXT IRQ 2)
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* IRQ 28 (EXT IRQ 3)
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* IRQ 29 (EXT IRQ 4)
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* IRQ 30 (EXT IRQ 5)
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* IRQ 31 (EXT IRQ 6)
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*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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@ -268,8 +255,13 @@ nand_init(void)
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{
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ulong totlen = 0;
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#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) || \
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/*
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The HI model is equipped with a large block NAND chip not supported yet
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by U-Boot
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(CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
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*/
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#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
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debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
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totlen += nand_probe (CFG_NAND0_BASE);
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#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
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@ -280,3 +272,39 @@ nand_init(void)
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printf ("%4lu MB\n", totlen >>20);
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}
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#endif
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#ifdef CONFIG_CFB_CONSOLE
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# ifdef CONFIG_CONSOLE_EXTRA_INFO
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# include <video_fb.h>
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extern GraphicDevice smi;
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void video_get_info_str (int line_number, char *info)
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{
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uint pvr = get_pvr ();
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/* init video info strings for graphic console */
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switch (line_number) {
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case 1:
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switch (pvr) {
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case PVR_405EP_RB:
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sprintf (info, " IBM PowerPC 405EP Rev. B");
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break;
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default:
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sprintf (info, " IBM PowerPC 405EP Rev. <unknown>");
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break;
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}
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return;
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case 2:
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sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
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return;
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case 3:
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sprintf (info, " %s", smi.modeIdent);
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return;
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}
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/* no more info lines */
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*info = 0;
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return;
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}
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# endif /* CONFIG_CONSOLE_EXTRA_INFO */
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#endif /* CONFIG_CFB_CONSOLE */
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@ -50,6 +50,9 @@ unsigned long flash_init (void)
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unsigned long base;
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int size_val = 0;
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debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
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debug("[%s, %d] flash_info = 0x%08X ...\n", __FUNCTION__, __LINE__, flash_info);
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/* Init: no FLASHes known */
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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@ -57,6 +60,7 @@ unsigned long flash_init (void)
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/* Static FLASH Bank configuration here - FIXME XXX */
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debug("[%s, %d] Calling flash_get_size ...\n", __FUNCTION__, __LINE__);
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size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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@ -64,8 +68,11 @@ unsigned long flash_init (void)
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size, size<<20);
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}
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debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
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/* Setup offsets */
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flash_get_offsets (-size, &flash_info[0]);
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debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
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/* Re-do sizing to get full correct info */
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mtdcr(ebccfga, pb0cr);
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@ -91,6 +98,7 @@ unsigned long flash_init (void)
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}
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pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
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mtdcr(ebccfgd, pbcr);
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debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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@ -98,6 +106,7 @@ unsigned long flash_init (void)
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0xffffffff,
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&flash_info[0]);
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debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
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flash_info[0].size = size;
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return (size);
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@ -220,6 +220,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
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ulong base = (ulong)addr;
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volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
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debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
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/* Write auto select command: read Manufacturer ID */
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addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
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addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
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@ -383,8 +383,13 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo)
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*/
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pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
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if (pllmr1 & PLLMR1_SSCS_MASK) {
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sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv)
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/ pllmr0_ccdv;
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/*
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* This is true if FWDVA == FWDVB:
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* sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv)
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* / pllmr0_ccdv;
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*/
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sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv * sysInfo->pllFwdDivB)
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/ sysInfo->pllFwdDiv / pllmr0_ccdv;
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} else {
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sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
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}
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@ -38,6 +38,18 @@
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#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
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#endif
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/* Only one of the following two symbols must be defined (default is 25 MHz)
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* CONFIG_PPCHAMELEON_CLK_25
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* CONFIG_PPCHAMELEON_CLK_33
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*/
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#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
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#error "* Two external frequencies (SysClk) are defined! *"
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#endif
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#undef CONFIG_PPCHAMELEON_SMI712
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/*
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* Debug stuff
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*/
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@ -60,7 +72,14 @@
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
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#ifdef CONFIG_PPCHAMELEON_CLK_25
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#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
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#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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#else
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#error "* External frequency (SysClk) not defined! *"
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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@ -75,7 +94,6 @@
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#undef CONFIG_EXT_PHY
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#define CONFIG_NET_MULTI 1
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@ -184,7 +202,6 @@
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#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
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#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
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#define NAND_DISABLE_CE(nand) do \
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{ \
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switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
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@ -211,7 +228,6 @@
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} \
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} while(0)
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#define NAND_CTL_CLRALE(nandptr) do \
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{ \
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switch((unsigned long)nandptr) \
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@ -292,9 +308,10 @@
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#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
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#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
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#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
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#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
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#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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@ -349,12 +366,23 @@
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/*-----------------------------------------------------------------------
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* Environment Variable setup
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*/
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#ifdef ENVIRONMENT_IN_EEPROM
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
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#define CFG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
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#else /* DEFAULT: environment in flash, using redundand flash sectors */
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
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#define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
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#define CFG_ENV_ADDR_REDUND 0xFFFFA000
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#define CFG_ENV_SIZE_REDUND 0x2000
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#endif /* ENVIRONMENT_IN_EEPROM */
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#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
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#define CFG_NVRAM_SIZE 242 /* NVRAM size */
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@ -414,23 +442,21 @@
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#define CFG_EBC_PB3AP 0x92015480
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#define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
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#if 0 /* Roese */
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/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
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#define CFG_EBC_PB1AP 0x92015480
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#define CFG_EBC_PB1CR 0xFF858000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
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/* Memory Bank 2 (CAN0, 1) initialization */
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#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
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/* Memory Bank 3 (CompactFlash IDE) initialization */
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#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
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#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
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/* Memory Bank 4 (NVRAM/RTC) initialization */
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#define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
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#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
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#ifdef CONFIG_PPCHAMELEON_SMI712
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/*
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* Video console (graphic: SMI LynxEM)
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*/
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#define CONFIG_VIDEO
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_SMI_LYNXEM
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#define CONFIG_VIDEO_LOGO
|
||||
/*#define CONFIG_VIDEO_BMP_LOGO*/
|
||||
#define CONFIG_CONSOLE_EXTRA_INFO
|
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
||||
/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
|
||||
#define CFG_ISA_IO 0xE8000000
|
||||
/* see also drivers/videomodes.c */
|
||||
#define CFG_DEFAULT_VIDEO_MODE 0x303
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
|
|
@ -485,6 +511,7 @@
|
|||
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
|
||||
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
|
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
|
@ -525,7 +552,6 @@
|
|||
/*--------------------------------------------------------------------*/
|
||||
#ifdef CONFIG_NO_SERIAL_EEPROM
|
||||
|
||||
|
||||
/*
|
||||
!-----------------------------------------------------------------------
|
||||
! Defines for entry options.
|
||||
|
|
@ -537,7 +563,6 @@
|
|||
#define DIMM_READ_ADDR 0xAB
|
||||
#define DIMM_WRITE_ADDR 0xAA
|
||||
|
||||
|
||||
#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
|
||||
#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
|
||||
#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
|
||||
|
|
@ -649,50 +674,92 @@
|
|||
#define PLL_PCIDIV_3 0x00000002
|
||||
#define PLL_PCIDIV_4 0x00000003
|
||||
|
||||
|
||||
#ifdef CONFIG_PPCHAMELEON_CLK_25
|
||||
/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
|
||||
#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
|
||||
#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
|
||||
#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
|
||||
#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_2)
|
||||
#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||
|
||||
#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
|
||||
|
||||
/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
|
||||
#define PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
|
||||
#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
|
||||
#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
|
||||
PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
|
||||
#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
|
||||
#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
|
||||
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
|
||||
#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
|
||||
#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
|
||||
#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_2)
|
||||
#define PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
|
||||
#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||
|
||||
#else
|
||||
#error "* External frequency (SysClk) not defined! *"
|
||||
#endif
|
||||
|
||||
#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
|
||||
/* Model HI */
|
||||
#define PLLMR0_DEFAULT PLLMR0_333_111_37_55_55
|
||||
#define PLLMR1_DEFAULT PLLMR1_333_111_37_55_55
|
||||
#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
|
||||
#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
|
||||
#define CFG_OPB_FREQ 55555555
|
||||
/* Model ME */
|
||||
#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
|
||||
#define PLLMR0_DEFAULT PLLMR0_266_133_33_66_33
|
||||
#define PLLMR1_DEFAULT PLLMR1_266_133_33_66_33
|
||||
#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
|
||||
#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
|
||||
#define CFG_OPB_FREQ 66666666
|
||||
#else
|
||||
/* Model BA (default) */
|
||||
#define PLLMR0_DEFAULT PLLMR0_133_133_33_66_33
|
||||
#define PLLMR1_DEFAULT PLLMR1_133_133_33_66_33
|
||||
#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
|
||||
#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
|
||||
#define CFG_OPB_FREQ 66666666
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_NO_SERIAL_EEPROM */
|
||||
|
||||
#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
|
||||
#define CONFIG_JFFS2_NAND 0 /* jffs2 on nand support */
|
||||
#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
|
||||
#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */
|
||||
#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */
|
||||
|
|
|
|||
Loading…
Reference in New Issue