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lib_ppc: rework the flush_cache 

- It is possible to miss flush/invalidate the last
  cache line, we fix it at here.
- add the volatile and memory clobber.

They are pointed by Scott Wood.

Signed-off-by: Dave Liu <daveliu@freescale.com>
This commit is contained in:
Dave Liu 2008-12-05 15:36:14 +08:00 committed by Wolfgang Denk
parent 63240ba88c
commit e39cd81c44
1 changed files with 17 additions and 19 deletions
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30
lib_ppc/cache.c
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@ -25,29 +25,27 @@
#include <asm/cache.h> #include <asm/cache.h>
#include <watchdog.h> #include <watchdog.h>
void flush_cache (ulong start_addr, ulong size) void flush_cache(ulong start_addr, ulong size)
{ {
#ifndef CONFIG_5xx #ifndef CONFIG_5xx
ulong addr, end_addr = start_addr + size; ulong addr, start, end;
if (CONFIG_SYS_CACHELINE_SIZE) { start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
addr = start_addr & (CONFIG_SYS_CACHELINE_SIZE - 1); end = start_addr + size - 1;
for (addr = start_addr;
addr < end_addr; for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
addr += CONFIG_SYS_CACHELINE_SIZE) { asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
asm ("dcbst 0,%0": :"r" (addr));
WATCHDOG_RESET(); WATCHDOG_RESET();
} }
asm ("sync"); /* Wait for all dcbst to complete on bus */ /* wait for all dcbst to complete on bus */
asm volatile("sync" : : : "memory");
for (addr = start_addr; for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
addr < end_addr; asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
addr += CONFIG_SYS_CACHELINE_SIZE) {
asm ("icbi 0,%0": :"r" (addr));
WATCHDOG_RESET(); WATCHDOG_RESET();
} }
} asm volatile("sync" : : : "memory");
asm ("sync"); /* Always flush prefetch queue in any case */ /* flush prefetch queue */
asm ("isync"); asm volatile("isync" : : : "memory");
#endif #endif
} }