From d761fa620575dff5a6a5909de53e4d1d06a71779 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 13 Dec 2010 21:53:09 -0600 Subject: [PATCH 01/63] powerpc/85xx: Removed support for ATUM8548 board The ATUM8548 board is no longer maintained and thus we are removing support for it. Signed-off-by: Kumar Gala --- MAINTAINERS | 4 - board/atum8548/Makefile | 57 ----- board/atum8548/atum8548.c | 297 ------------------------- board/atum8548/ddr.c | 83 ------- board/atum8548/law.c | 61 ----- board/atum8548/tlb.c | 90 -------- boards.cfg | 1 - doc/README.atum8548 | 29 --- include/configs/ATUM8548.h | 443 ------------------------------------- 9 files changed, 1065 deletions(-) delete mode 100644 board/atum8548/Makefile delete mode 100644 board/atum8548/atum8548.c delete mode 100644 board/atum8548/ddr.c delete mode 100644 board/atum8548/law.c delete mode 100644 board/atum8548/tlb.c delete mode 100644 doc/README.atum8548 delete mode 100644 include/configs/ATUM8548.h diff --git a/MAINTAINERS b/MAINTAINERS index d7cd09c13..dbae8102a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -256,10 +256,6 @@ Sangmoon Kim debris MPC8245 KVME080 MPC8245 -Robert Lazarski - - ATUM8548 MPC8548 - The LEOX team ELPT860 MPC860T diff --git a/board/atum8548/Makefile b/board/atum8548/Makefile deleted file mode 100644 index 0bb9ec86e..000000000 --- a/board/atum8548/Makefile +++ /dev/null @@ -1,57 +0,0 @@ -# -# Copyright 2004 Freescale Semiconductor. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-$(CONFIG_FSL_DDR2) += ddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c deleted file mode 100644 index 9403e4b02..000000000 --- a/board/atum8548/atum8548.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright 2007 - * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com - * - * Copyright 2007 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -long int fixed_sdram(void); - -int board_early_init_f (void) -{ - return 0; -} - -int checkboard (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); - - if ((uint)&gur->porpllsr != 0xe00e0000) { - printf("immap size error %lx\n",(ulong)&gur->porpllsr); - } - printf ("Board: ATUM8548\n"); - - lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ - lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ - ecm->eedr = 0xffffffff; /* Clear ecm errors */ - ecm->eeer = 0xffffffff; /* Enable ecm errors */ - - return 0; -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) -{ - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_SPD_EEPROM) - puts("fsl_ddr_sdram\n"); - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - puts("fixed_sdram\n"); - dram_size = fixed_sdram (); -#endif - - puts(" DDR: "); - return dram_size; -} - -#if defined(CONFIG_SYS_DRAM_TEST) -int -testdram(void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("Testing DRAM from 0x%08x to 0x%08x\n", - CONFIG_SYS_MEMTEST_START, - CONFIG_SYS_MEMTEST_END); - - printf("DRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) { - printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p); - *p = 0xaaaaaaaa; - } - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("DRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("DRAM test passed.\n"); - return 0; -} -#endif - -#ifdef CONFIG_PCI1 -static struct pci_controller pci1_hose; -#endif - -#ifdef CONFIG_PCI2 -static struct pci_controller pci2_hose; -#endif - -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -void pci_init_board(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[3]; - u32 devdisr, pordevsr, io_sel; - u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; - int first_free_busno = 0; - int num = 0; - - int pcie_ep, pcie_configured; - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - porpllsr = in_be32(&gur->porpllsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - - debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - - /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */ - setbits_be32(&gur->clkocr, MPC85xx_ATUM_CLKOCR); - - if (io_sel & 1) { - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) - printf("eTSEC1 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) - printf("eTSEC2 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) - printf("eTSEC3 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) - printf("eTSEC4 is in sgmii mode.\n"); - } - -#ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); -#ifdef CONFIG_SYS_PCIE1_MEM_BUS2 - /* outbound memory */ - pci_set_region(&pcie1_hose.regions[0], - CONFIG_SYS_PCIE1_MEM_BUS2, - CONFIG_SYS_PCIE1_MEM_PHYS2, - CONFIG_SYS_PCIE1_MEM_SIZE2, - PCI_REGION_MEM); - - pcie1_hose.region_count = 1; -#endif - printf ("PCIE1: connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif - -#ifdef CONFIG_PCI1 - pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */ - pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ - pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; - pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; - - if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info[num], 1); - pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); - printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", - (pci_32) ? 32 : 64, - (pci_speed == 33333000) ? "33" : - (pci_speed == 66666000) ? "66" : "unknown", - pci_clk_sel ? "sync" : "async", - pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter", - pci_info[num].regs); - - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pci1_hose, first_free_busno); - } else { - printf("PCI1: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ -#endif - -#ifdef CONFIG_PCI2 - if (!(devdisr & MPC85xx_DEVDISR_PCI2)) { - SET_STD_PCI_INFO(pci_info[num], 2); - pci_agent = fsl_setup_hose(&pci2_hose, pci_info[num].regs); - - puts("PCI2\n"); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pci1_hose, first_free_busno); - } else { - printf("PCI2: disabled\n"); - } - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ -#endif -} - - -int last_stage_init(void) -{ - int ic = icache_status (); - printf ("icache_status: %d\n", ic); - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - FT_FSL_PCI_SETUP; -} -#endif diff --git a/board/atum8548/ddr.c b/board/atum8548/ddr.c deleted file mode 100644 index ab64fa88f..000000000 --- a/board/atum8548/ddr.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include - -#include -#include - -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); - } -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 10; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/atum8548/law.c b/board/atum8548/law.c deleted file mode 100644 index 724b1bf0b..000000000 --- a/board/atum8548/law.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCIe MEM 512M - * 0xc000_0000 0xdfff_ffff PCI2 MEM 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe10f_ffff PCI1 IO 1M - * 0xe280_0000 0xe20f_ffff PCI2 IO 1M - * 0xe300_0000 0xe30f_ffff PCIe IO 1M - * 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - * LAW 0 is reserved for boot mapping - */ - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), - /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW(CONFIG_SYS_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/atum8548/tlb.c b/board/atum8548/tlb.c deleted file mode 100644 index ef7942cb1..000000000 --- a/board/atum8548/tlb.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 Initializations */ - /* - * TLB 0, 1: 128M Non-cacheable, guarded - * 0xf8000000 128M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, CONFIG_SYS_FLASH_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 2: 1G Non-cacheable, guarded - * 0x80000000 1G PCI1/PCIE 8,9,a,b - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_1G, 1), - - /* - * TLB 3, 4: 512M Non-cacheable, guarded - * 0xc0000000 1G PCI2 - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 1M PCI1 IO - * 0xe210_0000 1M PCI2 IO - * 0xe300_0000 1M PCIe IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 0574bb204..0c394ade6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -441,7 +441,6 @@ MVBLM7 powerpc mpc83xx mvblm7 matrix_ SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP TQM834x powerpc mpc83xx tqm834x tqc -ATUM8548 powerpc mpc85xx atum8548 MPC8540EVAL powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M MPC8540EVAL_33 powerpc mpc85xx mpc8540eval - - MPC8540EVAL MPC8540EVAL_33_slave powerpc mpc85xx mpc8540eval - - MPC8540EVAL:PCI_SLAVE diff --git a/doc/README.atum8548 b/doc/README.atum8548 deleted file mode 100644 index 4eb56bae2..000000000 --- a/doc/README.atum8548 +++ /dev/null @@ -1,29 +0,0 @@ -Building U-Boot ---------------- - -The ATUM8548 code is known to build using ELDK 4.1. - -$ make ATUM8548_config -Configuring for ATUM8548 board... -$ make - -Using Flash ------------ - -The ATUM8548 board has one flash bank, of 128MB in size (2^23 = 0x08000000). - -The BDI2000 commands for copying u-boot into flash are -as follows: - - erase 0xFFF80000 0x4000 0x20 - prog 0xfff80000 uboot.bin bin - -Booting Linux -------------- - -U-boot/kermit commands for booting linux via NFS - assumming the proper -bootargs are set - are as follows: - - tftp 1000000 uImage.atum - tftp c00000 mpc8548atum.dtb - bootm 1000000 - c00000 diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h deleted file mode 100644 index 78757ecce..000000000 --- a/include/configs/ATUM8548.h +++ /dev/null @@ -1,443 +0,0 @@ -/* - * Copyright 2007 - * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com - * - * Copyright 2004, 2007 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * atum8548 board configuration file - * - * Please refer to doc/README.atum8548 for more info. - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Debug Options, Disable in production -#define ET_DEBUG 1 -#define CONFIG_PANIC_HANG 1 -#define DEBUG 1 -*/ - -/* CPLD Configuration Options */ -#define MPC85xx_ATUM_CLKOCR 0x80000002 - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ -#define CONFIG_MPC8548 1 /* MPC8548 specific */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xfff80000 -#endif - -#define CONFIG_PCI 1 /* enable any pci type devices */ -#define CONFIG_PCI1 1 /* PCI controller 1 */ -#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCI2 1 /* PCI controller 2 */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ - -#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#define CONFIG_SYS_CLK_FREQ 33000000 - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */ -#define CONFIG_ENABLE_36BIT_PHYS 1 -#undef CONFIG_SYS_DRAM_TEST -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - -#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */ - -/* DDR Setup */ -#define CONFIG_FSL_DDR2 -#undef CONFIG_FSL_DDR_INTERACTIVE -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* Manually set up DDR parameters */ -#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-1024 */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x38355322 -#define CONFIG_SYS_DDR_TIMING_2 0x039048c7 -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_MODE 0x00000432 -#define CONFIG_SYS_DDR_INTERVAL 0x05150100 -#define DDR_SDRAM_CFG 0x43000000 - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * based on flash chip S29GL01GP - * One bank, 128M, using the CFI driver. - * Boot from BR0 bank at 0xf800_0000 - * - * BR0: - * Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0 - * - * OR0: - * Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0 - * Reserved ORx[17:18] = 00 - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx - */ - -#define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */ - -#define CONFIG_SYS_BR0_PRELIM 0xf8001001 - -#define CONFIG_SYS_OR0_PRELIM 0xf8000E65 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */ - - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* - * Flash on the LocalBus - */ -#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ - -/* Memory */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ - -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#ifdef CONFIG_PCI2 -#define CONFIG_SYS_PCI2_MEM_BUS 0xC0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ -#endif - -#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ -#endif - - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC2" -#define CONFIG_TSEC4 1 -#define CONFIG_TSEC4_NAME "eTSEC3" -#undef CONFIG_MPC85XX_FEC - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC3_PHY_ADDR 2 -#define TSEC4_PHY_ADDR 3 - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS TSEC_GIGABIT -#define TSEC4_FLAGS TSEC_GIGABIT - -/* Options are: eTSEC[0-3] */ -#define CONFIG_ETHPRIME "eTSEC2" -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD -#endif - -#define CONFIG_IPADDR 10.101.43.142 - -#define CONFIG_HOSTNAME atum -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE /tftpboot/uImage.atum -#define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */ - -#define CONFIG_SERVERIP 10.101.43.10 -#define CONFIG_GATEWAYIP 10.101.45.1 -#define CONFIG_NETMASK 255.255.248.0 - -#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ - -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr - $dtbaddr" - - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr $ramdiskaddr $dtbaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ From 341d30d4c8ebebd6bdde6365ae26486c91e533c6 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 13 Dec 2010 22:01:01 -0600 Subject: [PATCH 02/63] powerpc/85xx: Removed support for MPC8540EVAL board The MPC8540EVAL board is no longer maintained and thus we are removing support for it. Signed-off-by: Kumar Gala --- board/mpc8540eval/Makefile | 54 -- board/mpc8540eval/ddr.c | 73 --- board/mpc8540eval/flash.c | 894 -------------------------------- board/mpc8540eval/law.c | 54 -- board/mpc8540eval/mpc8540eval.c | 230 -------- board/mpc8540eval/tlb.c | 78 --- boards.cfg | 5 - include/configs/MPC8540EVAL.h | 362 ------------- 8 files changed, 1750 deletions(-) delete mode 100644 board/mpc8540eval/Makefile delete mode 100644 board/mpc8540eval/ddr.c delete mode 100644 board/mpc8540eval/flash.c delete mode 100644 board/mpc8540eval/law.c delete mode 100644 board/mpc8540eval/mpc8540eval.c delete mode 100644 board/mpc8540eval/tlb.c delete mode 100644 include/configs/MPC8540EVAL.h diff --git a/board/mpc8540eval/Makefile b/board/mpc8540eval/Makefile deleted file mode 100644 index 5eccfab69..000000000 --- a/board/mpc8540eval/Makefile +++ /dev/null @@ -1,54 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-y += flash.o -COBJS-$(CONFIG_FSL_DDR1) += ddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mpc8540eval/ddr.c b/board/mpc8540eval/ddr.c deleted file mode 100644 index 7850794d6..000000000 --- a/board/mpc8540eval/ddr.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include - -#include -#include - -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/mpc8540eval/flash.c b/board/mpc8540eval/flash.c deleted file mode 100644 index 9df5bd9a4..000000000 --- a/board/mpc8540eval/flash.c +++ /dev/null @@ -1,894 +0,0 @@ -/* - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao,(X.Xiao@motorola.com) - * - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -#if !defined(CONFIG_SYS_NO_FLASH) - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/* - * The variable should be in the flash info structure. Since it - * is only used in this board specific file it is declared here. - * In the future I think an endian flag should be part of the - * flash_info_t structure. (Ron Alder) - */ -static ulong big_endian = 0; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_block (flash_info_t *info, uchar * src, ulong dest, ulong cnt); -static int write_short (flash_info_t *info, ulong dest, ushort data); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(flash_info_t *info, vu_long * addr); -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ - for (i=0; i= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - - /* only deal with 16 bit and 32 bit port width, 16bit chip */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value,va,vb,vc,vd; - ulong base = (ulong)addr; - ulong sector_offset; - -#ifdef DEBUG - printf("Check flash at 0x%08x\n",(uint)addr); -#endif - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - udelay(20); - asm("sync"); - -#ifndef CONFIG_SYS_FLASH_CFI - printf("Not define CONFIG_SYS_FLASH_CFI\n"); - return (0); -#else - value = addr[0]; - va=(value & 0xFF000000)>>24; - vb=(value & 0x00FF0000)>>16; - vc=(value & 0x0000FF00)>>8; - vd=(value & 0x000000FF); - if ((va==0) && (vb==0)) { - printf("cannot identify Flash\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - else if ((va==0) && (vb!=0)) { - big_endian = 1; - info->chipwidth = FLASH_CFI_BY16; - if(vb == vd) info->portwidth = FLASH_CFI_32BIT; - else info->portwidth = FLASH_CFI_16BIT; - } - else if ((va!=0) && (vb==0)) { - big_endian = 0; - info->chipwidth = FLASH_CFI_BY16; - if(va == vc) info->portwidth = FLASH_CFI_32BIT; - else info->portwidth = FLASH_CFI_16BIT; - } - else if ((va!=0) && (vb!=0)) { - big_endian = 1; /* no meaning for 8bit chip */ - info->chipwidth = FLASH_CFI_BY8; - if(va == vb) info->portwidth = FLASH_CFI_16BIT; - else info->portwidth = FLASH_CFI_8BIT; - } -#ifdef DEBUG - switch (info->portwidth) { - case FLASH_CFI_8BIT: - printf("port width is 8 bit.\n"); - break; - case FLASH_CFI_16BIT: - printf("port width is 16 bit, "); - break; - case FLASH_CFI_32BIT: - printf("port width is 32 bit, "); - break; - } - switch (info->chipwidth) { - case FLASH_CFI_BY16: - printf("chip width is 16 bit, "); - switch (big_endian) { - case 0: - printf("Little Endian.\n"); - break; - case 1: - printf("Big Endian.\n"); - break; - } - break; - } -#endif -#endif /*#ifdef CONFIG_SYS_FLASH_CFI*/ - - if (big_endian==0) value = (addr[0] & 0xFF000000) >>8; - else value = (addr[0] & 0x00FF0000); -#ifdef DEBUG - printf("manufacturer=0x%x\n",(uint)(value>>16)); -#endif - switch (value) { - case MT_MANUFACT & 0xFFFF0000: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU & 0xFFFF0000: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - if (info->portwidth==FLASH_CFI_16BIT) { - switch (big_endian) { - case 0: - value = (addr[0] & 0x0000FF00)>>8; - break; - case 1: - value = (addr[0] & 0x000000FF); - break; - } - } - else if (info->portwidth == FLASH_CFI_32BIT) { - switch (big_endian) { - case 0: - value = (addr[1] & 0x0000FF00)>>8; - break; - case 1: - value = (addr[1] & 0x000000FF); - break; - } - } - -#ifdef DEBUG - printf("deviceID=0x%x\n",(uint)value); -#endif - switch (value) { - case (INTEL_ID_28F016S & 0x0000FFFF): - info->flash_id += FLASH_28F016SV; - info->sector_count = 32; - sector_offset = 0x10000; - break; /* => 2 MB */ - - case (INTEL_ID_28F160S3 & 0x0000FFFF): - info->flash_id += FLASH_28F160S3; - info->sector_count = 32; - sector_offset = 0x10000; - break; /* => 2 MB */ - - case (INTEL_ID_28F320S3 & 0x0000FFFF): - info->flash_id += FLASH_28F320S3; - info->sector_count = 64; - sector_offset = 0x10000; - break; /* => 4 MB */ - - case (INTEL_ID_28F640J3A & 0x0000FFFF): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - sector_offset = 0x20000; - break; /* => 8 MB */ - - case SHARP_ID_28F016SCL & 0x0000FFFF: - case SHARP_ID_28F016SCZ & 0x0000FFFF: - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - info->sector_count = 32; - sector_offset = 0x10000; - break; /* => 2 MB */ - - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - sector_offset = sector_offset * (info->portwidth / info->chipwidth); - info->size = info->sector_count * sector_offset; - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += sector_offset; - /* don't know how to check sector protection */ - info->protect[i] = 0; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - *addr = 0xFFFFFF; /* reset bank to read array mode */ - asm("sync"); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last, ready, erase_err_status; - - if (big_endian == 1) { - ready = 0x0080; - erase_err_status = 0x00a0; - } - else { - ready = 0x8000; - erase_err_status = 0xa000; - } - if ((info->portwidth / info->chipwidth)==2) { - ready += (ready <<16); - erase_err_status += (erase_err_status <<16); - } - -#ifdef DEBUG - printf ("\nReady flag is 0x%lx\nErase error flag is 0x%lx", ready, erase_err_status); -#endif - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - -#ifdef DEBUG - printf("\nFlash Erase:\n"); -#endif - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit(info, (vu_long *)(info->start[s_first]))){ - return 1; - } - - /* Start erase on unprotected sectors */ -#if defined(DEBUG) - printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); -#endif - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr16 = (vu_short *)(info->start[sect]); - vu_long *addr = (vu_long *)(info->start[sect]); - printf("."); - switch (info->portwidth) { - case FLASH_CFI_16BIT: - asm("sync"); - last = start = get_timer (0); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - /* Reset Array */ - *addr16 = 0xffff; - asm("sync"); - /* Clear Status Register */ - *addr16 = 0x5050; - asm("sync"); - /* Single Block Erase Command */ - *addr16 = 0x2020; - asm("sync"); - /* Confirm */ - *addr16 = 0xD0D0; - asm("sync"); - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr16 = 0xD0D0; - asm("sync"); - } - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - /* wait at least 80us - let's wait 1 ms */ - *addr16 = 0x7070; - udelay (1000); - while ((*addr16 & ready) != ready) { - if((*addr16 & erase_err_status)== erase_err_status){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr16); - *addr16 = 0xFFFF; /* reset bank */ - asm("sync"); - return 1; - } - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr16 = 0xFFFF; /* reset bank */ - asm("sync"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - /* reset to read mode */ - *addr16 = 0xFFFF; - asm("sync"); - break; - case FLASH_CFI_32BIT: - asm("sync"); - last = start = get_timer (0); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - /* Single Block Erase Command */ - *addr = 0x20202020; - asm("sync"); - /* Confirm */ - *addr = 0xD0D0D0D0; - asm("sync"); - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - asm("sync"); - } - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - /* wait at least 80us - let's wait 1 ms */ - *addr = 0x70707070; - udelay (1000); - while ((*addr & ready) != ready) { - if((*addr & erase_err_status)==erase_err_status){ - printf("Error in Block Erase - Lock Bit may be set!\n"); - printf("Status Register = 0x%X\n", (uint)*addr); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - /* reset to read mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - break; - } /* end switch */ - } /* end if */ - } /* end for */ - - printf ("flash erase done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -#define FLASH_BLOCK_SIZE 32 - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data, count, temp; -/* ulong temp[FLASH_BLOCK_SIZE/4];*/ - int i, l, rc; - - count = cnt; - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - cp = wp; - /* handle unaligned block bytes , flash block size = 16bytes */ - wp = (cp+FLASH_BLOCK_SIZE-1) & ~(FLASH_BLOCK_SIZE-1); - if ((wp-cp)>=cnt) { - if ((rc = write_block(info,src,cp,wp-cp)) !=0) - return (rc); - src += wp-cp; - cnt -= wp-cp; - } - /* handle aligned block bytes */ - temp = 0; - printf("\n"); - while ( cnt >= FLASH_BLOCK_SIZE) { - if ((rc = write_block(info,src,cp,FLASH_BLOCK_SIZE)) !=0) { - return (rc); - } - src += FLASH_BLOCK_SIZE; - cp += FLASH_BLOCK_SIZE; - cnt -= FLASH_BLOCK_SIZE; - if (((count-cnt)>>10)>temp) { - temp=(count-cnt)>>10; - printf("\r%lu KB",temp); - } - } - printf("\n"); - wp = cp; - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} -#undef FLASH_BLOCK_SIZE - -/*----------------------------------------------------------------------- - * Write block to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * -1 Error - */ -static int write_block(flash_info_t *info, uchar * src, ulong dest, ulong cnt) -{ - vu_short *baddr, *addr = (vu_short *)dest; - ushort data; - ulong start, now, xsr,csr, ready; - int flag; - - if (cnt==0) return 0; - else if(cnt != (cnt& ~1)) return -1; - - /* Check if Flash is (sufficiently) erased */ - data = * src; - data = (data<<8) | *(src+1); - if ((*addr & data) != data) { - return (2); - } - if (big_endian == 1) { - ready = 0x0080; - } - else { - ready = 0x8000; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - do { - /* Write Command */ - *addr = 0xe8e8; - asm("sync"); - xsr = *addr; - asm("sync"); - } while (!(xsr & ready)); /*wait until read */ - /*write count=BLOCK SIZE -1 */ - data=(cnt>>1)-1; - data=(data<<8)|data; - *addr = data; /* word mode, cnt/2 */ - asm("sync"); - baddr = addr; - while(cnt) { - data = * src++; - data = (data<<8) | *src++; - asm("sync"); - *baddr = data; - asm("sync"); - ++baddr; - cnt = cnt -2; - } - *addr = 0xd0d0; /* confirm write */ - start = get_timer(0); - asm("sync"); - if (flag) - enable_interrupts(); - /* data polling for D7 */ - flag = 0; - while (((csr = *addr) & ready) != ready) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x4040) { - printf ("CSR indicates write error (%04lx) at %08lx\n", - csr, (ulong)addr); - flag = 1; - } - /* Clear Status Registers Command */ - *addr = 0x5050; - asm("sync"); - /* Reset to read array mode */ - *addr = 0xFFFF; - asm("sync"); - return (flag); -} - - -/*----------------------------------------------------------------------- - * Write a short word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_short (flash_info_t *info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *)dest; - ulong start, now, csr, ready; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x1010; - start = get_timer (0); - asm("sync"); - /* Write Data */ - *addr = data; - asm("sync"); - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - if (big_endian == 1) { - ready = 0x0080; - } - else { - ready = 0x8000; - } - /* data polling for D7 */ - flag = 0; - while (((csr = *addr) & ready) != ready) { - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x4040) { - printf ("CSR indicates write error (%04lx) at %08lx\n", - csr, (ulong)addr); - flag = 1; - } - /* Clear Status Registers Command */ - *addr = 0x5050; - asm("sync"); - /* Reset to read array mode */ - *addr = 0xFFFF; - asm("sync"); - return (flag); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr, ready; - int flag=0; - - switch (info->portwidth) { - case FLASH_CFI_32BIT: - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - if (big_endian == 1) { - ready = 0x0080; - } - else { - ready = 0x8000; - } - if ((info->portwidth / info->chipwidth)==2) { - ready += (ready <<16); - } - else { - ready = ready << 16; - } - /* Write Command */ - *addr = 0x10101010; - asm("sync"); - /* Write Data */ - *addr = data; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - while (((csr = *addr) & ready) != ready) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - /* Clear Status Registers Command */ - *addr = 0x50505050; - asm("sync"); - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - break; - case FLASH_CFI_16BIT: - flag = write_short (info, dest, (unsigned short) (data>>16)); - if (flag == 0) - flag = write_short (info, dest+2, (unsigned short) (data)); - break; - } - return (flag); -} - -/*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout - */ - -static int clear_block_lock_bit(flash_info_t * info, vu_long * addr) -{ - ulong start, now, ready; - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - - *addr = 0x60606060; - asm("sync"); - *addr = 0xd0d0d0d0; - asm("sync"); - - - if (big_endian == 1) { - ready = 0x0080; - } - else { - ready = 0x8000; - } - if ((info->portwidth / info->chipwidth)==2) { - ready += (ready <<16); - } - else { - ready = ready << 16; - } -#ifdef DEBUG - printf ("%s: Ready flag is 0x%8lx\n", __FUNCTION__, ready); -#endif - *addr = 0x70707070; /* read status */ - start = get_timer (0); - while((*addr & ready) != ready){ - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - } - return 0; -} - -#endif /* !CONFIG_SYS_NO_FLASH */ diff --git a/board/mpc8540eval/law.c b/board/mpc8540eval/law.c deleted file mode 100644 index 9926d25ef..000000000 --- a/board/mpc8540eval/law.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* LAW(Local Access Window) configuration: - * 0000_0000-0800_0000: DDR(128M) -or- larger - * f000_0000-f3ff_ffff: PCI(256M) - * f400_0000-f7ff_ffff: RapidIO(128M) - * f800_0000-ffff_ffff: localbus(128M) - * f800_0000-fbff_ffff: LBC SDRAM(64M) - * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M) - * fdf0_0000-fdff_ffff: CCSRBAR(1M) - * fe00_0000-ffff_ffff: Flash(32M) - * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access - * Window. - * Note: If flash is 8M at default position(last 8M),no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), -#ifndef CONFIG_RAM_AS_FLASH - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c deleted file mode 100644 index 054d644d9..000000000 --- a/board/mpc8540eval/mpc8540eval.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include - -long int fixed_sdram (void); - -int board_pre_init (void) -{ -#if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); - - pci->peer &= 0xffffffdf; /* disable master abort */ -#endif - return 0; -} - -int checkboard (void) -{ - sys_info_t sysinfo; - - get_sys_info (&sysinfo); - - printf ("Board: Freescale MPC8540EVAL Board\n"); - printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor[0] / 1000000); - printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000); - printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); - if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \ - || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) { - printf ("\tLBC: %lu MHz\n", - sysinfo.freqSystemBus / 1000000/(CONFIG_SYS_LBC_LCRR & 0x0f)); - } else { - printf("\tLBC: unknown\n"); - } - printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n"); - return (0); -} - -phys_size_t initdram (int board_type) -{ - long dram_size = 0; - -#if !defined(CONFIG_RAM_AS_FLASH) - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - sys_info_t sysinfo; - uint temp_lbcdll = 0; -#endif -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif - -#if defined(CONFIG_DDR_DLL) - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CONFIG_SYS_RAMBOOT) - return dram_size; -#endif - -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ - get_sys_info(&sysinfo); - /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) { - lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; - } else { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff; - udelay(200); - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; - asm("sync;isync;msync"); - } - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */ - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; - asm("sync"); - * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; - asm("sync"); - * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; - asm("sync"); - * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; - asm("sync"); - * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; - asm("sync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - asm("sync"); - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("sync"); -#endif - -#if defined(CONFIG_DDR_ECC) - { - /* Initialize all of memory for ECC, then - * enable errors */ - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - - dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); - - /* Enable errors for ECC */ - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - } -#endif - - return dram_size; -} - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) -{ -#ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; -#if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; -#endif - asm("sync;isync;msync"); - udelay(500); -#if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); -#else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; -#endif - asm("sync; isync; msync"); - udelay(500); -#endif - return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024); -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - -int board_eth_init(bd_t *bis) -{ - /* - * This board either has PCI NICs or uses the CPU's TSECs - * pci_eth_init() will return 0 if no NICs found, so in that case - * returning -1 will force cpu_eth_init() to be called. - */ - int num = pci_eth_init(bis); - return (num <= 0 ? -1 : num); -} diff --git a/board/mpc8540eval/tlb.c b/board/mpc8540eval/tlb.c deleted file mode 100644 index 06092f89b..000000000 --- a/board/mpc8540eval/tlb.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - #if defined(CONFIG_SYS_FLASH_PORT_WIDTH_16) - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_4M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x400000, CONFIG_SYS_FLASH_BASE + 0x400000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_4M, 1), - #else - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_16M, 1), - #endif - - #if !defined(CONFIG_SPD_EEPROM) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 4, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_64M, 1), - #endif - - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - #if defined(CONFIG_RAM_AS_FLASH) - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - #else - MAS3_SX|MAS3_SW|MAS3_SR, 0, - #endif - 0, 6, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_16K, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_16K, 1), -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 0c394ade6..4d57517dd 100644 --- a/boards.cfg +++ b/boards.cfg @@ -441,11 +441,6 @@ MVBLM7 powerpc mpc83xx mvblm7 matrix_ SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP TQM834x powerpc mpc83xx tqm834x tqc -MPC8540EVAL powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M -MPC8540EVAL_33 powerpc mpc85xx mpc8540eval - - MPC8540EVAL -MPC8540EVAL_33_slave powerpc mpc85xx mpc8540eval - - MPC8540EVAL:PCI_SLAVE -MPC8540EVAL_66 powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M -MPC8540EVAL_66_slave powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M,PCI_SLAVE PM854 powerpc mpc85xx pm854 PM856 powerpc mpc85xx pm856 sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h deleted file mode 100644 index a96894981..000000000 --- a/include/configs/MPC8540EVAL.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - * (C) Copyright 2002,2003 Motorola,Inc. - * Modified by Lunsheng Wang, lunsheng@sohu.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* mpc8540eval board configuration file */ -/* please refer to doc/README.mpc85xxads for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC8540 1 /* MPC8540 specific */ -#define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */ - -#define CONFIG_SYS_TEXT_BASE 0xfff80000 - -#undef CONFIG_PCI /* pci ethernet support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -/* Using Localbus SDRAM to emulate flash before we can program the flash, - * normally you only need a flash-boot image(u-boot.bin),if unsure undef this. - * Not availabe for EVAL board - */ -#undef CONFIG_RAM_AS_FLASH - -/* sysclk for MPC8540EVAL */ -#if defined(CONFIG_SYSCLK_66M) - /* - * the oscillator on board is 66Mhz - * can also get 66M clock from external PCI - */ - #define CONFIG_SYS_CLK_FREQ 66000000 -#else - #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ -#endif - -/* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#undef CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) -#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both." -#endif - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - -#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is now 256MB */ - -#if defined(CONFIG_RAM_AS_FLASH) -#define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ -#else -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#endif -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 0MB */ - -#if defined(CONFIG_RAM_AS_FLASH) -#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ -#define CONFIG_SYS_BR0_PRELIM 0xf8001801 /* port size 32bit */ -#else /* Boot from real Flash */ -#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ -#define CONFIG_SYS_BR0_PRELIM 0xff801001 /* port size 16bit */ -#endif - -#define CONFIG_SYS_OR0_PRELIM 0xff806f67 /* 8MB Flash */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/ -#define CONFIG_SYS_FLASH_CFI 1 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* DDR Setup */ -#define CONFIG_FSL_DDR1 -#undef CONFIG_FSL_DDR_INTERACTIVE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ - -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -#undef CONFIG_CLOCKS_IN_MHZ - -/* local bus definitions */ -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq divider*/ -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_SYS_LBC_LSRT 0x20000000 -#define CONFIG_SYS_LBC_MRTPR 0x20000000 -#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 -#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 -#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 -#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 - -#if defined(CONFIG_RAM_AS_FLASH) -#define CONFIG_SYS_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ -#else -#define CONFIG_SYS_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */ -#endif -#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 -#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 - -/* General PCI */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI_MEM_SIZE 0x20000000 -#define CONFIG_SYS_PCI_IO_BASE 0xe2000000 - -#if defined(CONFIG_PCI) -#define CONFIG_NET_MULTI -#undef CONFIG_EEPRO100 -#define CONFIG_TULIP -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#if !defined(CONFIG_PCI_PNP) -#define PCI_ENET0_IOADDR 0xe0000000 -#define PCI_ENET0_MEMADDR 0xe0000000 -#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0008 -#elif defined(CONFIG_TSEC_ENET) -#define CONFIG_NET_MULTI 1 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_HAS_ETH1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_MPC85XX_FEC 1 -#define CONFIG_HAS_ETH2 -#define CONFIG_MPC85XX_FEC_NAME "FEC" -#define TSEC1_PHY_ADDR 7 -#define TSEC2_PHY_ADDR 4 -#define FEC_PHY_ADDR 2 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define FEC_FLAGS 0 - -/* Options are: TSEC[0-1], FEC */ -#define CONFIG_ETHPRIME "TSEC0" - -#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */ -#define INTEL_LXT971_PHY 1 -#endif - -/* Environment */ -#ifndef CONFIG_SYS_RAMBOOT -#if defined(CONFIG_RAM_AS_FLASH) -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#endif -#define CONFIG_ENV_SIZE 0x2000 -#else -/* #define CONFIG_SYS_NO_FLASH 1 */ /* Flash is not usable now */ -#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" -#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #undef CONFIG_CMD_SAVEENV - #undef CONFIG_CMD_LOADS -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/*****************************/ -/* Environment Configuration */ -/*****************************/ -/* The mac addresses for all ethernet interface */ -/* NOTE: change below for your network setting!!! */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:01:af:07:9b:8a -#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b -#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c -#endif - -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage - -#define CONFIG_SERVERIP 192.168.101.1 -#define CONFIG_IPADDR 192.168.101.11 -#define CONFIG_GATEWAYIP 192.168.101.0 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_HOSTNAME MPC8540EVAL - -#endif /* __CONFIG_H */ From 5962be6e43b2665f07619c6e133943ea032f5fee Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 13 Dec 2010 22:02:08 -0600 Subject: [PATCH 03/63] powerpc/85xx: Remove support for PM854/PM856 boards The PM854/PM856 boards are no longer maintained and thus we are removing support for them. Signed-off-by: Kumar Gala Acked-by: Wolfgang Denk --- board/pm854/Makefile | 53 ----- board/pm854/ddr.c | 73 ------- board/pm854/law.c | 58 ----- board/pm854/pm854.c | 298 -------------------------- board/pm854/tlb.c | 117 ----------- board/pm856/Makefile | 53 ----- board/pm856/ddr.c | 73 ------- board/pm856/law.c | 58 ----- board/pm856/pm856.c | 453 ---------------------------------------- board/pm856/tlb.c | 117 ----------- boards.cfg | 2 - include/configs/PM854.h | 426 ------------------------------------- include/configs/PM856.h | 429 ------------------------------------- 13 files changed, 2210 deletions(-) delete mode 100644 board/pm854/Makefile delete mode 100644 board/pm854/ddr.c delete mode 100644 board/pm854/law.c delete mode 100644 board/pm854/pm854.c delete mode 100644 board/pm854/tlb.c delete mode 100644 board/pm856/Makefile delete mode 100644 board/pm856/ddr.c delete mode 100644 board/pm856/law.c delete mode 100644 board/pm856/pm856.c delete mode 100644 board/pm856/tlb.c delete mode 100644 include/configs/PM854.h delete mode 100644 include/configs/PM856.h diff --git a/board/pm854/Makefile b/board/pm854/Makefile deleted file mode 100644 index 9f623a29d..000000000 --- a/board/pm854/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-$(CONFIG_FSL_DDR1) += ddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/pm854/ddr.c b/board/pm854/ddr.c deleted file mode 100644 index 7850794d6..000000000 --- a/board/pm854/ddr.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include - -#include -#include - -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/pm854/law.c b/board/pm854/law.c deleted file mode 100644 index ac21d7a27..000000000 --- a/board/pm854/law.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c deleted file mode 100644 index 0b8ea8192..000000000 --- a/board/pm854/pm854.c +++ /dev/null @@ -1,298 +0,0 @@ - /* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003, Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_DDR_ECC) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void); - - -int board_early_init_f (void) -{ -#if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); - - pci->peer &= 0xffffffdf; /* disable master abort */ -#endif - - return 0; -} - -int checkboard (void) -{ - puts("Board: MicroSys PM854\n"); - -#ifdef CONFIG_PCI - printf("PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf("PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init(); - - return 0; -} - - -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int i,x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) - { - gur->devdisr = gur->devdisr | 0x00010000; - asm("sync;isync;msync"); - for (i=0; idevdisr = gur->devdisr & 0xfff7ffff; - asm("sync;isync;msync"); - x++; - } - } -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CONFIG_DDR_ECC) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - puts(" DDR: "); - return dram_size; -} - - -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66MHz, DLL bypass mode must be used. - * If localbus freq is > 133MHz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr(); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) -{ - #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_pm854_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_pm854_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Intialize TSECs first */ - return pci_eth_init(bis); -} diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c deleted file mode 100644 index 5e74e2ded..000000000 --- a/board/pm854/tlb.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 64M FLASH (8,16,32 or 64 MB) - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7: 256M DDR - * 0x00000000 256M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_256M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/pm856/Makefile b/board/pm856/Makefile deleted file mode 100644 index 9f623a29d..000000000 --- a/board/pm856/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-$(CONFIG_FSL_DDR1) += ddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(OBJS) $(SOBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/pm856/ddr.c b/board/pm856/ddr.c deleted file mode 100644 index 7850794d6..000000000 --- a/board/pm856/ddr.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include - -#include -#include - -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/pm856/law.c b/board/pm856/law.c deleted file mode 100644 index ac21d7a27..000000000 --- a/board/pm856/law.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xf800_0000 0xf80f_ffff BCSR 1M - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c deleted file mode 100644 index 4e059b085..000000000 --- a/board/pm856/pm856.c +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2003,Motorola Inc. - * Xianghua Xiao, (X.Xiao@motorola.com) - * - * (C) Copyright 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_DDR_ECC) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -void local_bus_init(void); -long int fixed_sdram(void); - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ - -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } -}; - - -int board_early_init_f (void) -{ - return 0; -} - -void reset_phy (void) -{ -} - - -int checkboard (void) -{ - puts("Board: MicroSys PM856\n"); - -#ifdef CONFIG_PCI - printf("PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf("PCI1: disabled\n"); -#endif - - /* - * Initialize local bus. - */ - local_bus_init(); - - return 0; -} - - -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int i,x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) - { - gur->devdisr = gur->devdisr | 0x00010000; - asm("sync;isync;msync"); - for (i=0; idevdisr = gur->devdisr & 0xfff7ffff; - asm("sync;isync;msync"); - x++; - } - } -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CONFIG_DDR_ECC) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - puts(" DDR: "); - return dram_size; -} - - -/* - * Initialize Local Bus - */ - -void -local_bus_init(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - - uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; - - /* - * Errata LBC11. - * Fix Local Bus clock glitch when DLL is enabled. - * - * If localbus freq is < 66MHz, DLL bypass mode must be used. - * If localbus freq is > 133MHz, DLL can be safely enabled. - * Between 66 and 133, the DLL is enabled with an override workaround. - */ - - get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ - - } else if (lbc_hz >= 133) { - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ - - } else { - /* - * On REV1 boards, need to change CLKDIV before enable DLL. - * Default CLKDIV is 8, change it to 4 temporarily. - */ - uint pvr = get_pvr(); - uint temp_lbcdll = 0; - - if (pvr == PVR_85xx_REV1) { - /* FIXME: Justify the high bit here. */ - lbc->lcrr = 0x10000004; - } - - lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */ - udelay(200); - - /* - * Sample LBC DLL ctrl reg, upshift it to set the - * override bits. - */ - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); - asm("sync;isync;msync"); - } -} - -#if defined(CONFIG_SYS_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; - uint *p; - - printf("SDRAM test phase 1:\n"); - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test phase 2:\n"); - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - printf("SDRAM test passed.\n"); - return 0; -} -#endif - - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -long int fixed_sdram (void) -{ - #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - #if defined (CONFIG_DDR_ECC) - ddr->err_disable = 0x0000000D; - ddr->err_sbe = 0x00ff0000; - #endif - asm("sync;isync;msync"); - udelay(500); - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); - #else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - #endif - asm("sync; isync; msync"); - udelay(500); - #endif - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } -}; -#endif - - -static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxads_config_table, -#endif -}; - -#endif /* CONFIG_PCI */ - - -void -pci_init_board(void) -{ -#ifdef CONFIG_PCI - pci_mpc85xx_init(&hose); -#endif /* CONFIG_PCI */ -} - -int board_eth_init(bd_t *bis) -{ - cpu_eth_init(bis); /* Intialize TSECs first */ - return pci_eth_init(bis); -} diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c deleted file mode 100644 index 5e74e2ded..000000000 --- a/board/pm856/tlb.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 64M FLASH (8,16,32 or 64 MB) - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7: 256M DDR - * 0x00000000 256M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_256M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 4d57517dd..0f2e1df08 100644 --- a/boards.cfg +++ b/boards.cfg @@ -441,8 +441,6 @@ MVBLM7 powerpc mpc83xx mvblm7 matrix_ SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP TQM834x powerpc mpc83xx tqm834x tqc -PM854 powerpc mpc85xx pm854 -PM856 powerpc mpc85xx pm856 sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540 sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540 diff --git a/include/configs/PM854.h b/include/configs/PM854.h deleted file mode 100644 index 1e2089fb5..000000000 --- a/include/configs/PM854.h +++ /dev/null @@ -1,426 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * pm854 board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC8540 1 /* MPC8540 specific */ -#define CONFIG_PM854 1 /* PM854 board specific */ - -#define CONFIG_SYS_TEXT_BASE 0xfff80000 - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 -#endif - - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - - -/* DDR Setup */ -#define CONFIG_FSL_DDR1 -#undef CONFIG_FSL_DDR_INTERACTIVE -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x58 /* CTLR 0 DIMM 0 */ - -/* Manually set up DDR parameters */ -#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256 MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102 -#define CONFIG_SYS_DDR_TIMING_1 0x47444321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ -#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ - -#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of 32 MB FLASH */ -#define CONFIG_SYS_BR0_PRELIM 0xfe001801 /* port size 32bit */ - -#define CONFIG_SYS_OR0_PRELIM 0xfe006f67 /* 32 MB Flash */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#define CONFIG_EEPRO100 -#define CONFIG_E1000 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -#define CONFIG_MPC85XX_FEC 1 -#define CONFIG_MPC85XX_FEC_NAME "FEC" -#define FEC_PHY_ADDR 3 -#define FEC_PHYIDX 0 -#define FEC_FLAGS 0 - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 1 -#define CONFIG_HAS_ETH2 1 - -#endif /* CONFIG_TSEC_ENET */ - - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x80000) - #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_SAVEENV - #undef CONFIG_CMD_LOADS -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ -#define CONFIG_LOOPW - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:40:42:01:00:00 -#define CONFIG_ETH1ADDR 00:40:42:01:00:01 -#define CONFIG_ETH2ADDR 00:40:42:01:00:02 -#endif - - -#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx -#define CONFIG_BOOTFILE pm854/uImage - -#define CONFIG_HOSTNAME pm854 -#define CONFIG_IPADDR 192.168.0.103 -#define CONFIG_SERVERIP 192.168.0.64 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=pm854/uRamdisk\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/PM856.h b/include/configs/PM856.h deleted file mode 100644 index d3e8f412e..000000000 --- a/include/configs/PM856.h +++ /dev/null @@ -1,429 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * MicroSys PM856 board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -#define CONFIG_MPC8560 1 /* MPC8560 specific */ -#define CONFIG_CPM2 1 /* Has a CPM2 */ -#define CONFIG_PM856 1 /* PM856 board specific */ - -#define CONFIG_SYS_TEXT_BASE 0xfff80000 - -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66000000 -#endif - - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - -/* DDR Setup */ -#define CONFIG_FSL_DDR1 -#undef CONFIG_FSL_DDR_INTERACTIVE -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_FSL_DMA /* use DMA to init DDR ECC */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x58 /* CTLR 0 DIMM 0 */ - -/* Manually set up DDR parameters */ -#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256 MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-256MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102 -#define CONFIG_SYS_DDR_TIMING_1 0x47444321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ -#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */ - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ - -#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ -#define CONFIG_SYS_BR0_PRELIM 0xfe001801 /* port size 32bit */ - -#define CONFIG_SYS_OR0_PRELIM 0xfe006f67 /* 32MB Flash */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - - -/* - * Local Bus Definitions - */ - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - - -#if defined(CONFIG_TSEC_ENET) - -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -#endif /* CONFIG_TSEC_ENET */ - -#define CONFIG_ETHPRIME "TSEC0" - -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ - - -/* - * - Rx-CLK is CLK15 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ -#define CONFIG_ETHER_ON_FCC3 -#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x80000) - #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_SAVEENV - #undef CONFIG_CMD_LOADS -#endif - - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ -#define CONFIG_LOOPW - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:40:42:01:00:00 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:40:42:01:00:01 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:40:42:01:00:02 -#endif - - -#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx -#define CONFIG_BOOTFILE pm856/uImage - -#define CONFIG_HOSTNAME pm856 -#define CONFIG_IPADDR 192.168.0.103 -#define CONFIG_SERVERIP 192.168.0.64 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=pm856/uRamdisk\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ From f2cdf461b66c86945488ed431d171859356bb192 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Mon, 13 Dec 2010 14:46:43 -0500 Subject: [PATCH 04/63] MPC8xxx: Update maintainer entry for Wind River sbc8xxx boards I've probably got the best chance of getting access to these boards in order to test things, and since Joe's e-mail is bouncing, update the MAINTAINERS entry to reflect this. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- MAINTAINERS | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index dbae8102a..a79903747 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -198,6 +198,14 @@ Siddarth Gore guruplug ARM926EJS (Kirkwood SoC) +Paul Gortmaker + + sbc8349 MPC8349 + sbc8540 MPC8540 + sbc8548 MPC8548 + sbc8560 MPC8560 + sbc8641d MPC8641D + Frank Gottschling MHPC MPC8xx @@ -212,11 +220,6 @@ Wolfgang Grandegger IPHASE4539 MPC8260 SCM MPC8260 -Joe Hamman - - sbc8548 MPC8548 - sbc8641d MPC8641D - Klaus Heydeck KUP4K MPC855 From 2e81ad05d79328767803a4956b0ebe22e577366e Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Mon, 13 Dec 2010 15:06:44 -0600 Subject: [PATCH 05/63] socrates: rename sdram_setup fixed_sdram() This will help us go to a fixed initdram() for all 85xx boards going forward. sdram_setup() had an argument that it didn't need, since the value was #defined. Signed-off-by: Becky Bruce Signed-off-by: Kumar Gala --- board/socrates/sdram.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 029ba0298..ef897b216 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -39,7 +39,7 @@ * so this should be extended for other future boards * using this routine! */ -long int sdram_setup(int casl) +long int fixed_sdram(void) { volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); @@ -85,7 +85,7 @@ phys_size_t initdram (int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #else - dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL); + dram_size = fixed_sdram(); #endif return dram_size; } From d2d004a14fce207f82ef9a975cee4ed673e2f5f4 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Mon, 13 Dec 2010 15:06:45 -0600 Subject: [PATCH 06/63] mpc8569mds: Remove unnecessary CONFIG_SYS_LBC_SDRAM_BASE definition This isn't used - delete it. Signed-off-by: Becky Bruce Signed-off-by: Kumar Gala --- include/configs/MPC8569MDS.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 9620fd001..e64277e3f 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -263,12 +263,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ #endif -/* - * SDRAM on the LocalBus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ From 16dad759758009be79da9c3ce977191ac5a5162f Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Mon, 13 Dec 2010 15:06:48 -0600 Subject: [PATCH 07/63] MPC8568/MPC8569: Remove CONFIG_DDR_DLL define Neither of these parts should have the erratum this is meant to work around. Delete it. Signed-off-by: Becky Bruce Signed-off-by: Kumar Gala --- include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 281918bdc..7817fba2f 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -82,7 +82,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index e64277e3f..2395cb222 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -122,7 +122,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef From cb14e93b55b64feac556030e87835151cdc77be0 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 12 Nov 2010 08:22:01 -0600 Subject: [PATCH 08/63] powerpc/85xx: Add support for booting from NAND on MPC8572DS Mimic support that exists on MPC8536DS on the MPC8572DS to allow booting from NAND. Signed-off-by: Jin Qing Signed-off-by: Kumar Gala --- board/freescale/mpc8572ds/config.mk | 8 +- board/freescale/mpc8572ds/tlb.c | 14 +- boards.cfg | 1 + include/configs/MPC8572DS.h | 117 ++++++++++++--- nand_spl/board/freescale/mpc8572ds/Makefile | 133 ++++++++++++++++++ .../board/freescale/mpc8572ds/nand_boot.c | 82 +++++++++++ 6 files changed, 337 insertions(+), 18 deletions(-) create mode 100644 nand_spl/board/freescale/mpc8572ds/Makefile create mode 100644 nand_spl/board/freescale/mpc8572ds/nand_boot.c diff --git a/board/freescale/mpc8572ds/config.mk b/board/freescale/mpc8572ds/config.mk index 5413921a2..7fd64123d 100644 --- a/board/freescale/mpc8572ds/config.mk +++ b/board/freescale/mpc8572ds/config.mk @@ -1,5 +1,5 @@ # -# Copyright 2007-2008 Freescale Semiconductor, Inc. +# Copyright 2007-2008,2010 Freescale Semiconductor, Inc. # # See file CREDITS for list of people who contributed to this # project. @@ -23,4 +23,10 @@ # # mpc8572ds board # +ifndef NAND_SPL +ifeq ($(CONFIG_NAND), y) +LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds +endif +endif + RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 6a2a0b57f..575bdb55a 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -85,6 +85,18 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_4K, 1), + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, + CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_256K, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 0f2e1df08..3497408f3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -473,6 +473,7 @@ MPC8569MDS_ATM powerpc mpc85xx mpc8569mds freesca MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freescale - MPC8569MDS:NAND MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT +MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011 P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,NAND P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,SDCARD diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 1ee95aed2..9d2e209d6 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -33,6 +33,25 @@ #define CONFIG_PHYS_64BIT #endif +#ifdef CONFIG_NAND +#define CONFIG_NAND_U_BOOT +#define CONFIG_RAMBOOT_NAND +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ +#else +#define CONFIG_SYS_TEXT_BASE 0xf8f82000 +#endif /* CONFIG_NAND_SPL */ +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -41,10 +60,6 @@ #define CONFIG_MPC8572DS 1 #define CONFIG_MP 1 /* support multiple processors */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 -#endif - #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ @@ -80,11 +95,22 @@ #define CONFIG_SYS_MEMTEST_END 0x7fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ +/* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ @@ -93,6 +119,12 @@ #endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR +#else +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif + /* DDR Setup */ #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 @@ -177,8 +209,11 @@ #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 + +#define CONFIG_FLASH_BR_PRELIM \ + (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ + | BR_PS_16 | BR_V) +#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 @@ -193,7 +228,12 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#else +#undef CONFIG_SYS_RAMBOOT +#endif #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI @@ -246,6 +286,8 @@ #define PIXIS_VWATCH 0x24 /* Watchdog Register */ #define PIXIS_LED 0x25 /* LED Register */ +#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ + /* old pixis referenced names */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ @@ -277,12 +319,22 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ +#ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull #else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#endif + #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ CONFIG_SYS_NAND_BASE + 0x40000, \ CONFIG_SYS_NAND_BASE + 0x80000,\ @@ -293,6 +345,17 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START \ + (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) + + /* NAND flash config */ #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2< 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024)\ + + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif + +#else + #define CONFIG_ENV_IS_IN_FLASH 1 + #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 + #define CONFIG_ENV_ADDR 0xfff80000 + #else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #endif + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile new file mode 100644 index 000000000..e2181e969 --- /dev/null +++ b/nand_spl/board/freescale/mpc8572ds/Makefile @@ -0,0 +1,133 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# Copyright 2009-2010 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +NAND_SPL := y +CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000 +PAD_TO := 0xfff01000 + +include $(TOPDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o resetvec.o +COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \ + nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +$(obj)cache.c: + @rm -f $(obj)cache.c + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + +$(obj)cpu_init_early.c: + @rm -f $(obj)cpu_init_early.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + +$(obj)cpu_init_nand.c: + @rm -f $(obj)cpu_init_nand.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c + +$(obj)fsl_law.c: + @rm -f $(obj)fsl_law.c + ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c + +$(obj)law.c: + @rm -f $(obj)law.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + +$(obj)nand_boot_fsl_elbc.c: + @rm -f $(obj)nand_boot_fsl_elbc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ + $(obj)nand_boot_fsl_elbc.c + +$(obj)ns16550.c: + @rm -f $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S + +$(obj)fixed_ivor.S: + @rm -f $(obj)fixed_ivor.S + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + +$(obj)start.S: $(obj)fixed_ivor.S + @rm -f $(obj)start.S + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S + +$(obj)tlb.c: + @rm -f $(obj)tlb.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c + +$(obj)tlb_table.c: + @rm -f $(obj)tlb_table.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + +ifneq ($(OBJTREE), $(SRCTREE)) +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c +endif + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/mpc8572ds/nand_boot.c b/nand_spl/board/freescale/mpc8572ds/nand_boot.c new file mode 100644 index 000000000..7ca4d4dd3 --- /dev/null +++ b/nand_spl/board/freescale/mpc8572ds/nand_boot.c @@ -0,0 +1,82 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include + +u32 sysclk_tbl[] = { + 33333000, 39999600, 49999500, 66666000, + 83332500, 99999000, 133332000, 166665000 +}; + +void board_init_f(ulong bootflag) +{ + int px_spd; + u32 plat_ratio, bus_clk, sys_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) + /* for FPGA */ + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); +#else +#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined +#endif + + /* initialize selected port with appropriate baud rate */ + px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); + sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + bus_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} From 35079aa98c64b6739ea2fc5453b527a9bdf22b6c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 15 Dec 2010 03:50:47 -0600 Subject: [PATCH 09/63] powerpc/85xx: Replace CONFIG_SYS_HAS_SERDES with a weak function Instead of a #define use a null weak function for fsl_serdes_init Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 ++++++-- include/configs/MPC8536DS.h | 1 - include/configs/P1022DS.h | 1 - include/configs/corenet_ds.h | 1 - 4 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4b8faa5da..4a6cc6566 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -232,6 +232,12 @@ void cpu_init_f (void) invalidate_cpc(); } +/* Implement a dummy function for those platforms w/o SERDES */ +static void __fsl_serdes__init(void) +{ + return ; +} +__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); /* * Initialize L2 as cache. @@ -375,10 +381,8 @@ int cpu_init_r(void) qe_reset(); #endif -#if defined(CONFIG_SYS_HAS_SERDES) /* needs to be in ram since code uses global static vars */ fsl_serdes_init(); -#endif #if defined(CONFIG_MP) setup_mp(); diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 5c5be0ce9..7473834c5 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -78,7 +78,6 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_SYS_HAS_SERDES /* has SERDES */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 7e6c40fc6..272bd9ff6 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -34,7 +34,6 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_SYS_HAS_SERDES /* has SERDES */ #define CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 454a30a04..e1cd1b0b0 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -50,7 +50,6 @@ #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_SYS_HAS_SERDES /* has SERDES */ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ From c5780a6fe9e3f0a0f33d356d5047537ed113143c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 15 Dec 2010 04:07:55 -0600 Subject: [PATCH 10/63] powerpc/85xx: Create a SERDES section in Makefile Created a section in the Makefile for SoC specific SERDES code. Also added P1013 SERDES (use P1022 SERDES code). Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 63d79233d..e14ed01e6 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -66,8 +66,6 @@ COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_CORENET) += liodn.o COBJS-$(CONFIG_MP) += mp.o -COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o -COBJS-$(CONFIG_P1022) += p1022_serdes.o COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_FSL_CORENET) += portals.o @@ -77,6 +75,11 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o + +# SoC specific SERDES support +COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o +COBJS-$(CONFIG_P1013) += p1013_serdes.o +COBJS-$(CONFIG_P1022) += p1022_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS = $(COBJS-y) From af04247426e4e7ee5d0561a1bd34855665e72b31 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 15 Dec 2010 04:52:48 -0600 Subject: [PATCH 11/63] powerpc/86xx: Add SERDES support on MPC8641 & MPC8610 Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. This mimics the code we have in place for the 85xx platforms. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc86xx/Makefile | 2 + arch/powerpc/cpu/mpc86xx/cpu_init.c | 6 +- arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c | 85 ++++++++++++++++++++ arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c | 94 +++++++++++++++++++++++ 4 files changed, 186 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c create mode 100644 arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile index 5b7d80a5b..b4ef286af 100644 --- a/arch/powerpc/cpu/mpc86xx/Makefile +++ b/arch/powerpc/cpu/mpc86xx/Makefile @@ -42,6 +42,8 @@ COBJS-$(CONFIG_MPC8641) += ddr-8641.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-y += interrupts.o COBJS-$(CONFIG_MP) += mp.o +COBJS-$(CONFIG_MPC8610) += mpc8610_serdes.o +COBJS-$(CONFIG_MPC8641) += mpc8641_serdes.o COBJS-y += speed.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c index 82c216ba5..1d35c0c65 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc86xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2004,2009 Freescale Semiconductor, Inc. + * Copyright 2004,2009-2010 Freescale Semiconductor, Inc. * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -31,6 +31,7 @@ #include #include #include +#include #include void setup_bats(void); @@ -76,6 +77,9 @@ void cpu_init_f(void) */ int cpu_init_r(void) { + /* needs to be in ram since code uses global static vars */ + fsl_serdes_init(); + #if defined(CONFIG_MP) setup_mp(); #endif diff --git a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c new file mode 100644 index 000000000..0dc1975bf --- /dev/null +++ b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c @@ -0,0 +1,85 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 4 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x1] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x7] = {NONE, NONE, NONE, NONE}, +}; + +static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x0] = {PCIE2, PCIE2, PCIE2, PCIE2}, + [0x4] = {PCIE2, PCIE2, PCIE2, PCIE2}, + [0x7] = {NONE, NONE, NONE, NONE}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; + ccsr_gur_t *gur = &immap->im_gur; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC8610_PORDEVSR_IO_SEL) >> + MPC8610_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c new file mode 100644 index 000000000..3ae9069f1 --- /dev/null +++ b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c @@ -0,0 +1,94 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 4 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x3] = {PCIE2, PCIE2, PCIE2, PCIE2}, + [0x5] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0x6] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0x7] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0x9] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xa] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xb] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xe] = {PCIE2, PCIE2, PCIE2, PCIE2}, + [0xf] = {PCIE2, PCIE2, PCIE2, PCIE2}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; + ccsr_gur_t *gur = &immap->im_gur; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC8641_PORDEVSR_IO_SEL) >> + MPC8641_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } +} From 3818db43de4fa884eec20d1a640e45640295e1b4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 15 Dec 2010 02:49:03 -0600 Subject: [PATCH 12/63] powerpc/85xx: Add is_serdes_configured() support for P2020 SERDES Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Li Yang Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 2 + arch/powerpc/cpu/mpc85xx/p2020_serdes.c | 73 +++++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/p2020_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index e14ed01e6..a2c844d44 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -80,6 +80,8 @@ COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS-$(CONFIG_P1013) += p1013_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o +COBJS-$(CONFIG_P2010) += p2020_serdes.o +COBJS-$(CONFIG_P2020) += p2020_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS = $(COBJS-y) diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c new file mode 100644 index 000000000..389ff6bd2 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c @@ -0,0 +1,73 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x0] = {PCIE1, NONE, NONE, NONE}, + [0x2] = {PCIE1, PCIE2, PCIE3, PCIE3}, + [0x4] = {PCIE1, PCIE1, PCIE3, PCIE3}, + [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x7] = {SRIO2, SRIO1, NONE, NONE}, + [0x8] = {SRIO2, SRIO2, SRIO2, SRIO2}, + [0x9] = {SRIO2, SRIO2, SRIO2, SRIO2}, + [0xa] = {SRIO2, SRIO2, SRIO2, SRIO2}, + [0xb] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3}, + [0xc] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3}, + [0xd] = {PCIE1, SRIO1, SGMII_TSEC2, SGMII_TSEC3}, + [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, + [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} From af87cab6777c607f094be7e6f9eb4f1271c451c6 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 26 Apr 2010 23:09:23 -0500 Subject: [PATCH 13/63] powerpc/85xx: Add is_serdes_configured() support for MPC8572 SERDES Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Chenhui Zhao Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 1 + arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c | 81 +++++++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index a2c844d44..9ec19bb12 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -78,6 +78,7 @@ COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o # SoC specific SERDES support COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o +COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o COBJS-$(CONFIG_P1013) += p1013_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c new file mode 100644 index 000000000..2ff5d9a06 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c @@ -0,0 +1,81 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define SRDS1_MAX_LANES 8 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3}, + [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0xc] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0xd] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0xe] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + serdes1_prtcl_map |= (1 << SGMII_TSEC1); + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + serdes1_prtcl_map |= (1 << SGMII_TSEC2); + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + serdes1_prtcl_map |= (1 << SGMII_TSEC3); + + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) + serdes1_prtcl_map |= (1 << SGMII_TSEC4); +} From bc48d0d5036f5759688f0902e8a652d372186eda Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 26 Apr 2010 23:25:33 -0500 Subject: [PATCH 14/63] powerpc/85xx: Add is_serdes_configured() support for MPC8548 SERDES Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 1 + arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c | 65 +++++++++++++++++++++++ 2 files changed, 66 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 9ec19bb12..e1320bf15 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -78,6 +78,7 @@ COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o # SoC specific SERDES support COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o +COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o COBJS-$(CONFIG_P1013) += p1013_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c new file mode 100644 index 000000000..76288cd56 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c @@ -0,0 +1,65 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define SRDS1_MAX_LANES 8 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg); + + if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg); + return ; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} From 5ba40eec72a1e45a262c4c8a6aa20760e61fb7ec Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 26 Apr 2010 23:44:10 -0500 Subject: [PATCH 15/63] powerpc/85xx: Add is_serdes_configured() support for MPC8568 SERDES Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 1 + arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c | 65 +++++++++++++++++++++++ 2 files changed, 66 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index e1320bf15..3c7542969 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -79,6 +79,7 @@ COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o # SoC specific SERDES support COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o +COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o COBJS-$(CONFIG_P1013) += p1013_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c new file mode 100644 index 000000000..258263739 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c @@ -0,0 +1,65 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define SRDS1_MAX_LANES 8 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} From 47567c266363e1c3be9e6e2ad37286970304d180 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 27 Apr 2010 00:05:41 -0500 Subject: [PATCH 16/63] powerpc/85xx: Add is_serdes_configured() support for MPC8569 SERDES Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 1 + arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c | 74 +++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 3c7542969..78bc27abf 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -80,6 +80,7 @@ COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o +COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o COBJS-$(CONFIG_P1013) += p1013_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c new file mode 100644 index 000000000..f480c2609 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c @@ -0,0 +1,74 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x0] = {PCIE1, NONE, NONE, NONE}, + [0x1] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2}, + [0x2] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2}, + [0x3] = {SRIO1, SRIO2, NONE, NONE}, + [0x4] = {PCIE1, NONE, SGMII_TSEC1, SGMII_TSEC2}, + [0x5] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x6] = {PCIE1, NONE, SRIO1, SRIO2}, + [0x7] = {PCIE1, PCIE1, SRIO1, SRIO2}, + [0x8] = {PCIE1, PCIE1, SRIO1, SRIO2}, + [0x9] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xa] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xb] = {SRIO1, SRIO1, SRIO1, SRIO1}, + [0xc] = {PCIE1, SRIO1, SGMII_TSEC1, SGMII_TSEC2}, + [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} From 877a26112db880ecb978a6c9ad1f230cd838fe58 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 27 Apr 2010 09:20:20 -0500 Subject: [PATCH 17/63] powerpc/85xx: Add is_serdes_configured() support for MPC8544 SERDES Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 1 + arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c | 95 +++++++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 78bc27abf..dbb53c897 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -78,6 +78,7 @@ COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o # SoC specific SERDES support COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o +COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c new file mode 100644 index 000000000..7c490972a --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c @@ -0,0 +1,95 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define SRDS1_MAX_LANES 8 +#define SRDS2_MAX_LANES 4 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, + [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE}, + [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, + [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}, +}; + +static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x1] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3}, + [0x3] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3}, + [0x5] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3}, + [0x6] = {PCIE3, NONE, NONE, NONE}, + [0x7] = {PCIE3, NONE, SGMII_TSEC1, SGMII_TSEC3}, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } + + if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) + serdes2_prtcl_map &= ~(1 << SGMII_TSEC1); + + if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS) + serdes2_prtcl_map &= ~(1 << SGMII_TSEC3); +} From 70ea7f82ed166a96869abf11d6299cb55b49c200 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 15 Dec 2010 04:04:56 -0600 Subject: [PATCH 18/63] powerpc/85xx: Add is_serdes_configured() support for P1021 SERDES Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 4 ++ arch/powerpc/cpu/mpc85xx/p1021_serdes.c | 64 +++++++++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/p1021_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index dbb53c897..af7bc09b9 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -83,7 +83,11 @@ COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o +COBJS-$(CONFIG_P1011) += p1021_serdes.o +COBJS-$(CONFIG_P1012) += p1021_serdes.o COBJS-$(CONFIG_P1013) += p1013_serdes.o +COBJS-$(CONFIG_P1020) += p1021_serdes.o +COBJS-$(CONFIG_P1021) += p1021_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c new file mode 100644 index 000000000..457ab5dca --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c @@ -0,0 +1,64 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x0] = {PCIE1, NONE, NONE, NONE}, + [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, + [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3}, +}; + +int is_serdes_configured(enum srds_prtcl prtcl) +{ + return (1 << prtcl) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} From afabe4b94e35af74f3dfc13d833bf47d367c2051 Mon Sep 17 00:00:00 2001 From: Piergiorgio Beruto Date: Tue, 4 Jan 2011 14:32:15 +0100 Subject: [PATCH 19/63] powerpc/85xx: Fix wrong SVR value for MPC8567 and MPC8567E processors Signed-off-by: Piergiorgio Beruto Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/processor.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 9cafe85f1..71fafa30d 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1030,8 +1030,8 @@ #define SVR_8555 0x807100 #define SVR_8555_E 0x807900 #define SVR_8560 0x807000 -#define SVR_8567 0x807600 -#define SVR_8567_E 0x807E00 +#define SVR_8567 0x807501 +#define SVR_8567_E 0x807D01 #define SVR_8568 0x807500 #define SVR_8568_E 0x807D00 #define SVR_8569 0x808000 From a6da8b8195f47a70106f743948f2729d94157b32 Mon Sep 17 00:00:00 2001 From: Chenhui Zhao Date: Tue, 4 Jan 2011 17:23:05 +0800 Subject: [PATCH 20/63] fsl_esdhc: Fix esdhc disabled problem on some platforms Some new platform's esdhc pins don't share with other function. The eSDHC shouldn't be disabled, even if "esdhc" isn't defined in hwconfig env variable. Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem. Signed-off-by: Chenhui Zhao Signed-off-by: Li Yang Signed-off-by: Kumar Gala --- drivers/mmc/fsl_esdhc.c | 14 ++++++++------ include/configs/MPC837XEMDS.h | 1 + include/configs/MPC837XERDB.h | 1 + include/configs/MPC8569MDS.h | 1 + 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 40b136c17..cef2859ec 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -508,17 +508,19 @@ int fsl_esdhc_mmc_init(bd_t *bis) void fdt_fixup_esdhc(void *blob, bd_t *bd) { const char *compat = "fsl,esdhc"; - const char *status = "okay"; +#ifdef CONFIG_FSL_ESDHC_PIN_MUX if (!hwconfig("esdhc")) { - status = "disabled"; - goto out; + do_fixup_by_compat(blob, compat, "status", "disabled", + 8 + 1, 1); + return; } +#endif do_fixup_by_compat_u32(blob, compat, "clock-frequency", gd->sdhc_clk, 1); -out: - do_fixup_by_compat(blob, compat, "status", status, - strlen(status) + 1, 1); + + do_fixup_by_compat(blob, compat, "status", "okay", + 4 + 1, 1); } #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index c237991ad..abccfd643 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -509,6 +509,7 @@ extern int board_pci_host_broken(void); #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC +#define CONFIG_FSL_ESDHC_PIN_MUX #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 385c7c321..ea3056b93 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -517,6 +517,7 @@ #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC +#define CONFIG_FSL_ESDHC_PIN_MUX #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 2395cb222..177d5d536 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -554,6 +554,7 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC +#define CONFIG_FSL_ESDHC_PIN_MUX #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC From 5d27e02c04f8fef38341e58475a988f8b2c78b9f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 15 Dec 2010 04:55:20 -0600 Subject: [PATCH 21/63] powerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configured Now that we have serdes support for all 85xx/86xx/Pxxx chips we can replace the is_fsl_pci_cfg() code with the is_serdes_configured(). Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/Makefile | 1 - arch/powerpc/cpu/mpc8xxx/pci_cfg.c | 204 ---------------------- arch/powerpc/include/asm/fsl_pci.h | 2 - board/freescale/mpc8544ds/mpc8544ds.c | 7 +- board/freescale/mpc8548cds/mpc8548cds.c | 3 +- board/freescale/mpc8568mds/mpc8568mds.c | 3 +- board/freescale/mpc8569mds/mpc8569mds.c | 3 +- board/freescale/mpc8572ds/mpc8572ds.c | 7 +- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 11 +- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 5 +- board/freescale/p1_p2_rdb/pci.c | 10 +- board/freescale/p2020ds/p2020ds.c | 7 +- board/sbc8548/sbc8548.c | 3 +- board/sbc8641d/sbc8641d.c | 5 +- board/tqc/tqm85xx/tqm85xx.c | 5 +- board/xes/common/fsl_8xxx_pci.c | 11 +- 16 files changed, 39 insertions(+), 248 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc8xxx/pci_cfg.c diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index ab80dd772..95c73be88 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -12,7 +12,6 @@ LIB = $(obj)lib8xxx.o ifneq ($(CPU),mpc83xx) COBJS-y += cpu.o -COBJS-$(CONFIG_PCI) += pci_cfg.o endif COBJS-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c deleted file mode 100644 index 53236a36f..000000000 --- a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -struct pci_info { - u32 cfg; -}; - -/* The cfg field is a bit mask in which each bit represents the value of - * cfg_IO_ports[] signal and the bit is set if the interface would be - * enabled based on the value of cfg_IO_ports[] signal - * - * On MPC86xx/PQ3 based systems: - * we extract cfg_IO_ports from GUTS register PORDEVSR - * - * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems - * without PCIe) - */ - -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, -}; -#elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, -}; -#elif defined(CONFIG_MPC8536) -static struct pci_info pci_config_info[] = -{ -}; -#elif defined(CONFIG_MPC8544) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | - (1 << 6) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 6) | (1 << 7), - }, -}; -#elif defined(CONFIG_MPC8548) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI_1] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCI_2] = { - .cfg = 0, - }, - /* PCI_2 is always host and we dont use iosel to determine enable/disable */ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 3) | (1 << 4) | (1 << 7), - }, -}; -#elif defined(CONFIG_MPC8568) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 3) | (1 << 4) | (1 << 7), - }, -}; -#elif defined(CONFIG_MPC8569) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | - (1 << 8) | (1 << 0xc) | (1 << 0xf), - }, -}; -#elif defined(CONFIG_MPC8572) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 2) | (1 << 3) | (1 << 7) | - (1 << 0xb) | (1 << 0xc) | (1 << 0xf), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 3) | (1 << 7), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 7), - }, -}; -#elif defined(CONFIG_MPC8610) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCI_1] = { - .cfg = 0, - }, - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 1) | (1 << 4), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 0) | (1 << 4), - }, -}; -#elif defined(CONFIG_MPC8641) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | - (1 << 7) | (1 << 0xf), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 3) | (1 << 0xe) | (1 << 0xf), - }, -}; -#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ - defined(CONFIG_P1012) || defined(CONFIG_P1021) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 0xe), - }, -}; -#elif defined(CONFIG_P1013) || defined(CONFIG_P1022) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xa) | - (1 << 0xb) | (1 << 0xd) | (1 << 0xe) | - (1 << 0xf) | (1 << 0x15) | (1 << 0x16) | - (1 << 0x17) | (1 << 0x18) | (1 << 0x19) | - (1 << 0x1a) | (1 << 0x1b) | (1 << 0x1c) | - (1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) | - (1 << 0xd) | (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | - (1 << 0x18) | (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) | - (1 << 0xa) | (1 << 0xb) | (1 << 0xd) | (1 << 0x15) | - (1 << 0x16) | (1 << 0x17) | (1 << 0x18) | (1 << 0x1c), - }, -}; -#elif defined(CONFIG_P2010) || defined(CONFIG_P2020) -static struct pci_info pci_config_info[] = -{ - [LAW_TRGT_IF_PCIE_1] = { - .cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) | - (1 << 0xd) | (1 << 0xe) | (1 << 0xf), - }, - [LAW_TRGT_IF_PCIE_2] = { - .cfg = (1 << 2) | (1 << 0xe), - }, - [LAW_TRGT_IF_PCIE_3] = { - .cfg = (1 << 2) | (1 << 4), - }, -}; -#elif defined(CONFIG_FSL_CORENET) -#else -#error Need to define pci_config_info for processor -#endif - -#ifndef CONFIG_FSL_CORENET -int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel) -{ - return ((1 << io_sel) & pci_config_info[trgt].cfg); -} -#endif diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index dc5c579e1..fa035142f 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -23,8 +23,6 @@ #include -int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel); - int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 31c3fad86..3285ceaa1 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -127,7 +128,7 @@ void pci_init_board(void) puts("\n"); #ifdef CONFIG_PCIE3 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + pcie_configured = is_serdes_configured(PCIE3); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ SET_STD_PCIE_INFO(pci_info[num], 3); @@ -162,7 +163,7 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); @@ -193,7 +194,7 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE2 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + pcie_configured = is_serdes_configured(PCIE2); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ SET_STD_PCIE_INFO(pci_info[num], 2); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 14c902cb9..ebeb89749 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -332,7 +333,7 @@ void pci_init_board(void) #endif /* CONFIG_PCI2 */ #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index d74fcac98..71cfbf0f3 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -399,7 +400,7 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index dc0884e7b..9700b8c6e 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -579,7 +580,7 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 120f35c2c..15a4d316c 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -187,7 +188,7 @@ void pci_init_board(void) puts("\n"); #ifdef CONFIG_PCIE3 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + pcie_configured = is_serdes_configured(PCIE3); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ SET_STD_PCIE_INFO(pci_info[num], 3); @@ -219,7 +220,7 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE2 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + pcie_configured = is_serdes_configured(PCIE2); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ SET_STD_PCIE_INFO(pci_info[num], 2); @@ -239,7 +240,7 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 61a635de7..8abd91788 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -225,7 +226,7 @@ void pci_init_board(void) volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; struct fsl_pci_info pci_info[3]; - u32 devdisr, pordevsr, io_sel; + u32 devdisr, pordevsr; int first_free_busno = 0; int num = 0; @@ -233,13 +234,9 @@ void pci_init_board(void) devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); - io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL) - >> MPC8610_PORDEVSR_IO_SEL_SHIFT; - - debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){ SET_STD_PCIE_INFO(pci_info[num], 1); @@ -260,7 +257,7 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE2 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + pcie_configured = is_serdes_configured(PCIE2); if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){ SET_STD_PCIE_INFO(pci_info[num], 2); diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 882ff0bf2..e95102170 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -147,9 +148,7 @@ void pci_init_board(void) volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; uint devdisr = in_be32(&gur->devdisr); - uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) - >> MPC8641_PORDEVSR_IO_SEL_SHIFT; - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + int pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { SET_STD_PCIE_INFO(pci_info[num], 1); diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index 2a2d6b702..e95431b7a 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -43,7 +44,7 @@ void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info[2]; - u32 devdisr, pordevsr, io_sel; + u32 devdisr, pordevsr; int first_free_busno = 0; int num = 0; @@ -51,16 +52,13 @@ void pci_init_board(void) devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - - debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf("eTSEC2 is in sgmii mode.\n"); puts("\n"); #ifdef CONFIG_PCIE2 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + pcie_configured = is_serdes_configured(PCIE2); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 2); @@ -79,7 +77,7 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index b05ef989b..a40be1390 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -210,7 +211,7 @@ void pci_init_board(void) puts("\n"); #ifdef CONFIG_PCIE2 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + pcie_configured = is_serdes_configured(PCIE2); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { SET_STD_PCIE_INFO(pci_info[num], 2); @@ -250,7 +251,7 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE3 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + pcie_configured = is_serdes_configured(PCIE3); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { SET_STD_PCIE_INFO(pci_info[num], 3); @@ -269,7 +270,7 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { SET_STD_PCIE_INFO(pci_info[num], 1); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 272428fbf..06c1eea37 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -364,7 +365,7 @@ pci_init_board(void) setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */ #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 5bf2364ee..5ee8f73c2 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include @@ -210,13 +211,11 @@ void pci_init_board(void) volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; uint devdisr = in_be32(&gur->devdisr); - uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) - >> MPC8641_PORDEVSR_IO_SEL_SHIFT; int pcie_ep; int num = 0; #ifdef CONFIG_PCIE1 - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + int pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { SET_STD_PCIE_INFO(pci_info[num], 1); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 527af6dd2..43c73e19e 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include @@ -555,8 +556,6 @@ void pci_init_board (void) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 devdisr = in_be32(&gur->devdisr); u32 pordevsr = in_be32(&gur->pordevsr); - __maybe_unused uint io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; #ifdef CONFIG_PCI1 uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; @@ -598,7 +597,7 @@ void pci_init_board (void) #endif #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { SET_STD_PCIE_INFO(pci_info[num], 1); diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c index 4a0965bf0..4135849f1 100644 --- a/board/xes/common/fsl_8xxx_pci.c +++ b/board/xes/common/fsl_8xxx_pci.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -81,11 +82,9 @@ void pci_init_board(void) volatile ccsr_gur_t *gur = &immap->im_gur; #endif u32 devdisr = in_be32(&gur->devdisr); - u32 pordevsr = in_be32(&gur->pordevsr); - __maybe_unused uint io_sel = (pordevsr & MPC8xxx_PORDEVSR_IO_SEL) >> - MPC8xxx_PORDEVSR_IO_SEL_SHIFT; #ifdef CONFIG_PCI1 + u32 pordevsr = in_be32(&gur->pordevsr); uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD; uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; @@ -114,7 +113,7 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) { SET_STD_PCIE_INFO(pci_info[num], 1); @@ -131,7 +130,7 @@ void pci_init_board(void) #endif /* CONFIG_PCIE1 */ #ifdef CONFIG_PCIE2 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + pcie_configured = is_serdes_configured(PCIE2); if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) { SET_STD_PCIE_INFO(pci_info[num], 2); @@ -148,7 +147,7 @@ void pci_init_board(void) #endif /* CONFIG_PCIE2 */ #ifdef CONFIG_PCIE3 - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + pcie_configured = is_serdes_configured(PCIE3); if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) { SET_STD_PCIE_INFO(pci_info[num], 3); From 058d7dc7ba28a45ae6bb7f6ef12b978b31584406 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 16 Dec 2010 14:28:06 -0600 Subject: [PATCH 22/63] powerpc/85xx: Cleanup SGMII detection and reporting Use new is_serdes_configured to determine if TSECs are in SGMII mode and report that on the various boards that use or can be configured in SGMII mode in board_eth_init() instead of in the PCI init code. Signed-off-by: Kumar Gala --- board/freescale/mpc8536ds/mpc8536ds.c | 27 +++++++++------------------ board/freescale/mpc8544ds/mpc8544ds.c | 20 +++++++++----------- board/freescale/mpc8572ds/mpc8572ds.c | 26 ++++++++++++-------------- board/freescale/p1_p2_rdb/p1_p2_rdb.c | 8 ++++---- board/freescale/p1_p2_rdb/pci.c | 3 --- board/freescale/p2020ds/p2020ds.c | 14 ++++++-------- 6 files changed, 40 insertions(+), 58 deletions(-) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index cf92ba121..bd80cb776 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -194,7 +194,7 @@ void pci_init_board(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info[4]; - u32 devdisr, pordevsr, io_sel, sdrs2_io_sel; + u32 devdisr, pordevsr, io_sel; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; int first_free_busno = 0; int num = 0; @@ -205,18 +205,8 @@ void pci_init_board(void) pordevsr = in_be32(&gur->pordevsr); porpllsr = in_be32(&gur->porpllsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; - debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n", - devdisr, sdrs2_io_sel, io_sel); - - if (sdrs2_io_sel == 7) - printf("Serdes2 disalbed\n"); - else if (sdrs2_io_sel == 4) { - printf("eTSEC1 is in sgmii mode.\n"); - printf("eTSEC3 is in sgmii mode.\n"); - } else if (sdrs2_io_sel == 6) - printf("eTSEC1 is in sgmii mode.\n"); + debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); puts("\n"); #ifdef CONFIG_PCIE3 @@ -354,14 +344,12 @@ int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET struct tsec_info_struct tsec_info[2]; - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; - uint sdrs2_io_sel = - (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); - if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { + if (is_serdes_configured(SGMII_TSEC1)) { + puts("eTSEC1 is in sgmii mode.\n"); tsec_info[num].phyaddr = 0; tsec_info[num].flags |= TSEC_SGMII; } @@ -369,7 +357,8 @@ int board_eth_init(bd_t *bis) #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); - if (sdrs2_io_sel == 4) { + if (is_serdes_configured(SGMII_TSEC3)) { + puts("eTSEC3 is in sgmii mode.\n"); tsec_info[num].phyaddr = 1; tsec_info[num].flags |= TSEC_SGMII; } @@ -382,8 +371,10 @@ int board_eth_init(bd_t *bis) } #ifdef CONFIG_FSL_SGMII_RISER - if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) + if (is_serdes_configured(SGMII_TSEC1) || + is_serdes_configured(SGMII_TSEC3)) { fsl_sgmii_riser_init(tsec_info, num); + } #endif tsec_eth_init(bis, tsec_info, num); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 3285ceaa1..2b6900c08 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -119,12 +119,6 @@ void pci_init_board(void) debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - if (io_sel & 1) { - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) - printf("eTSEC1 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) - printf("eTSEC3 is in sgmii mode.\n"); - } puts("\n"); #ifdef CONFIG_PCIE3 @@ -324,20 +318,22 @@ int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET struct tsec_info_struct tsec_info[2]; - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; int num = 0; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + if (is_serdes_configured(SGMII_TSEC1)) { + puts("eTSEC1 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + if (is_serdes_configured(SGMII_TSEC3)) { + puts("eTSEC3 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif @@ -347,8 +343,10 @@ int board_eth_init(bd_t *bis) return 0; } - if (io_sel & 1) + if (is_serdes_configured(SGMII_TSEC1) || + is_serdes_configured(SGMII_TSEC3)) { fsl_sgmii_riser_init(tsec_info, num); + } tsec_eth_init(bis, tsec_info, num); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 15a4d316c..c217c278e 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -177,15 +177,6 @@ void pci_init_board(void) debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) - printf("eTSEC1 is in sgmii mode.\n"); - if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) - printf("eTSEC2 is in sgmii mode.\n"); - if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) - printf("eTSEC3 is in sgmii mode.\n"); - if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) - printf("eTSEC4 is in sgmii mode.\n"); - puts("\n"); #ifdef CONFIG_PCIE3 pcie_configured = is_serdes_configured(PCIE3); @@ -289,31 +280,38 @@ int board_early_init_r(void) int board_eth_init(bd_t *bis) { struct tsec_info_struct tsec_info[4]; - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + if (is_serdes_configured(SGMII_TSEC1)) { + puts("eTSEC1 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + if (is_serdes_configured(SGMII_TSEC2)) { + puts("eTSEC2 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + if (is_serdes_configured(SGMII_TSEC3)) { + puts("eTSEC3 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif #ifdef CONFIG_TSEC4 SET_STD_TSEC_INFO(tsec_info[num], 4); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) + if (is_serdes_configured(SGMII_TSEC4)) { + puts("eTSEC4 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 1c4c0200e..440fcb924 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -166,10 +167,8 @@ int board_early_init_r(void) int board_eth_init(bd_t *bis) { struct tsec_info_struct tsec_info[4]; - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; char *tmp; - u32 pordevsr; unsigned int vscfw_addr; #ifdef CONFIG_TSEC1 @@ -182,9 +181,10 @@ int board_eth_init(bd_t *bis) #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); - pordevsr = in_be32(&gur->pordevsr); - if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + if (is_serdes_configured(SGMII_TSEC3)) { + puts("eTSEC3 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif if (!num) { diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index e95431b7a..2034459b6 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -53,9 +53,6 @@ void pci_init_board(void) devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); - if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) - printf("eTSEC2 is in sgmii mode.\n"); - puts("\n"); #ifdef CONFIG_PCIE2 pcie_configured = is_serdes_configured(PCIE2); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index a40be1390..07b08014d 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -204,11 +204,6 @@ void pci_init_board(void) debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) - printf("eTSEC2 is in sgmii mode.\n"); - if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) - printf("eTSEC3 is in sgmii mode.\n"); - puts("\n"); #ifdef CONFIG_PCIE2 pcie_configured = is_serdes_configured(PCIE2); @@ -318,7 +313,6 @@ int board_early_init_r(void) int board_eth_init(bd_t *bis) { struct tsec_info_struct tsec_info[4]; - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; #ifdef CONFIG_TSEC1 @@ -327,14 +321,18 @@ int board_eth_init(bd_t *bis) #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + if (is_serdes_configured(SGMII_TSEC2)) { + puts("eTSEC2 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; + } num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + if (is_serdes_configured(SGMII_TSEC3)) { + puts("eTSEC3 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; +} num++; #endif From 5b297d1a4269308a459d123cfb91a3c91f57337c Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Fri, 17 Dec 2010 17:17:54 -0600 Subject: [PATCH 23/63] tqm85xx: create fixed_sdram() to do sdram setup Also, change this code to use phys_size_t instead of long int. Using common naming for this function will enable us to use the common initdram() for 85xx going forward. Other than the type change, this is just a code rearrange. Signed-off-by: Becky Bruce Acked-by: Stefan Roese Signed-off-by: Kumar Gala --- board/tqc/tqm85xx/sdram.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 503c5e530..260cd1c6d 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -65,6 +65,7 @@ sdram_conf_t ddr_cs_conf[] = { #define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0])) int cas_latency (void); +static phys_size_t sdram_setup(int); /* * Autodetect onboard DDR SDRAM on 85xx platforms @@ -73,7 +74,26 @@ int cas_latency (void); * so this should be extended for other future boards * using this routine! */ -long int sdram_setup (int casl) +phys_size_t fixed_sdram(void) +{ + int casl = 0; + phys_size_t dram_size = 0; + + casl = cas_latency(); + dram_size = sdram_setup(casl); + if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { + /* + * Try again with default CAS latency + */ + printf("Problem with CAS lantency, using default CL %d/10!\n", + CONFIG_DDR_DEFAULT_CL); + dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL); + puts(" "); + } + return dram_size; +} + +static phys_size_t sdram_setup(int casl) { int i; volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); @@ -376,8 +396,7 @@ long int sdram_setup (int casl) phys_size_t initdram (int board_type) { - long dram_size = 0; - int casl; + phys_size_t dram_size = 0; #if defined(CONFIG_DDR_DLL) /* @@ -407,17 +426,7 @@ phys_size_t initdram (int board_type) } #endif - casl = cas_latency (); - dram_size = sdram_setup (casl); - if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { - /* - * Try again with default CAS latency - */ - printf ("Problem with CAS lantency, using default CL %d/10!\n", - CONFIG_DDR_DEFAULT_CL); - dram_size = sdram_setup (CONFIG_DDR_DEFAULT_CL); - puts (" "); - } + dram_size = fixed_sdram(); return dram_size; } From 6b1ef2a6a553c33e74c5e50c77b55d40af669be3 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Fri, 17 Dec 2010 17:17:55 -0600 Subject: [PATCH 24/63] mpc85xx/tlb.c: Allow platforms to specify wimge bits Some platforms might want to override the default wimge=0 for DDR. Add CONFIG_SYS_PPC_DDR_WIMGE for those platforms to use. This will initially only be used by TQM85xx, but could be useful for other boards or testing going forward. Note that the name of this define is not 85xx-specific. WIMGE is a fairly universal concept, so any ppc platforms that require different WIMGE settings for DDR can use the same #define. Signed-off-by: Becky Bruce Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/tlb.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index e3a71aec5..31143ba53 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -250,10 +250,14 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { int i; unsigned int tlb_size; + unsigned int wimge = 0; unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; u64 size, memsize = (u64)memsize_in_meg << 20; +#ifdef CONFIG_SYS_PPC_DDR_WIMGE + wimge = CONFIG_SYS_PPC_DDR_WIMGE; +#endif size = min(memsize, CONFIG_MAX_MEM_MAPPED); /* Convert (4^max) kB to (2^max) bytes */ @@ -277,7 +281,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) tlb_size = (camsize - 10) / 2; set_tlb(1, ram_tlb_address, p_addr, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, wimge, 0, ram_tlb_index, tlb_size, 1); size -= 1ULL << camsize; From 38dba0c2ff685e3f8276a236bd70eaa09c84ead5 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Fri, 17 Dec 2010 17:17:56 -0600 Subject: [PATCH 25/63] mpc85xx boards: initdram() cleanup/bugfix Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences: 1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner. 2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad. The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c Signed-off-by: Becky Bruce Tested-by: Paul Gortmaker Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu.c | 52 +++++++++++++ arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 10 +++ arch/powerpc/include/asm/fsl_ddr_sdram.h | 13 ++++ arch/powerpc/include/asm/fsl_lbc.h | 4 + board/freescale/mpc8536ds/mpc8536ds.c | 21 ------ board/freescale/mpc8540ads/mpc8540ads.c | 52 +------------ board/freescale/mpc8540ads/tlb.c | 19 ----- board/freescale/mpc8541cds/mpc8541cds.c | 43 ----------- board/freescale/mpc8544ds/mpc8544ds.c | 17 ----- board/freescale/mpc8548cds/mpc8548cds.c | 38 ---------- board/freescale/mpc8555cds/mpc8555cds.c | 45 ------------ board/freescale/mpc8560ads/mpc8560ads.c | 52 +------------ board/freescale/mpc8560ads/tlb.c | 19 ----- board/freescale/mpc8568mds/mpc8568mds.c | 38 ---------- board/freescale/mpc8569mds/mpc8569mds.c | 36 --------- board/freescale/mpc8572ds/mpc8572ds.c | 19 ----- board/freescale/p1022ds/p1022ds.c | 13 ---- board/freescale/p1_p2_rdb/ddr.c | 15 +--- board/freescale/p2020ds/p2020ds.c | 34 ++------- board/sbc8548/sbc8548.c | 45 +----------- board/sbc8548/tlb.c | 34 +++------ board/sbc8560/sbc8560.c | 93 +----------------------- board/socrates/sdram.c | 15 +--- board/stx/stxgp3/stxgp3.c | 32 -------- board/stx/stxssa/stxssa.c | 33 --------- board/tqc/tqm85xx/sdram.c | 37 ---------- board/tqc/tqm85xx/tlb.c | 47 ------------ board/xes/common/Makefile | 2 - board/xes/common/fsl_8xxx_ddr.c | 46 ------------ board/xes/xpedite517x/xpedite517x.c | 13 ++++ include/configs/TQM85xx.h | 4 + 31 files changed, 121 insertions(+), 820 deletions(-) delete mode 100644 board/xes/common/fsl_8xxx_ddr.c diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 55ee36d0b..bea8e10af 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -286,6 +287,57 @@ void mpc85xx_reginfo(void) print_lbc_regs(); } +/* Common ddr init for non-corenet fsl 85xx platforms */ +#ifndef CONFIG_FSL_CORENET +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + +#if defined(CONFIG_DDR_DLL) + { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned int x = 10; + unsigned int i; + + /* + * Work around to stabilize DDR DLL + */ + out_be32(&gur->ddrdllcr, 0x81000000); + asm("sync;isync;msync"); + udelay(200); + while (in_be32(&gur->ddrdllcr) != 0x81000100) { + setbits_be32(&gur->devdisr, 0x00010000); + for (i = 0; i < x; i++) + ; + clrbits_be32(&gur->devdisr, 0x00010000); + x++; + } + } +#endif + +#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) + dram_size = fsl_ddr_sdram(); +#else + dram_size = fixed_sdram(); +#endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + /* Some boards also have sdram on the lbc */ + sdram_init(); + + puts("DDR: "); + return dram_size; +} +#endif + #if CONFIG_POST & CONFIG_SYS_POST_MEMORY /* Board-specific functions defined in each board's ddr.c */ diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index fcef40c5b..10fcd243f 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -9,6 +9,16 @@ #include #include +#ifdef CONFIG_MPC85xx +/* Boards should provide their own version of this if they use lbc sdram */ +void __sdram_init(void) +{ + /* Do nothing */ +} +void sdram_init(void) __attribute__((weak, alias("__sdram_init"))); +#endif + + void print_lbc_regs(void) { int i; diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 17d4b319b..8ceae1845 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -214,6 +214,19 @@ typedef struct memctl_options_s { extern phys_size_t fsl_ddr_sdram(void); +/* + * The 85xx boards have a common prototype for fixed_sdram so put the + * declaration here. + */ +#ifdef CONFIG_MPC85xx +extern phys_size_t fixed_sdram(void); +#endif + +#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + + typedef struct fixed_ddr_parm{ int min_freq; int max_freq; diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 82d24ab13..fcf3371f5 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -16,6 +16,10 @@ #include #include +#ifdef CONFIG_MPC85xx +void sdram_init(void); +#endif + /* BR - Base Registers */ #define BR0 0x5000 /* Register offset to immr */ diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index bd80cb776..58dc564ee 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -42,8 +42,6 @@ #include "../common/sgmii_riser.h" -phys_size_t fixed_sdram(void); - int board_early_init_f (void) { #ifdef CONFIG_MMC @@ -98,25 +96,6 @@ int checkboard (void) return 0; } -phys_size_t -initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing...."); - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} - #if !defined(CONFIG_SPD_EEPROM) /* * Fixed sdram init -- doesn't use serial presence detect. diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index d354a26f6..deab811bd 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -39,8 +39,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void); int checkboard (void) { @@ -61,54 +59,6 @@ int checkboard (void) return 0; } - -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint temp_ddrdll = 0; - - /* - * Work around to stabilize DDR DLL - */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; -#else - dram_size = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - /* - * Initialize SDRAM. - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - - /* * Initialize Local Bus */ @@ -232,7 +182,7 @@ sdram_init(void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index a9925d542..adcc0ade0 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_64M, 1), -#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 59ec60446..59df2bdb3 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -42,7 +42,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif void local_bus_init(void); -void sdram_init(void); /* * I/O Port configuration table @@ -242,48 +241,6 @@ int checkboard (void) return 0; } -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 2b6900c08..caea2f4d9 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -68,23 +68,6 @@ int checkboard (void) return 0; } -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} - #ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; #endif diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index ebeb89749..a4a35fa3b 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -42,7 +42,6 @@ DECLARE_GLOBAL_DATA_PTR; void local_bus_init(void); -void sdram_init(void); int checkboard (void) { @@ -75,43 +74,6 @@ int checkboard (void) return 0; } -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index edaba26f5..5fe7f1398 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -40,7 +40,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif void local_bus_init(void); -void sdram_init(void); /* * I/O Port configuration table @@ -240,50 +239,6 @@ int checkboard (void) return 0; } -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 2ae0459fe..49701efda 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -44,8 +44,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void); /* @@ -266,54 +264,6 @@ int checkboard (void) return 0; } - -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint temp_ddrdll = 0; - - /* - * Work around to stabilize DDR DLL - */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; -#else - dram_size = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - /* - * Initialize SDRAM. - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - - /* * Initialize Local Bus */ @@ -437,7 +387,7 @@ sdram_init(void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index a9925d542..adcc0ade0 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_64M, 1), -#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 71cfbf0f3..85885fc4f 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -101,7 +101,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { }; void local_bus_init(void); -void sdram_init(void); int board_early_init_f (void) { @@ -138,43 +137,6 @@ int checkboard (void) return 0; } -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 9700b8c6e..07db16aa0 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -45,8 +45,6 @@ #include "../common/pq-mds-pib.h" #endif -phys_size_t fixed_sdram(void); - const qe_iop_conf_t qe_iop_conf_tab[] = { /* QE_MUX_MDC */ {2, 31, 1, 0, 1}, /* QE_MUX_MDC */ @@ -245,40 +243,6 @@ int checkboard (void) return 0; } -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - volatile ccsr_gur_t *gur = - (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - out_be32(&gur->ddrdllcr, 0x81000000); - udelay(200); -#endif - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} - #if !defined(CONFIG_SPD_EEPROM) phys_size_t fixed_sdram(void) { diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index c217c278e..c69dfe4cc 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -39,8 +39,6 @@ #include "../common/sgmii_riser.h" -long int fixed_sdram(void); - int checkboard (void) { u8 vboot; @@ -74,23 +72,6 @@ int checkboard (void) return 0; } -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing...."); - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} #if !defined(CONFIG_SPD_EEPROM) /* diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 7cb549b1b..e3e830066 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -76,19 +76,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing....\n"); - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000; - - puts(" DDR: "); - return dram_size; -} - #define CONFIG_TFP410_I2C_ADDR 0x38 /* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 15b46b0da..e54fde253 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -239,19 +239,6 @@ phys_size_t fixed_sdram (void) fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1); return ddr_size; } - -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - dram_size = fixed_sdram(); - set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts("DDR: "); - return dram_size; -} diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 07b08014d..40589da11 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -44,8 +44,6 @@ DECLARE_GLOBAL_DATA_PTR; -phys_size_t fixed_sdram(void); - int checkboard(void) { u8 sw; @@ -70,31 +68,6 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing...."); - -#ifdef CONFIG_DDR_SPD - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); - - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - dram_size, - LAW_TRGT_IF_DDR) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - }; -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} - #if !defined(CONFIG_DDR_SPD) /* * Fixed sdram init -- doesn't use serial presence detect. @@ -170,6 +143,13 @@ phys_size_t fixed_sdram(void) udelay(500); #endif + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE * 1024 * 1024, + LAW_TRGT_IF_DDR) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + }; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 06c1eea37..1bce6fa3f 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -43,8 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram (void); int board_early_init_f (void) { @@ -69,47 +67,6 @@ int checkboard (void) return 0; } -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - out_be32(&gur->ddrdllcr, 0x81000000); - asm("sync;isync;msync"); - udelay(200); - } -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ @@ -268,7 +225,7 @@ testdram(void) * fixed_sdram init -- doesn't use serial presence detect. * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 38bdeb37c..bb4c05210 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -65,44 +65,34 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 1, BOOKE_PAGESZ_1G, 1), /* - * TLB 2: 256M Cacheable, non-guarded - * 0x0 256M DDR SDRAM - */ -#if !defined(CONFIG_SPD_EEPROM) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 2, BOOKE_PAGESZ_256M, 1), -#endif - - /* - * TLB 3: 64M Non-cacheable, guarded + * TLB 2: 64M Non-cacheable, guarded * 0xe0000000 1M CCSRBAR * 0xe2000000 8M PCI1 IO * 0xe2800000 8M PCIe IO */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_64M, 1), + 0, 2, BOOKE_PAGESZ_64M, 1), /* - * TLB 4: 64M Cacheable, non-guarded + * TLB 3: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 4, BOOKE_PAGESZ_64M, 1), + 0, 3, BOOKE_PAGESZ_64M, 1), /* - * TLB 5: 64M Cacheable, non-guarded + * TLB 4: 64M Cacheable, non-guarded * 0xf4000000 64M LBC SDRAM Second half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_64M, 1), + 0, 4, BOOKE_PAGESZ_64M, 1), /* - * TLB 6: 16M Cacheable, non-guarded + * TLB 5: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision @@ -110,24 +100,24 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_16M, 1), + 0, 5, BOOKE_PAGESZ_16M, 1), /* - * TLB 7: 4M Non-cacheable, guarded + * TLB 6: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_4M, 1), + 0, 6, BOOKE_PAGESZ_4M, 1), /* - * TLB 8: 4M Non-cacheable, guarded + * TLB 7: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4M, 1), + 0, 7, BOOKE_PAGESZ_4M, 1), }; diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 7bf81799e..c5fe92e06 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -38,8 +38,6 @@ #include #include -long int fixed_sdram (void); - /* * I/O Port configuration table * @@ -263,95 +261,6 @@ int checkboard (void) } -phys_size_t initdram (int board_type) -{ - long dram_size = 0; - -#if 0 -#if !defined(CONFIG_RAM_AS_FLASH) - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - sys_info_t sysinfo; - uint temp_lbcdll = 0; -#endif -#endif /* 0 */ -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif -#if defined(CONFIG_DDR_DLL) - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - -#if 0 -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */ - get_sys_info(&sysinfo); - /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) { - lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; - } else { -#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */ - lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */ -#endif - lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff; - udelay(200); - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; - asm("sync;isync;msync"); - } - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */ - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; - asm("sync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - asm("sync"); - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("sync"); -#endif -#endif - -#if defined(CONFIG_DDR_ECC) - { - /* Initialize all of memory for ECC, then - * enable errors */ - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - - dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); - - /* Enable errors for ECC */ - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - } -#endif - - return dram_size; -} - - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { @@ -390,7 +299,7 @@ int testdram (void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #define CONFIG_SYS_DDR_CONTROL 0xc2000000 diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index ef897b216..c8235f4a9 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -39,7 +39,7 @@ * so this should be extended for other future boards * using this routine! */ -long int fixed_sdram(void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); @@ -77,19 +77,6 @@ long int fixed_sdram(void) } #endif -phys_size_t initdram (int board_type) -{ - long dram_size = 0; -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram(); -#endif - return dram_size; -} - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c index 1ed340efe..de22bf5e0 100644 --- a/board/stx/stxgp3/stxgp3.c +++ b/board/stx/stxgp3/stxgp3.c @@ -40,8 +40,6 @@ #include #include -long int fixed_sdram (void); - /* * I/O Port configuration table * @@ -277,36 +275,6 @@ show_activity(int flag) next_led_update += (get_tbclk() / 4); } -phys_size_t -initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DDR_ECC) - /* Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - return dram_size; -} - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index 6cd28a34b..83ffcd2b9 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -41,8 +41,6 @@ #include #include -long int fixed_sdram (void); - /* * I/O Port configuration table * @@ -294,37 +292,6 @@ show_activity(int flag) next_led_update += (get_tbclk() / 4); } -phys_size_t -initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DDR_ECC) - /* Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - return dram_size; -} - - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 260cd1c6d..b2d318535 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -394,43 +394,6 @@ static phys_size_t sdram_setup(int casl) return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0; } -phys_size_t initdram (int board_type) -{ - phys_size_t dram_size = 0; - -#if defined(CONFIG_DDR_DLL) - /* - * This DLL-Override only used on TQM8540 and TQM8560 - */ - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int i, x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm ("sync; isync; msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) { - gur->devdisr = gur->devdisr | 0x00010000; - asm ("sync; isync; msync"); - for (i = 0; i < x; i++) - ; - gur->devdisr = gur->devdisr & 0xfff7ffff; - asm ("sync; isync; msync"); - x++; - } - } -#endif - - dram_size = fixed_sdram(); - - return dram_size; -} - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 75dd348aa..f9f8cc9a0 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -120,36 +120,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), - -#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE) - /* - * TLB 7+8: 2G DDR, cache enabled - * 0x00000000 2G DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - */ - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_1G, 1), - - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_1G, 1), -#else - /* - * TLB 7+8: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - */ - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), -#endif #ifdef CONFIG_PCIE1 /* * TLB 9: 16M Non-cacheable, guarded @@ -228,23 +198,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 7, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 8+9: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 9, BOOKE_PAGESZ_256M, 1), - #ifdef CONFIG_PCIE1 /* * TLB 10: 16M Non-cacheable, guarded diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index 7604f626b..39d105fcd 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -33,8 +33,6 @@ COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o -COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o -COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o diff --git a/board/xes/common/fsl_8xxx_ddr.c b/board/xes/common/fsl_8xxx_ddr.c deleted file mode 100644 index 81ee70d5a..000000000 --- a/board/xes/common/fsl_8xxx_ddr.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = fsl_ddr_sdram(); - -#ifdef CONFIG_MPC85xx - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* Initialize and enable DDR ECC */ - ddr_enable_ecc(dram_size); -#endif - - return dram_size; -} diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c index 0f7fa6c43..572a90800 100644 --- a/board/xes/xpedite517x/xpedite517x.c +++ b/board/xes/xpedite517x/xpedite517x.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -71,6 +72,18 @@ int board_early_init_r(void) return 0; } +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = fsl_ddr_sdram(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* Initialize and enable DDR ECC */ + ddr_enable_ecc(dram_size); +#endif + + return dram_size; +} + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 890d6d9d4..febe95da8 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -147,6 +147,10 @@ * DDR Setup */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#if defined(CONFIG_TQM_BIGFLASH) || \ + (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE)) +#define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G) +#endif #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #ifdef CONFIG_TQM8548_AG #define CONFIG_VERY_BIG_RAM From 70961ba41477a709870a01c86af2950124bb64fe Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Fri, 17 Dec 2010 17:17:57 -0600 Subject: [PATCH 26/63] mpc85xx: rename sdram_init() lbc_sdram_init() sdram_init() is used to initialize sdram on the lbc. Rename it accordingly. Signed-off-by: Becky Bruce Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 4 ++-- arch/powerpc/include/asm/fsl_lbc.h | 2 +- board/freescale/mpc8540ads/mpc8540ads.c | 4 +--- board/freescale/mpc8541cds/mpc8541cds.c | 3 +-- board/freescale/mpc8548cds/mpc8548cds.c | 3 +-- board/freescale/mpc8555cds/mpc8555cds.c | 3 +-- board/freescale/mpc8560ads/mpc8560ads.c | 4 +--- board/freescale/mpc8568mds/mpc8568mds.c | 3 +-- board/sbc8548/sbc8548.c | 3 +-- 10 files changed, 11 insertions(+), 20 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index bea8e10af..afa9ca978 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -331,7 +331,7 @@ phys_size_t initdram(int board_type) #endif /* Some boards also have sdram on the lbc */ - sdram_init(); + lbc_sdram_init(); puts("DDR: "); return dram_size; diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 10fcd243f..6f401e750 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -11,11 +11,11 @@ #ifdef CONFIG_MPC85xx /* Boards should provide their own version of this if they use lbc sdram */ -void __sdram_init(void) +void __lbc_sdram_init(void) { /* Do nothing */ } -void sdram_init(void) __attribute__((weak, alias("__sdram_init"))); +void lbc_sdram_init(void) __attribute__((weak, alias("__lbc_sdram_init"))); #endif diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index fcf3371f5..c5047326a 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -17,7 +17,7 @@ #include #ifdef CONFIG_MPC85xx -void sdram_init(void); +void lbc_sdram_init(void); #endif /* BR - Base Registers diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index deab811bd..9eeb13492 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -122,9 +122,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ - -void -sdram_init(void) +void lbc_sdram_init(void) { volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 59df2bdb3..3ee666f42 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -291,8 +291,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ -void -sdram_init(void) +void lbc_sdram_init(void) { #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index a4a35fa3b..8ad6b22b1 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -111,8 +111,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ -void -sdram_init(void) +void lbc_sdram_init(void) { #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 5fe7f1398..02df6ae22 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -289,8 +289,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ -void -sdram_init(void) +void lbc_sdram_init(void) { #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 49701efda..26a64a3da 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -327,9 +327,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ - -void -sdram_init(void) +void lbc_sdram_init(void) { volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 85885fc4f..07f8e5159 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -171,8 +171,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ -void -sdram_init(void) +void lbc_sdram_init(void) { #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 1bce6fa3f..ff3920bc9 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -104,8 +104,7 @@ local_bus_init(void) /* * Initialize SDRAM memory on the Local Bus. */ -void -sdram_init(void) +void lbc_sdram_init(void) { #if defined(CONFIG_SYS_LBC_SDRAM_SIZE) From 810c44274980d8bb9fa0d81d091a374adbae8309 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Fri, 17 Dec 2010 17:17:58 -0600 Subject: [PATCH 27/63] 85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN This config option is for an erratum workaround; rename it to be more clear. Also, drop it from config files don't need it and were undefining it. Signed-off-by: Becky Bruce Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- doc/README.mpc85xxads | 4 ++-- include/configs/MPC8536DS.h | 1 - include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8572DS.h | 1 - include/configs/P1_P2_RDB.h | 1 - include/configs/SBC8540.h | 2 +- include/configs/TQM85xx.h | 2 +- include/configs/sbc8560.h | 2 +- include/configs/stxgp3.h | 2 +- include/configs/stxssa.h | 1 - 12 files changed, 11 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index d73f3d7f1..2d32532f2 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -46,6 +46,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) puts("Work-around for Erratum CPU22 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) + puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); #endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index afa9ca978..4ef9be1b2 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -293,7 +293,7 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; -#if defined(CONFIG_DDR_DLL) +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); unsigned int x = 10; diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index 046f981cf..d059a9798 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -144,8 +144,8 @@ Updated 13-July-2004 Jon Loeliger also manual config the DDR after undef this definition. CONFIG_DDR_ECC only for ECC DDR module - CONFIG_DDR_DLL DLL fix on some ADS boards needed for more - stability. + CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN DLL fix on some ADS boards needed + for more stability. CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0. Other than the above definitions, the rest in the config files are diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 7473834c5..71ffba3e0 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -144,7 +144,6 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD -#undef CONFIG_DDR_DLL #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b221a5cc9..e5ac3a950 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -89,7 +89,7 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 9d2e209d6..8cdcbea7b 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -131,7 +131,6 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD -#undef CONFIG_DDR_DLL #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 2dfee3d1b..d479a0985 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -146,7 +146,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_DLL #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index fd9bacc49..72559c0c0 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -118,7 +118,7 @@ #undef CONFIG_DDR_SPD #if defined(CONFIG_MPC85xx_REV1) - #define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #endif #undef CONFIG_DDR_ECC /* only for ECC DDR module */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index febe95da8..79a958dc2 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -162,7 +162,7 @@ #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) /* TQM8540 & 8560 need DLL-override */ -#define CONFIG_DDR_DLL /* DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 101c5d943..435b148f3 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -116,7 +116,7 @@ #undef CONFIG_DDR_SPD #if defined(CONFIG_MPC85xx_REV1) - #define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #endif #undef CONFIG_DDR_ECC /* only for ECC DDR module */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index c2497ad09..fc3881d22 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -123,7 +123,7 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 996120a02..d5dd94f55 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -135,7 +135,6 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef From 7ea3871e06c421a44e7286792610dc00992070e6 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Fri, 17 Dec 2010 17:17:59 -0600 Subject: [PATCH 28/63] MPC8xxx DDR: align informational prints Add spaces to cause the informational prints to line up with the ones from init_func_ram() in board.c. Output now looks like this: .... DRAM: Detected 4096 MB of memory This U-Boot only supports < 4G of DDR You could rebuild it with CONFIG_PHYS_64BIT DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC off) .... The prints from lbc_sdram_init() have also been modified to line line up and changed to start with "LBC SDRAM" instead of the confusing "SDRAM". Signed-off-by: Becky Bruce Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 5 +++-- board/freescale/mpc8540ads/mpc8540ads.c | 5 +++-- board/freescale/mpc8541cds/mpc8541cds.c | 6 +++--- board/freescale/mpc8548cds/mpc8548cds.c | 6 +++--- board/freescale/mpc8555cds/mpc8555cds.c | 6 +++--- board/freescale/mpc8560ads/mpc8560ads.c | 5 +++-- board/freescale/mpc8568mds/mpc8568mds.c | 6 +++--- 7 files changed, 21 insertions(+), 18 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 6d582e97d..e3888ff6e 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -469,8 +469,9 @@ phys_size_t fsl_ddr_sdram(void) /* Check for 4G or more. Bad. */ if (total_memory >= (1ull << 32)) { printf("Detected %lld MB of memory\n", total_memory >> 20); - printf("This U-Boot only supports < 4G of DDR\n"); - printf("You could rebuild it with CONFIG_PHYS_64BIT\n"); + printf(" This U-Boot only supports < 4G of DDR\n"); + printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); + printf(" "); /* re-align to match init_func_ram print */ total_memory = CONFIG_MAX_MEM_MAPPED; } #endif diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index 9eeb13492..c75585e28 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -127,8 +127,9 @@ void lbc_sdram_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - puts(" SDRAM: "); - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + puts("LBC SDRAM: "); + print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, + "\n "); /* * Setup SDRAM Base and Option Registers diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 3ee666f42..0d3752d56 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -301,9 +301,9 @@ void lbc_sdram_init(void) uint cpu_board_rev; uint lsdmr_common; - puts(" SDRAM: "); - - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + puts("LBC SDRAM: "); + print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, + "\n "); /* * Setup SDRAM Base and Option Registers diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 8ad6b22b1..2c455853a 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -121,9 +121,9 @@ void lbc_sdram_init(void) uint cpu_board_rev; uint lsdmr_common; - puts(" SDRAM: "); - - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + puts("LBC SDRAM: "); + print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, + "\n "); /* * Setup SDRAM Base and Option Registers diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 02df6ae22..60d1758af 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -299,9 +299,9 @@ void lbc_sdram_init(void) uint cpu_board_rev; uint lsdmr_common; - puts(" SDRAM: "); - - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + puts("LBC SDRAM: "); + print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, + "\n "); /* * Setup SDRAM Base and Option Registers diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 26a64a3da..1a165bff8 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -332,8 +332,9 @@ void lbc_sdram_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - puts(" SDRAM: "); - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + puts("LBC SDRAM: "); + print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, + "\n "); /* * Setup SDRAM Base and Option Registers diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 07f8e5159..a504f8a9d 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -180,9 +180,9 @@ void lbc_sdram_init(void) uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint lsdmr_common; - puts(" SDRAM: "); - - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + puts("LBC SDRAM: "); + print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, + "\n "); /* * Setup SDRAM Base and Option Registers From 45a68135c12bf7d534f3ce25bef493e16d32cedb Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 5 Jan 2011 10:33:46 -0600 Subject: [PATCH 29/63] powerpc/85xx: Fix bug in dcache_disable We set the L1 dache register with a bogus register value. Need to be using 'r3' instead of 'r0'. Reported-by: John Traill Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 945c1b847..fa98af64b 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -753,7 +753,7 @@ dcache_disable: lis r4,0 ori r4,r4,L1CSR0_DCE andc r3,r3,r4 - mtspr L1CSR0,r0 + mtspr L1CSR0,r3 isync blr From 3a0e3c27a50e395a59497e8bd60a00404e662eb1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 05:57:25 -0600 Subject: [PATCH 30/63] powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixup Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala Acked-by: Wolfgang Denk --- arch/powerpc/include/asm/fsl_pci.h | 43 +++--------------------------- drivers/pci/fsl_pci_init.c | 5 +++- drivers/pci/pci.c | 12 +++++++++ include/pci.h | 1 + 4 files changed, 20 insertions(+), 41 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index fa035142f..5cbe139d5 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -27,8 +27,7 @@ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); -void ft_fsl_pci_setup(void *blob, const char *pci_compat, - struct pci_controller *hose, unsigned long ctrl_addr); +void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr); /* * Common PCI/PCIE Register structure for mpc85xx and mpc86xx @@ -201,54 +200,18 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, } #define __FT_FSL_PCI_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, &pci##num##_hose, \ - CONFIG_SYS_PCI##num##_ADDR) - -#define __FT_FSL_PCI_DEL(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCI##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR) #define __FT_FSL_PCIE_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, &pcie##num##_hose, \ - CONFIG_SYS_PCIE##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR) -#define __FT_FSL_PCIE_DEL(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCIE##num##_ADDR) - -#ifdef CONFIG_PCI1 #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1) -#else -#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 1) -#endif - -#ifdef CONFIG_PCI2 #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2) -#else -#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 2) -#endif -#ifdef CONFIG_PCIE1 #define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1) -#else -#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 1) -#endif - -#ifdef CONFIG_PCIE2 #define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2) -#else -#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 2) -#endif - -#ifdef CONFIG_PCIE3 #define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3) -#else -#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 3) -#endif - -#ifdef CONFIG_PCIE4 #define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4) -#else -#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 4) -#endif #if defined(CONFIG_FSL_CORENET) #define FSL_PCIE_COMPAT "fsl,p4080-pcie" diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 5b34dcbb0..71ab02b88 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -518,11 +518,14 @@ void fsl_pci_config_unlock(struct pci_controller *hose) #include void ft_fsl_pci_setup(void *blob, const char *pci_compat, - struct pci_controller *hose, unsigned long ctrl_addr) + unsigned long ctrl_addr) { int off; u32 bus_range[2]; phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr; + struct pci_controller *hose; + + hose = find_hose_by_cfg_addr((void *)(ctrl_addr)); /* convert ctrl_addr to true physical address */ p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 702ac6782..cdfc4fb01 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -165,6 +165,18 @@ struct pci_controller *pci_bus_to_hose (int bus) return NULL; } +struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr) +{ + struct pci_controller *hose; + + for (hose = hose_head; hose; hose = hose->next) { + if (hose->cfg_addr == cfg_addr) + return hose; + } + + return NULL; +} + int pci_last_busno(void) { struct pci_controller *hose = hose_head; diff --git a/include/pci.h b/include/pci.h index c45600603..e80b6bdf5 100644 --- a/include/pci.h +++ b/include/pci.h @@ -511,6 +511,7 @@ extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); extern void pci_register_hose(struct pci_controller* hose); extern struct pci_controller* pci_bus_to_hose(int bus); +extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); extern int pci_hose_scan(struct pci_controller *hose); extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); From a4aafcc990c12816cfd4644e5c003d8556b6236b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 15 Dec 2010 14:21:41 -0600 Subject: [PATCH 31/63] powerpc/fsl-pci: Add generic code to setup PCIe controllers Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/fsl_pci.h | 10 ++ board/freescale/p1022ds/p1022ds.c | 67 +------------ drivers/pci/fsl_pci_init.c | 148 +++++++++++++++++++++++++++++ 3 files changed, 160 insertions(+), 65 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 5cbe139d5..15ab50d95 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -22,6 +22,8 @@ #define __FSL_PCI_H_ #include +#include +#include int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); @@ -172,6 +174,9 @@ struct fsl_pci_info { int fsl_pci_init_port(struct fsl_pci_info *pci_info, struct pci_controller *hose, int busno); +int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, + struct fsl_pci_info *pci_info); +int fsl_pcie_init_board(int busno); #define SET_STD_PCI_INFO(x, num) \ { \ @@ -220,6 +225,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, FT_FSL_PCIE2_SETUP; \ FT_FSL_PCIE3_SETUP; \ FT_FSL_PCIE4_SETUP; +#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP #elif defined(CONFIG_MPC85xx) #define FSL_PCI_COMPAT "fsl,mpc8540-pci" #define FSL_PCIE_COMPAT "fsl,mpc8548-pcie" @@ -229,6 +235,10 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, FT_FSL_PCIE1_SETUP; \ FT_FSL_PCIE2_SETUP; \ FT_FSL_PCIE3_SETUP; +#define FT_FSL_PCIE_SETUP \ + FT_FSL_PCIE1_SETUP; \ + FT_FSL_PCIE2_SETUP; \ + FT_FSL_PCIE3_SETUP; #elif defined(CONFIG_MPC86xx) #define FSL_PCI_COMPAT "fsl,mpc8610-pci" #define FSL_PCIE_COMPAT "fsl,mpc8641-pcie" diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index e3e830066..0ea0bdf28 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -187,7 +187,7 @@ static u8 serdes_dev_slot[][SATA2 + 1] = { * Returns the name of the slot to which the PCIe or SATA controller is * connected */ -const char *serdes_slot_name(enum srds_prtcl device) +const char *board_serdes_name(enum srds_prtcl device) { ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); @@ -202,73 +202,10 @@ const char *serdes_slot_name(enum srds_prtcl device) return "Nothing"; } -static void configure_pcie(struct fsl_pci_info *info, - struct pci_controller *hose, - const char *connected) -{ - static int bus_number = 0; - int is_endpoint; - - set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); - set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); - is_endpoint = fsl_setup_hose(hose, info->regs); - printf("PCIE%u: connected to %s as %s (base addr %lx)\n", - info->pci_num, connected, - is_endpoint ? "Endpoint" : "Root Complex", info->regs); - bus_number = fsl_pci_init_port(info, hose, bus_number); -} - -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - #ifdef CONFIG_PCI void pci_init_board(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - struct fsl_pci_info pci_info; - u32 devdisr = in_be32(&gur->devdisr); - -#ifdef CONFIG_PCIE1 - if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) { - SET_STD_PCIE_INFO(pci_info, 1); - configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1)); - } else { - printf("PCIE1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { - SET_STD_PCIE_INFO(pci_info, 2); - configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2)); - } else { - printf("PCIE2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCIE3 - if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { - SET_STD_PCIE_INFO(pci_info, 3); - configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3)); - } else { - printf("PCIE3: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ -#endif + fsl_pcie_init_board(0); } #endif diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 71ab02b88..d7623369f 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -18,6 +18,8 @@ */ #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -513,6 +515,152 @@ void fsl_pci_config_unlock(struct pci_controller *hose) } } +#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \ + defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4) +int fsl_configure_pcie(struct fsl_pci_info *info, + struct pci_controller *hose, + const char *connected, int busno) +{ + int is_endpoint; + + set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); + set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); + is_endpoint = fsl_setup_hose(hose, info->regs); + printf("PCIE%u: connected to %s as %s (base addr %lx)\n", + info->pci_num, connected, + is_endpoint ? "Endpoint" : "Root Complex", info->regs); + return fsl_pci_init_port(info, hose, busno); +} + +#if defined(CONFIG_FSL_CORENET) + #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1 + #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2 + #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3 + #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4 + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC85xx) + #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE + #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2 + #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3 + #define _DEVDISR_PCIE4 0 + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC86xx) + #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1 + #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2 + #define _DEVDISR_PCIE3 0 + #define _DEVDISR_PCIE4 0 + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ + (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) +#else +#error "No defines for DEVDISR_PCIE" +#endif + +/* Implement a dummy function for those platforms w/o SERDES */ +static const char *__board_serdes_name(enum srds_prtcl device) +{ + switch (device) { +#ifdef CONFIG_SYS_PCIE1_NAME + case PCIE1: + return CONFIG_SYS_PCIE1_NAME; +#endif +#ifdef CONFIG_SYS_PCIE2_NAME + case PCIE2: + return CONFIG_SYS_PCIE2_NAME; +#endif +#ifdef CONFIG_SYS_PCIE3_NAME + case PCIE3: + return CONFIG_SYS_PCIE3_NAME; +#endif +#ifdef CONFIG_SYS_PCIE4_NAME + case PCIE4: + return CONFIG_SYS_PCIE4_NAME; +#endif + default: + return NULL; + } + + return NULL; +} + +__attribute__((weak, alias("__board_serdes_name"))) const char * +board_serdes_name(enum srds_prtcl device); + +static u32 devdisr_mask[] = { + _DEVDISR_PCIE1, + _DEVDISR_PCIE2, + _DEVDISR_PCIE3, + _DEVDISR_PCIE4, +}; + +int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, + struct fsl_pci_info *pci_info) +{ + struct pci_controller *hose; + int num = dev - PCIE1; + + hose = calloc(1, sizeof(struct pci_controller)); + if (!hose) + return busno; + + if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) { + busno = fsl_configure_pcie(pci_info, hose, + board_serdes_name(dev), busno); + } else { + printf("PCIE%d: disabled\n", num + 1); + } + + return busno; +} + +int fsl_pcie_init_board(int busno) +{ + struct fsl_pci_info pci_info; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; + u32 devdisr = in_be32(&gur->devdisr); + +#ifdef CONFIG_PCIE1 + SET_STD_PCIE_INFO(pci_info, 1); + busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info); +#else + setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ +#endif + +#ifdef CONFIG_PCIE2 + SET_STD_PCIE_INFO(pci_info, 2); + busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info); +#else + setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ +#endif + +#ifdef CONFIG_PCIE3 + SET_STD_PCIE_INFO(pci_info, 3); + busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info); +#else + setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */ +#endif + +#ifdef CONFIG_PCIE4 + SET_STD_PCIE_INFO(pci_info, 4); + busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info); +#else + setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */ +#endif + + return busno; +} +#else +int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, + struct fsl_pci_info *pci_info) +{ + return busno; +} + +int fsl_pcie_init_board(int busno) +{ + return busno; +} +#endif + #ifdef CONFIG_OF_BOARD_SETUP #include #include From 18ea5551307866af06eb7628ec05b1959212efa0 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 06:53:52 -0600 Subject: [PATCH 32/63] powerpc/85xx: Rework MPC8572DS pci_init_board to use common FSL PCIe code Remove duplicated code in MPC8572DS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Chenhui Zhao Signed-off-by: Kumar Gala --- board/freescale/mpc8572ds/law.c | 8 +-- board/freescale/mpc8572ds/mpc8572ds.c | 91 +++------------------------ include/configs/MPC8572DS.h | 3 + 3 files changed, 13 insertions(+), 89 deletions(-) diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c index e13bb5336..7c63f847d 100644 --- a/board/freescale/mpc8572ds/law.c +++ b/board/freescale/mpc8572ds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008, 2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -29,12 +29,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), - SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index c69dfe4cc..4b2ef4e5e 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -129,107 +129,34 @@ phys_size_t fixed_sdram (void) #endif -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - #ifdef CONFIG_PCI void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[3]; - u32 devdisr, pordevsr, io_sel, temp32; - int first_free_busno = 0; - int num = 0; + struct pci_controller *hose; - int pcie_ep, pcie_configured; + fsl_pcie_init_board(0); - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR)); - debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); + if (hose) { + u32 temp32; + u8 uli_busno = hose->first_busno + 2; - puts("\n"); -#ifdef CONFIG_PCIE3 - pcie_configured = is_serdes_configured(PCIE3); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ - SET_STD_PCIE_INFO(pci_info[num], 3); - pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); - printf("PCIE3: connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie3_hose, first_free_busno); /* * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. * Device 1d has the first on-board memory BAR. */ - pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0), + pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0), PCI_BASE_ADDRESS_1, &temp32); + if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { - void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), + void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0), temp32, 4, 0); debug(" uli1572 read to %p\n", p); in_be32(p); } - } else { - printf("PCIE3: disabled\n"); } - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - pcie_configured = is_serdes_configured(PCIE2); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - } else { - printf("PCIE2: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif } #endif diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 8cdcbea7b..9ec02cce9 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -467,6 +467,7 @@ */ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ +#define CONFIG_SYS_PCIE3_NAME "ULI" #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 @@ -486,6 +487,7 @@ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 @@ -505,6 +507,7 @@ #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 From 4d5723da57344cc8f41324fb18b039fb2ce83428 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 07:01:00 -0600 Subject: [PATCH 33/63] powerpc/85xx: Rework P2020DS pci_init_board to use common FSL PCIe code Remove duplicated code in P2020DS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Li Yang Signed-off-by: Kumar Gala --- board/freescale/p2020ds/law.c | 8 +-- board/freescale/p2020ds/p2020ds.c | 105 +----------------------------- include/configs/P2020DS.h | 3 + 3 files changed, 5 insertions(+), 111 deletions(-) diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c index 28ed2ed5e..91642a983 100644 --- a/board/freescale/p2020ds/law.c +++ b/board/freescale/p2020ds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -29,12 +29,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), - SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 40589da11..8546aa903 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -155,113 +155,10 @@ phys_size_t fixed_sdram(void) #endif -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - #ifdef CONFIG_PCI void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[3]; - u32 devdisr, pordevsr, io_sel; - int first_free_busno = 0; - int num = 0; - - int pcie_ep, pcie_configured; - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - - debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - - puts("\n"); -#ifdef CONFIG_PCIE2 - pcie_configured = is_serdes_configured(PCIE2); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf("PCIE2: connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - - /* - * The workaround doesn't work on p2020 because the location - * we try and read isn't valid on p2020, fix this later - */ -#if 0 - /* - * Activate ULI1575 legacy chip by performing a fake - * memory access. Needed to make ULI RTC work. - * Device 1d has the first on-board memory BAR. - */ - - pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0), - PCI_BASE_ADDRESS_1, &temp32); - if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { - void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), - temp32, 4, 0); - debug(" uli1575 read to %p\n", p); - in_be32(p); - } -#endif - } else { - printf("PCIE2: disabled\n"); - } - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCIE3 - pcie_configured = is_serdes_configured(PCIE3); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { - SET_STD_PCIE_INFO(pci_info[num], 3); - pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); - printf("PCIE3: connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie3_hose, first_free_busno); - } else { - printf("PCIE3: disabled\n"); - } - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ -#endif - -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif + fsl_pcie_init_board(0); } #endif diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 0af21528d..24f2498d0 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -394,6 +394,7 @@ */ /* controller 3, Slot 1, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_NAME "Slot 1" #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 @@ -413,6 +414,7 @@ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "ULI" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 @@ -432,6 +434,7 @@ #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 From 64a1686a5534030227bc7356cb6914078a3d88c4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 06:01:24 -0600 Subject: [PATCH 34/63] powerpc/85xx: Rework MPC8544DS pci_init_board to use common FSL PCIe code Remove duplicated code in MPC8544DS board and utilize the common fsl_pcie_init_ctrl(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. We don't use the full fsl_pcie_init_ctrl() since we have to handle PCIE3 specially to setup the additional memory map region and we utilize a single LAW to cover the controller. Signed-off-by: Kumar Gala --- board/freescale/mpc8544ds/law.c | 10 +-- board/freescale/mpc8544ds/mpc8544ds.c | 99 +++++++-------------------- include/configs/MPC8544DS.h | 5 +- 3 files changed, 30 insertions(+), 84 deletions(-) diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c index 3d308c8e5..59e03fc92 100644 --- a/board/freescale/mpc8544ds/law.c +++ b/board/freescale/mpc8544ds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008, 2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -28,15 +28,7 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - /* contains both PCIE3 MEM & IO space */ - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index caea2f4d9..a48c8155c 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -72,14 +72,6 @@ int checkboard (void) static struct pci_controller pci1_hose; #endif -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - #ifdef CONFIG_PCIE3 static struct pci_controller pcie3_hose; #endif @@ -87,11 +79,10 @@ static struct pci_controller pcie3_hose; void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[4]; + struct fsl_pci_info pci_info; u32 devdisr, pordevsr, io_sel; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; int first_free_busno = 0; - int num = 0; int pcie_ep, pcie_configured; @@ -108,9 +99,12 @@ void pci_init_board(void) pcie_configured = is_serdes_configured(PCIE3); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ - SET_STD_PCIE_INFO(pci_info[num], 3); - pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); -#ifdef CONFIG_SYS_PCIE3_MEM_BUS2 + /* contains both PCIE3 MEM & IO space */ + set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, + LAW_TRGT_IF_PCIE_3); + SET_STD_PCIE_INFO(pci_info, 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs); + /* outbound memory */ pci_set_region(&pcie3_hose.regions[0], CONFIG_SYS_PCIE3_MEM_BUS2, @@ -119,11 +113,11 @@ void pci_init_board(void) PCI_REGION_MEM); pcie3_hose.region_count = 1; -#endif + printf("PCIE3: connected to ULI as %s (base addr %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], + pci_info.regs); + first_free_busno = fsl_pci_init_port(&pci_info, &pcie3_hose, first_free_busno); /* @@ -140,64 +134,17 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); -#ifdef CONFIG_SYS_PCIE1_MEM_BUS2 - /* outbound memory */ - pci_set_region(&pcie1_hose.regions[0], - CONFIG_SYS_PCIE1_MEM_BUS2, - CONFIG_SYS_PCIE1_MEM_PHYS2, - CONFIG_SYS_PCIE1_MEM_SIZE2, - PCI_REGION_MEM); - - pcie1_hose.region_count = 1; -#endif - printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } - - puts("\n"); + SET_STD_PCIE_INFO(pci_info, 1); + first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info); #else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ + setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ #endif #ifdef CONFIG_PCIE2 - pcie_configured = is_serdes_configured(PCIE2); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); -#ifdef CONFIG_SYS_PCIE2_MEM_BUS2 - /* outbound memory */ - pci_set_region(&pcie2_hose.regions[0], - CONFIG_SYS_PCIE2_MEM_BUS2, - CONFIG_SYS_PCIE2_MEM_PHYS2, - CONFIG_SYS_PCIE2_MEM_SIZE2, - PCI_REGION_MEM); - - pcie2_hose.region_count = 1; -#endif - printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - } else { - printf("PCIE2: disabled\n"); - } - - puts("\n"); + SET_STD_PCIE_INFO(pci_info, 2); + first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info); #else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ + setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCI1 @@ -207,8 +154,13 @@ void pci_init_board(void) pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info[num], 1); - pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + SET_STD_PCI_INFO(pci_info, 1); + set_next_law(pci_info.mem_phys, + law_size_bits(pci_info.mem_size), pci_info.law); + set_next_law(pci_info.io_phys, + law_size_bits(pci_info.io_size), pci_info.law); + + pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : @@ -216,9 +168,9 @@ void pci_init_board(void) pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", - pci_info[num].regs); + pci_info.regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], + first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); } else { printf("PCI: disabled\n"); @@ -230,7 +182,6 @@ void pci_init_board(void) #endif } - int last_stage_init(void) { return 0; diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index e94822e5b..dc821a381 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007, 2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -268,6 +268,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 1, tgtid 1, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 @@ -278,6 +279,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2,tgtid 2, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 @@ -288,6 +290,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_NAME "ULI" #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 From 5f7b31b00098eb3d4c960136d042fc73f619eca4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 15:14:54 -0600 Subject: [PATCH 35/63] powerpc/85xx: Rework MPC8536DS pci_init_board to use common FSL PCIe code Remove duplicated code in MPC8536DS board and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala --- board/freescale/mpc8536ds/mpc8536ds.c | 116 ++++---------------------- include/configs/MPC8536DS.h | 3 + 2 files changed, 17 insertions(+), 102 deletions(-) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 58dc564ee..f83f629d4 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -156,123 +156,35 @@ phys_size_t fixed_sdram (void) static struct pci_controller pci1_hose; #endif -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - #ifdef CONFIG_PCI void pci_init_board(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[4]; - u32 devdisr, pordevsr, io_sel; + struct fsl_pci_info pci_info; + u32 devdisr, pordevsr; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; - int first_free_busno = 0; - int num = 0; + int first_free_busno; - int pcie_ep, pcie_configured; + first_free_busno = fsl_pcie_init_board(0); +#ifdef CONFIG_PCI1 devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); porpllsr = in_be32(&gur->porpllsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - - puts("\n"); -#ifdef CONFIG_PCIE3 - pcie_configured = is_serdes_configured(PCIE3); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ - set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, - LAW_TRGT_IF_PCIE_3); - set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_3); - SET_STD_PCIE_INFO(pci_info[num], 3); - pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); - printf("PCIE3: connected to Slot3 as %s (base address %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie3_hose, first_free_busno); - } else { - printf("PCIE3: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ -#endif - -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, - LAW_TRGT_IF_PCIE_1); - set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_1); - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected to Slot1 as %s (base address %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - pcie_configured = is_serdes_configured(PCIE2); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ - set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, - LAW_TRGT_IF_PCIE_2); - set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_2); - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - } else { - printf("PCIE2: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCI1 pci_speed = 66666000; pci_32 = 1; pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_PCI); - set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCI); - SET_STD_PCI_INFO(pci_info[num], 1); - pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + SET_STD_PCI_INFO(pci_info, 1); + set_next_law(pci_info.mem_phys, + law_size_bits(pci_info.mem_size), pci_info.law); + set_next_law(pci_info.io_phys, + law_size_bits(pci_info.io_size), pci_info.law); + + pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : @@ -280,9 +192,9 @@ void pci_init_board(void) pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", - pci_info[num].regs); + pci_info.regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], + first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); } else { printf("PCI: disabled\n"); diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 71ffba3e0..94a542cef 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -484,6 +484,7 @@ #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 1" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 @@ -503,6 +504,7 @@ #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "Slot 2" #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 @@ -522,6 +524,7 @@ #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ +#define CONFIG_SYS_PCIE3_NAME "Slot 3" #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 From 64e55d5ed40e4de2dd52910f7634304fbebe1840 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 10:47:36 -0600 Subject: [PATCH 36/63] powerpc/86xx: Rework MPC8641HPCN pci_init_board to use common FSL PCIe code Remove duplicated code in MPC8641HPCN board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala --- board/freescale/mpc8641hpcn/law.c | 7 +--- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 48 +---------------------- include/configs/MPC8641HPCN.h | 1 + 3 files changed, 3 insertions(+), 53 deletions(-) diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c index 8c8ce9585..30a7b706f 100644 --- a/board/freescale/mpc8641hpcn/law.c +++ b/board/freescale/mpc8641hpcn/law.c @@ -53,12 +53,7 @@ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), #endif -#ifdef CONFIG_PCI - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2), -#elif defined(CONFIG_RIO) +#if defined(CONFIG_RIO) SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), #endif SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index e95102170..166ff0c97 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -127,64 +127,18 @@ fixed_sdram(void) } #endif /* !defined(CONFIG_SPD_EEPROM) */ - -#if defined(CONFIG_PCI) -static struct pci_controller pcie1_hose; -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif /* CONFIG_PCIE2 */ - -int first_free_busno = 0; - void pci_init_board(void) { - struct fsl_pci_info pci_info[2]; - int pcie_ep; - int num = 0; + fsl_pcie_init_board(0); #ifdef CONFIG_PCIE1 - volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - uint devdisr = in_be32(&gur->devdisr); - int pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - /* * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); - - } else { - puts("PCIE1: disabled\n"); - } -#else - puts("PCIE1: disabled\n"); #endif /* CONFIG_PCIE1 */ - -#ifdef CONFIG_PCIE2 - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf("PCIE2: connected as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); -#else - puts("PCIE2: disabled\n"); -#endif /* CONFIG_PCIE2 */ - } diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index ab3ae5b2e..fea087649 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -332,6 +332,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Addresses are mapped 1-1. */ +#define CONFIG_SYS_PCIE1_NAME "ULI" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 From f5fa8f366931089344ddc9c995c54a53bc992d2f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 10:21:22 -0600 Subject: [PATCH 37/63] powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe code Remove duplicated code in MPC8548CDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala --- board/freescale/mpc8548cds/law.c | 10 +----- board/freescale/mpc8548cds/mpc8548cds.c | 43 +++++++------------------ include/configs/MPC8548CDS.h | 3 +- 3 files changed, 14 insertions(+), 42 deletions(-) diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index 98748aa47..e59fee807 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008,2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -51,17 +51,9 @@ */ struct law_entry law_table[] = { -#ifdef CONFIG_SYS_PCI1_MEM_PHYS - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), -#endif #ifdef CONFIG_SYS_PCI2_MEM_PHYS SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), -#endif -#ifdef CONFIG_SYS_PCIE1_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), #endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 2c455853a..f5c799b9f 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -215,20 +215,13 @@ static struct pci_controller pci1_hose = { static struct pci_controller pci2_hose; #endif /* CONFIG_PCI2 */ -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif /* CONFIG_PCIE1 */ - void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[4]; + struct fsl_pci_info pci_info; u32 devdisr, pordevsr, io_sel; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; int first_free_busno = 0; - int num = 0; - - int pcie_ep, pcie_configured; devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); @@ -244,8 +237,13 @@ void pci_init_board(void) pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info[num], 1); - pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + SET_STD_PCI_INFO(pci_info, 1); + set_next_law(pci_info.mem_phys, + law_size_bits(pci_info.mem_size), pci_info.law); + set_next_law(pci_info.io_phys, + law_size_bits(pci_info.io_size), pci_info.law); + + pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : @@ -253,9 +251,9 @@ void pci_init_board(void) pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", - pci_info[num].regs); + pci_info.regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], + first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); #ifdef CONFIG_PCIX_CHECK @@ -293,26 +291,7 @@ void pci_init_board(void) setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ #endif /* CONFIG_PCI2 */ -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif + fsl_pcie_init_board(first_free_busno); } int last_stage_init(void) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index e5ac3a950..4c5b99842 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007 Freescale Semiconductor. + * Copyright 2004, 2007, 2010 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -353,6 +353,7 @@ extern unsigned long get_clock_freq(void); #endif #ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 From 663570950d780f0dad543a6b2161e6bf75871886 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 10:23:03 -0600 Subject: [PATCH 38/63] powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code Remove duplicated code in MPC8xxx XES boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala CC: Peter Tyser --- board/xes/common/fsl_8xxx_pci.c | 112 ++++---------------------------- board/xes/xpedite517x/law.c | 8 --- board/xes/xpedite520x/law.c | 8 --- board/xes/xpedite537x/law.c | 12 ---- board/xes/xpedite550x/law.c | 12 ---- 5 files changed, 14 insertions(+), 138 deletions(-) diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c index 4135849f1..28c83c7ca 100644 --- a/board/xes/common/fsl_8xxx_pci.c +++ b/board/xes/common/fsl_8xxx_pci.c @@ -34,57 +34,16 @@ #ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; #endif -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - -/* - * 85xx and 86xx share naming conventions, but different layout. - * Correlate names to CPU-specific values to share common - * PCI code. - */ -#if defined(CONFIG_MPC85xx) -#define MPC8xxx_DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE -#define MPC8xxx_DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2 -#define MPC8xxx_DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3 -#define MPC8xxx_PORDEVSR_IO_SEL MPC85xx_PORDEVSR_IO_SEL -#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT MPC85xx_PORDEVSR_IO_SEL_SHIFT -#define MPC8xxx_PORBMSR_HA MPC85xx_PORBMSR_HA -#define MPC8xxx_PORBMSR_HA_SHIFT MPC85xx_PORBMSR_HA_SHIFT -#elif defined(CONFIG_MPC86xx) -#define MPC8xxx_DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIEX1 -#define MPC8xxx_DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIEX2 -#define MPC8xxx_DEVDISR_PCIE3 0 /* 8641 doesn't have PCIe3 */ -#define MPC8xxx_PORDEVSR_IO_SEL MPC8641_PORDEVSR_IO_SEL -#define MPC8xxx_PORDEVSR_IO_SEL_SHIFT MPC8641_PORDEVSR_IO_SEL_SHIFT -#define MPC8xxx_PORBMSR_HA MPC8641_PORBMSR_HA -#define MPC8xxx_PORBMSR_HA_SHIFT MPC8641_PORBMSR_HA_SHIFT -#endif void pci_init_board(void) { - struct fsl_pci_info pci_info[3]; int first_free_busno = 0; - int num = 0; - int pcie_ep; - __maybe_unused int pcie_configured; - -#if defined(CONFIG_MPC85xx) - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#elif defined(CONFIG_MPC86xx) - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; -#endif - u32 devdisr = in_be32(&gur->devdisr); #ifdef CONFIG_PCI1 - u32 pordevsr = in_be32(&gur->pordevsr); + int pcie_ep; + struct fsl_pci_info pci_info; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr = in_be32(&gur->devdisr); uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD; uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; @@ -92,8 +51,13 @@ void pci_init_board(void) uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + SET_STD_PCI_INFO(pci_info, 1); + set_next_law(pci_info.mem_phys, + law_size_bits(pci_info.mem_size), pci_info.law); + set_next_law(pci_info.io_phys, + law_size_bits(pci_info.io_size), pci_info.law); + + pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs); printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n", pci_32 ? 32 : 64, pcix ? "PCIX" : "PCI", @@ -102,66 +66,18 @@ void pci_init_board(void) pcie_ep ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter"); - first_free_busno = fsl_pci_init_port(&pci_info[num++], + first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); } else { printf("PCI1: disabled\n"); } #elif defined CONFIG_MPC8548 + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); /* PCI1 not present on MPC8572 */ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); #endif -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) { - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected as %s\n", - pcie_ep ? "Endpoint" : "Root Complex"); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1); -#endif /* CONFIG_PCIE1 */ - -#ifdef CONFIG_PCIE2 - pcie_configured = is_serdes_configured(PCIE2); - - if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) { - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf("PCIE2: connected as %s\n", - pcie_ep ? "Endpoint" : "Root Complex"); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - } else { - printf("PCIE2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2); -#endif /* CONFIG_PCIE2 */ - -#ifdef CONFIG_PCIE3 - pcie_configured = is_serdes_configured(PCIE3); - - if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) { - SET_STD_PCIE_INFO(pci_info[num], 3); - pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); - printf("PCIE3: connected as %s\n", - pcie_ep ? "Endpoint" : "Root Complex"); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie3_hose, first_free_busno); - } else { - printf("PCIE3: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3); -#endif /* CONFIG_PCIE3 */ + fsl_pcie_init_board(first_free_busno); } #if defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/xes/xpedite517x/law.c b/board/xes/xpedite517x/law.c index 0b7d9ef8d..df23df1ba 100644 --- a/board/xes/xpedite517x/law.c +++ b/board/xes/xpedite517x/law.c @@ -39,14 +39,6 @@ struct law_entry law_table[] = { /* NAND LAW covers 2 NAND flashes */ SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC), #endif -#ifdef CONFIG_SYS_PCIE1_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), -#endif -#ifdef CONFIG_SYS_PCIE2_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), -#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite520x/law.c b/board/xes/xpedite520x/law.c index bbfcb9da8..5c1fcd2b1 100644 --- a/board/xes/xpedite520x/law.c +++ b/board/xes/xpedite520x/law.c @@ -38,14 +38,6 @@ struct law_entry law_table[] = { /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#if CONFIG_SYS_PCI1_MEM_PHYS - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1), -#endif -#if CONFIG_SYS_PCI2_MEM_PHYS - SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2), -#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite537x/law.c b/board/xes/xpedite537x/law.c index daee676c4..54c28dad3 100644 --- a/board/xes/xpedite537x/law.c +++ b/board/xes/xpedite537x/law.c @@ -37,18 +37,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_PCIE1_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), -#endif -#ifdef CONFIG_SYS_PCIE2_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), -#endif -#ifdef CONFIG_SYS_PCIE3_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3), - SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3), -#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite550x/law.c b/board/xes/xpedite550x/law.c index 4d4445d31..66f1cf9cd 100644 --- a/board/xes/xpedite550x/law.c +++ b/board/xes/xpedite550x/law.c @@ -37,18 +37,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_PCIE1_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), -#endif -#ifdef CONFIG_SYS_PCIE2_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), -#endif -#ifdef CONFIG_SYS_PCIE3_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3), - SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3), -#endif }; int num_law_entries = ARRAY_SIZE(law_table); From 48f27919aa85c6f545d42093f389bd1d312d5744 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 10:23:45 -0600 Subject: [PATCH 39/63] powerpc/85xx: Rework TQM boards pci_init_board to use common FSL PCIe code Remove duplicated code in TQM 85xx boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala CC: wd@denx.de --- board/tqc/tqm85xx/law.c | 9 +------ board/tqc/tqm85xx/tqm85xx.c | 47 ++++++++++++------------------------- 2 files changed, 16 insertions(+), 40 deletions(-) diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c index e684ba2c2..c596303c5 100644 --- a/board/tqc/tqm85xx/law.c +++ b/board/tqc/tqm85xx/law.c @@ -67,20 +67,13 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR), - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), -#ifdef CONFIG_PCIE1 - SET_LAW(CONFIG_SYS_PCIE1_MEM_BUS, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1), -#else /* !CONFIG_PCIE1 */ +#ifndef CONFIG_PCIE1 SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO), #endif /* CONFIG_PCIE1 */ #if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND) SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), #endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */ -#ifdef CONFIG_PCIE1 - SET_LAW(CONFIG_SYS_PCIE1_IO_BUS, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1), -#endif /* CONFIG_PCIE */ }; int num_law_entries = ARRAY_SIZE (law_table); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 43c73e19e..99b13311c 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -541,31 +541,29 @@ void local_bus_init (void) static struct pci_controller pci1_hose; #endif /* CONFIG_PCI1 */ -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif /* CONFIG_PCIE1 */ - void pci_init_board (void) { - struct fsl_pci_info pci_info[2]; - int first_free_busno = 0; - int num = 0; - int pcie_ep; - __maybe_unused int pcie_configured; - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 devdisr = in_be32(&gur->devdisr); - u32 pordevsr = in_be32(&gur->pordevsr); - + int first_free_busno = 0; #ifdef CONFIG_PCI1 + struct fsl_pci_info pci_info; + int pcie_ep; + + u32 devdisr = in_be32(&gur->devdisr); + uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + SET_STD_PCI_INFO(pci_info, 1); + set_next_law(pci_info.mem_phys, + law_size_bits(pci_info.mem_size), pci_info.law); + set_next_law(pci_info.io_phys, + law_size_bits(pci_info.io_size), pci_info.law); + + pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs); printf("PCI1: %d bit, %s MHz, %s, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33333333) ? "33" : @@ -573,7 +571,7 @@ void pci_init_board (void) pci_clk_sel ? "sync" : "async", pcie_ep ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter"); - first_free_busno = fsl_pci_init_port(&pci_info[num++], + first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); #ifdef CONFIG_PCIX_CHECK if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) { @@ -596,22 +594,7 @@ void pci_init_board (void) setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); #endif -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected as %s\n", - pcie_ep ? "Endpoint" : "Root Complex"); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); -#endif /* CONFIG_PCIE1 */ + fsl_pcie_init_board(first_free_busno); } #ifdef CONFIG_OF_BOARD_SETUP From 3f6f9d76415072571029b646a6aefc067a635bde Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 10:13:19 -0600 Subject: [PATCH 40/63] powerpc/85xx: Rework MPC8568MDS pci_init_board to use common FSL PCIe code Remove duplicated code in MPC8568MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala --- board/freescale/mpc8568mds/law.c | 6 +--- board/freescale/mpc8568mds/mpc8568mds.c | 47 +++++++------------------ include/configs/MPC8568MDS.h | 3 +- 3 files changed, 16 insertions(+), 40 deletions(-) diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c index 3114e8a17..e24b72bfe 100644 --- a/board/freescale/mpc8568mds/law.c +++ b/board/freescale/mpc8568mds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008, 2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -50,10 +50,6 @@ */ struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index a504f8a9d..5cda81c31 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -266,10 +266,6 @@ static struct pci_controller pci1_hose = { }; #endif /* CONFIG_PCI */ -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif /* CONFIG_PCIE1 */ - /* * pib_init() -- Initialize the PCA9555 IO expander on the PIB board */ @@ -316,13 +312,11 @@ pib_init(void) void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[2]; + int first_free_busno = 0; +#ifdef CONFIG_PCI1 + struct fsl_pci_info pci_info; u32 devdisr, pordevsr, io_sel; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; - int first_free_busno = 0; - int num = 0; - - int pcie_ep, pcie_configured; devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); @@ -331,15 +325,19 @@ void pci_init_board(void) debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); -#ifdef CONFIG_PCI1 pci_speed = 66666000; pci_32 = 1; pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info[num], 1); - pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + SET_STD_PCI_INFO(pci_info, 1); + set_next_law(pci_info.mem_phys, + law_size_bits(pci_info.mem_size), pci_info.law); + set_next_law(pci_info.io_phys, + law_size_bits(pci_info.io_size), pci_info.law); + + pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : @@ -347,9 +345,9 @@ void pci_init_board(void) pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", - pci_info[num].regs); + pci_info.regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], + first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); } else { printf("PCI: disabled\n"); @@ -360,26 +358,7 @@ void pci_init_board(void) setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif + fsl_pcie_init_board(first_free_busno); } #endif /* CONFIG_PCI */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 7817fba2f..a491650ab 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007 Freescale Semiconductor. + * Copyright 2004-2007, 2010 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -293,6 +293,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ +#define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 From 94f2bc486043365f253892342a3ab75371b1444a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 10:18:07 -0600 Subject: [PATCH 41/63] powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe code Remove duplicated code in MPC8569MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala --- board/freescale/mpc8569mds/law.c | 4 +-- board/freescale/mpc8569mds/mpc8569mds.c | 39 +------------------------ include/configs/MPC8569MDS.h | 1 + 3 files changed, 3 insertions(+), 41 deletions(-) diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c index 60eea45a8..bcd03116f 100644 --- a/board/freescale/mpc8569mds/law.c +++ b/board/freescale/mpc8569mds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -51,8 +51,6 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR), #endif - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 07db16aa0..ecda22299 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -518,51 +518,14 @@ static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd) clrbits_8(&bcsr[17], BCSR17_nUSBEN); } -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif /* CONFIG_PCIE1 */ - #ifdef CONFIG_PCI void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[1]; - u32 devdisr, pordevsr, io_sel; - int first_free_busno = 0; - int num = 0; - - int pcie_ep, pcie_configured; - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - - debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - #if defined(CONFIG_PQ_MDS_PIB) pib_init(); #endif -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif - + fsl_pcie_init_board(0); } #endif /* CONFIG_PCI */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 177d5d536..814c17546 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -345,6 +345,7 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory Addresses are mapped 1-1. I/O is mapped from 0 */ +#define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 From 06eb4d8c68d2ea72da398c88c077fc2fb7cca6d9 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 10:42:01 -0600 Subject: [PATCH 42/63] powerpc/85xx: Rework P1_P2_RDB pci_init_board to use common FSL PCIe code Remove duplicated code in P1_P2_RDB boards and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/law.c | 6 +--- board/freescale/p1_p2_rdb/pci.c | 58 +-------------------------------- include/configs/P1_P2_RDB.h | 2 ++ 3 files changed, 4 insertions(+), 62 deletions(-) diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c index 1320d5da0..4c80fa6ed 100644 --- a/board/freescale/p1_p2_rdb/law.c +++ b/board/freescale/p1_p2_rdb/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -26,10 +26,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index 2034459b6..bd1a91e31 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -32,65 +32,9 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[2]; - u32 devdisr, pordevsr; - int first_free_busno = 0; - int num = 0; - - int pcie_ep, pcie_configured; - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - - puts("\n"); -#ifdef CONFIG_PCIE2 - pcie_configured = is_serdes_configured(PCIE2); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - } else { - printf("PCIE2: disabled\n"); - } - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif + fsl_pcie_init_board(0); } void ft_pci_board_setup(void *blob) diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index d479a0985..6862e6db9 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -358,6 +358,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 @@ -368,6 +369,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 From b8526212ca1e299d8833f413b737a326bf484ee4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 10:42:33 -0600 Subject: [PATCH 43/63] powerpc/86xx: Rework MPC8610HPCD pci_init_board to use common FSL PCIe code Remove duplicated code in MPC8610HPCD board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala --- board/freescale/mpc8610hpcd/law.c | 8 +-- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 72 +++++------------------ include/configs/MPC8610HPCD.h | 4 +- 3 files changed, 19 insertions(+), 65 deletions(-) diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c index 0fc838484..26e41b6ab 100644 --- a/board/freescale/mpc8610hpcd/law.c +++ b/board/freescale/mpc8610hpcd/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008,2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -31,14 +31,8 @@ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1), #endif - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 8abd91788..d7dd470c3 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -213,78 +213,34 @@ config_table:pci_mpc86xxcts_config_table }; #endif /* CONFIG_PCI */ -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - void pci_init_board(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; - struct fsl_pci_info pci_info[3]; + struct fsl_pci_info pci_info; u32 devdisr, pordevsr; - int first_free_busno = 0; - int num = 0; - - int pci_agent, pcie_ep, pcie_configured; + int first_free_busno; + int pci_agent; devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - pcie_configured = is_serdes_configured(PCIE2); - - if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){ - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf("PCIE2: connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - } else { - printf("PCIE2: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */ -#endif + first_free_busno = fsl_pcie_init_board(0); #ifdef CONFIG_PCI1 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info[num], 1); - pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + SET_STD_PCI_INFO(pci_info, 1); + set_next_law(pci_info.mem_phys, + law_size_bits(pci_info.mem_size), pci_info.law); + set_next_law(pci_info.io_phys, + law_size_bits(pci_info.io_size), pci_info.law); + + pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); printf("PCI: connected to PCI slots as %s" \ " (base address %lx)\n", pci_agent ? "Agent" : "Host", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], + pci_info.regs); + first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); } else { printf("PCI: disabled\n"); @@ -294,6 +250,8 @@ void pci_init_board(void) #else setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ #endif + + fsl_pcie_init_board(first_free_busno); } #if defined(CONFIG_OF_BOARD_SETUP) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 17dac6c74..03ee394b3 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007, 2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -276,6 +276,7 @@ #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ /* controller 1, Base address 0xa000 */ +#define CONFIG_SYS_PCIE1_NAME "ULI" #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ @@ -284,6 +285,7 @@ #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ /* controller 2, Base Address 0x9000 */ +#define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ From c51136ec45b924a9c4f34a2e4ab16dc2606c40a5 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 10:26:44 -0600 Subject: [PATCH 44/63] powerpc/86xx: Rework SBC8641 pci_init_board to use common FSL PCIe code Remove duplicated code in SBC8641 board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala CC: Paul Gortmaker --- board/sbc8641d/law.c | 4 --- board/sbc8641d/sbc8641d.c | 63 ++------------------------------------- 2 files changed, 2 insertions(+), 65 deletions(-) diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c index 705e1c296..a6f60eeb6 100644 --- a/board/sbc8641d/law.c +++ b/board/sbc8641d/law.c @@ -49,11 +49,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), #endif - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) }; diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 5ee8f73c2..5c30b2676 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -181,70 +181,11 @@ long int fixed_sdram (void) * Initialize PCI Devices, report devices found. */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_fsl86xxads_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, - {} -}; -#endif - -static struct pci_controller pcie1_hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc86xxcts_config_table -#endif -}; -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif /* CONFIG_PCIE2 */ - -int first_free_busno = 0; - void pci_init_board(void) { - struct fsl_pci_info pci_info[2]; - volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - uint devdisr = in_be32(&gur->devdisr); - int pcie_ep; - int num = 0; - -#ifdef CONFIG_PCIE1 - int pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - puts("PCIE1: disabled\n"); - } -#else - puts("PCIE1: disabled\n"); -#endif /* CONFIG_PCIE1 */ - -#ifdef CONFIG_PCIE2 - - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf("PCIE2: connected as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); -#else - puts("PCIE2: disabled\n"); -#endif /* CONFIG_PCIE2 */ + fsl_pcie_init_board(0); } +#endif /* CONFIG_PCI */ #if defined(CONFIG_OF_BOARD_SETUP) From 2d0a054d55665dee16343468b2ae8a0f8387dae1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 17 Dec 2010 10:30:44 -0600 Subject: [PATCH 45/63] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code Remove duplicated code in SBC8548 board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala Tested-by: Paul Gortmaker --- board/sbc8548/law.c | 8 ------- board/sbc8548/sbc8548.c | 50 +++++++++++------------------------------ 2 files changed, 13 insertions(+), 45 deletions(-) diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index 6d1efc0c6..5fa9db02f 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -49,14 +49,6 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), -#endif -#ifdef CONFIG_SYS_PCI1_MEM_PHYS - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), -#endif -#ifdef CONFIG_SYS_PCIE1_MEM_PHYS - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), #endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index ff3920bc9..e1a3ea36e 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -266,33 +266,19 @@ phys_size_t fixed_sdram(void) static struct pci_controller pci1_hose; #endif /* CONFIG_PCI1 */ -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif /* CONFIG_PCIE1 */ - - #ifdef CONFIG_PCI void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[2]; - u32 devdisr, pordevsr, porpllsr, io_sel; int first_free_busno = 0; - int num = 0; - -#ifdef CONFIG_PCIE1 - int pcie_configured; -#endif - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - porpllsr = in_be32(&gur->porpllsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - - debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); #ifdef CONFIG_PCI1 + struct fsl_pci_info pci_info; + u32 devdisr = in_be32(&gur->devdisr); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 porpllsr = in_be32(&gur->porpllsr); + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; @@ -306,8 +292,13 @@ pci_init_board(void) pci_clk_sel ? "sync" : "async", pci_arb ? "arbiter" : "external-arbiter"); - SET_STD_PCI_INFO(pci_info[num], 1); - first_free_busno = fsl_pci_init_port(&pci_info[num++], + SET_STD_PCI_INFO(pci_info, 1); + set_next_law(pci_info.mem_phys, + law_size_bits(pci_info.mem_size), pci_info.law); + set_next_law(pci_info.io_phys, + law_size_bits(pci_info.io_size), pci_info.law); + + first_free_busno = fsl_pci_init_port(&pci_info, &pci1_hose, first_free_busno); } else { printf("PCI: disabled\n"); @@ -320,22 +311,7 @@ pci_init_board(void) setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */ -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - SET_STD_PCIE_INFO(pci_info[num], 1); - printf("PCIE: base address %lx\n", pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif + fsl_pcie_init_board(first_free_busno); } #endif From e650ae1bb7453dc114bcb8565d76dd1ed334936b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 6 Jan 2011 10:39:52 -0600 Subject: [PATCH 46/63] powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe code Remove duplicated code in corenet_ds boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala --- board/freescale/corenet_ds/pci.c | 118 +------------------------------ 1 file changed, 2 insertions(+), 116 deletions(-) diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c index 775b623cc..18a75de8c 100644 --- a/board/freescale/corenet_ds/pci.c +++ b/board/freescale/corenet_ds/pci.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -28,123 +28,9 @@ #include #include -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - -#ifdef CONFIG_PCIE4 -static struct pci_controller pcie4_hose; -#endif - void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[4]; - u32 devdisr; - int first_free_busno = 0; - int num = 0; - - int pcie_ep, pcie_configured; - - devdisr = in_be32(&gur->devdisr); - - debug (" pci_init_board: devdisr=%x\n", devdisr); - -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE1)) { - set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, - LAW_TRGT_IF_PCIE_1); - set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_1); - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - pcie_configured = is_serdes_configured(PCIE2); - - if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE2)) { - set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, - LAW_TRGT_IF_PCIE_2); - set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_2); - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf("PCIE2: connected to Slot 3 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - } else { - printf("PCIE2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCIE3 - pcie_configured = is_serdes_configured(PCIE3); - - if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE3)) { - set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, - LAW_TRGT_IF_PCIE_3); - set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_3); - SET_STD_PCIE_INFO(pci_info[num], 3); - pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); - printf("PCIE3: connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie3_hose, first_free_busno); - } else { - printf("PCIE3: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */ -#endif - -#ifdef CONFIG_PCIE4 - pcie_configured = is_serdes_configured(PCIE4); - - if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) { - set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M, - LAW_TRGT_IF_PCIE_4); - set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_4); - SET_STD_PCIE_INFO(pci_info[num], 4); - pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs); - printf("PCIE4: connected to as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie4_hose, first_free_busno); - } else { - printf("PCIE4: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */ -#endif + fsl_pcie_init_board(0); } void pci_of_setup(void *blob, bd_t *bd) From 213ac73e2caff8b477c31f85d8132f8cc116f366 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Tue, 28 Dec 2010 17:47:25 -0600 Subject: [PATCH 47/63] fsl_pci: Update PCIe boot ouput This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to ..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/fsl_pci.h | 2 +- drivers/pci/fsl_pci_init.c | 38 ++++++++++++++++-------------- 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 15ab50d95..0a98bdee3 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -27,7 +27,6 @@ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); -void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr); @@ -172,6 +171,7 @@ struct fsl_pci_info { int pci_num; }; +void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info); int fsl_pci_init_port(struct fsl_pci_info *pci_info, struct pci_controller *hose, int busno); int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index d7623369f..6c168c141 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -217,8 +217,10 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, return 1; } -void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) +void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) { + u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; + u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data; u16 temp16; u32 temp32; int enabled, r, inbound = 0; @@ -235,10 +237,6 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) u64 out_hi = 0, out_lo = -1ULL; u32 pcicsrbar, pcicsrbar_sz; -#ifdef DEBUG - int neg_link_w; -#endif - pci_setup_indirect(hose, cfg_addr, cfg_data); /* Handle setup of outbound windows first */ @@ -354,20 +352,20 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) #endif if (!enabled) { - debug("....PCIE link error. Skipping scan." - "LTSSM=0x%02x\n", ltssm); + /* Let the user know there's no PCIe link */ + printf("no link, regs @ 0x%lx\n", pci_info->regs); hose->last_busno = hose->first_busno; return; } out_be32(&pci->pme_msg_det, 0xffffffff); out_be32(&pci->pme_msg_int_en, 0xffffffff); -#ifdef DEBUG + + /* Print the negotiated PCIe link width */ pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); - neg_link_w = (temp16 & 0x3f0 ) >> 4; - printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", - ltssm, neg_link_w); -#endif + printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, + pci_info->regs); + hose->current_busno++; /* Start scan with secondary */ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); } @@ -476,7 +474,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, hose->region_count = r - hose->regions; hose->first_busno = busno; - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); + fsl_pci_init(hose, pci_info); if (fsl_is_pci_agent(hose)) { fsl_pci_config_unlock(hose); @@ -485,7 +483,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? - "E" : "", pci_info->pci_num, + "e" : "", pci_info->pci_num, hose->first_busno, hose->last_busno); return(hose->last_busno + 1); @@ -525,10 +523,14 @@ int fsl_configure_pcie(struct fsl_pci_info *info, set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); + is_endpoint = fsl_setup_hose(hose, info->regs); - printf("PCIE%u: connected to %s as %s (base addr %lx)\n", - info->pci_num, connected, - is_endpoint ? "Endpoint" : "Root Complex", info->regs); + printf("PCIe%u: %s", info->pci_num, + is_endpoint ? "Endpoint" : "Root Complex"); + if (connected) + printf(" of %s", connected); + puts(", "); + return fsl_pci_init_port(info, hose, busno); } @@ -606,7 +608,7 @@ int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, busno = fsl_configure_pcie(pci_info, hose, board_serdes_name(dev), busno); } else { - printf("PCIE%d: disabled\n", num + 1); + printf("PCIe%d: disabled\n", num + 1); } return busno; From a09b9b68d492e978ef0e14cae93ff9cfbc2d3e4b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 30 Dec 2010 12:09:53 -0600 Subject: [PATCH 48/63] powerpc/8xxx: Refactor SRIO initialization into common code Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala Acked-by: Wolfgang Denk --- README | 18 ++++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 ++- arch/powerpc/cpu/mpc85xx/fdt.c | 7 +- arch/powerpc/cpu/mpc8xxx/Makefile | 1 + arch/powerpc/cpu/mpc8xxx/fdt.c | 23 ++++++- arch/powerpc/cpu/mpc8xxx/srio.c | 86 +++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_law.h | 1 + board/freescale/corenet_ds/corenet_ds.c | 44 ------------- include/configs/corenet_ds.h | 19 +++--- 9 files changed, 151 insertions(+), 56 deletions(-) create mode 100644 arch/powerpc/cpu/mpc8xxx/srio.c diff --git a/README b/README index d7a23cda9..556bf59c1 100644 --- a/README +++ b/README @@ -2783,6 +2783,24 @@ Low Level (hardware related) configuration options: Disable PCI-Express on systems where it is supported but not required. +- CONFIG_SYS_SRIO: + Chip has SRIO or not + +- CONFIG_SRIO1: + Board has SRIO 1 port available + +- CONFIG_SRIO2: + Board has SRIO 2 port available + +- CONFIG_SYS_SRIOn_MEM_VIRT: + Virtual Address of SRIO port 'n' memory region + +- CONFIG_SYS_SRIOn_MEM_PHYS: + Physical Address of SRIO port 'n' memory region + +- CONFIG_SYS_SRIOn_MEM_SIZE: + Size of SRIO port 'n' memory region + - CONFIG_SPD_EEPROM Get DDR timing information from an I2C EEPROM. Common with pluggable memory modules such as SODIMMs diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4a6cc6566..1d016c4d0 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com @@ -40,6 +40,8 @@ DECLARE_GLOBAL_DATA_PTR; +extern void srio_init(void); + #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -384,6 +386,10 @@ int cpu_init_r(void) /* needs to be in ram since code uses global static vars */ fsl_serdes_init(); +#ifdef CONFIG_SYS_SRIO + srio_init(); +#endif + #if defined(CONFIG_MP) setup_mp(); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 53e059655..00fa75299 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; extern void ft_qe_setup(void *blob); extern void ft_fixup_num_cores(void *blob); +extern void ft_srio_setup(void *blob); #ifdef CONFIG_MP #include "mp.h" @@ -478,4 +479,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_qportals(blob); #endif + +#ifdef CONFIG_SYS_SRIO + ft_srio_setup(blob); +#endif } diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 95c73be88..5dfd65b88 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -16,6 +16,7 @@ endif COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o +COBJS-$(CONFIG_SYS_SRIO) += srio.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 54e60bb1a..0c166fd6c 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains @@ -28,6 +28,7 @@ #include #include #include +#include #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -239,3 +240,23 @@ int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc) return fdt_setprop_string(blob, offset, "phy-connection-type", fsl_phy_enet_if_str[phyc]); } + +#ifdef CONFIG_SYS_SRIO +void ft_srio_setup(void *blob) +{ +#ifdef CONFIG_SRIO1 + if (!is_serdes_configured(SRIO1)) { + fdt_del_node_and_alias(blob, "rio0"); + } +#else + fdt_del_node_and_alias(blob, "rio0"); +#endif +#ifdef CONFIG_SRIO2 + if (!is_serdes_configured(SRIO2)) { + fdt_del_node_and_alias(blob, "rio1"); + } +#else + fdt_del_node_and_alias(blob, "rio1"); +#endif +} +#endif diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c new file mode 100644 index 000000000..e46d32806 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -0,0 +1,86 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#if defined(CONFIG_FSL_CORENET) + #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 + #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 + #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC85xx) + #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO + #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO + #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC86xx) + #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO + #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO + #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ + (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) +#else +#error "No defines for DEVDISR_SRIO" +#endif + +void srio_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; + int srio1_used = 0, srio2_used = 0; + + if (is_serdes_configured(SRIO1)) { + set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS, + law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), + LAW_TRGT_IF_RIO_1); + srio1_used = 1; + printf("SRIO1: enabled\n"); + } else { + printf("SRIO1: disabled\n"); + } + +#ifdef CONFIG_SRIO2 + if (is_serdes_configured(SRIO2)) { + set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS, + law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), + LAW_TRGT_IF_RIO_2); + srio2_used = 1; + printf("SRIO2: enabled\n"); + } else { + printf("SRIO2: disabled\n"); + } +#endif + +#ifdef CONFIG_FSL_CORENET + /* On FSL_CORENET devices we can disable individual ports */ + if (!srio1_used) + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); + if (!srio2_used) + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); +#endif + + /* neither port is used - disable everything */ + if (!srio1_used && !srio2_used) { + setbits_be32(&gur->devdisr, _DEVDISR_SRIO1); + setbits_be32(&gur->devdisr, _DEVDISR_SRIO2); + setbits_be32(&gur->devdisr, _DEVDISR_RMU); + } +} diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index 0e255ffce..6a4279ce9 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -90,6 +90,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 +#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO #ifdef CONFIG_MPC8641 #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index f183cf61d..232dc7297 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -157,34 +157,10 @@ static const char *serdes_clock_to_string(u32 clock) int misc_init_r(void) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - __maybe_unused ccsr_gur_t *gur; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw3; - gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_SRIO1 - if (is_serdes_configured(SRIO1)) { - set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_1); - } else { - printf (" SRIO1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ -#endif - -#ifdef CONFIG_SRIO2 - if (is_serdes_configured(SRIO2)) { - set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_2); - } else { - printf (" SRIO2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ -#endif - /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. @@ -217,24 +193,6 @@ void board_lmb_reserve(struct lmb *lmb) } #endif -void ft_srio_setup(void *blob) -{ -#ifdef CONFIG_SRIO1 - if (!is_serdes_configured(SRIO1)) { - fdt_del_node_and_alias(blob, "rio0"); - } -#else - fdt_del_node_and_alias(blob, "rio0"); -#endif -#ifdef CONFIG_SRIO2 - if (!is_serdes_configured(SRIO2)) { - fdt_del_node_and_alias(blob, "rio1"); - } -#else - fdt_del_node_and_alias(blob, "rio1"); -#endif -} - void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -242,8 +200,6 @@ void ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); - ft_srio_setup(blob); - base = getenv_bootm_low(); size = getenv_bootm_size(); diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index e1cd1b0b0..d1ac756b5 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -51,6 +51,7 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +#define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ @@ -265,21 +266,21 @@ /* * RapidIO */ -#define CONFIG_SYS_RIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_RIO1_MEM_PHYS 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_RIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_RIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull #else -#define CONFIG_SYS_RIO2_MEM_PHYS 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 #endif -#define CONFIG_SYS_RIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * General PCI From 8b47d7ec9bbb7c3022aa758a971acb7335ea1cdf Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 4 Jan 2011 17:57:59 -0600 Subject: [PATCH 49/63] powerpc/85xx: Convert MPC8548CDS to use common SRIO init code Signed-off-by: Kumar Gala --- board/freescale/mpc8548cds/law.c | 5 +---- board/freescale/mpc8548cds/tlb.c | 9 ++++----- include/configs/MPC8548CDS.h | 15 ++++++++------- 3 files changed, 13 insertions(+), 16 deletions(-) diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index e59fee807..5b6943da9 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008,2010 Freescale Semiconductor, Inc. + * Copyright 2008,2010-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -57,9 +57,6 @@ struct law_entry law_table[] = { #endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_RIO_MEM_PHYS - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), -#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index 2267ad747..b2c1b31af 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008, 2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -58,21 +58,20 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1G, 1), -#ifdef CONFIG_SYS_RIO_MEM_PHYS /* * TLB 2: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), /* * TLB 3: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), -#endif + /* * TLB 5: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4c5b99842..ececa3875 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007, 2010 Freescale Semiconductor. + * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -40,10 +40,12 @@ #define CONFIG_SYS_TEXT_BASE 0xfff80000 #endif +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI /* enable any pci type devices */ #define CONFIG_PCI1 /* PCI controller 1 */ #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#undef CONFIG_RIO #undef CONFIG_PCI2 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ @@ -364,14 +366,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif -#ifdef CONFIG_RIO /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 -#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ -#endif +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ #ifdef CONFIG_LEGACY #define BRIDGE_ID 17 From 5f7bbd13a89940fc349e8ce63566e205d8514a62 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 4 Jan 2011 18:01:49 -0600 Subject: [PATCH 50/63] powerpc/85xx: Convert MPC8568MDS to use common SRIO init code Signed-off-by: Kumar Gala --- board/freescale/mpc8568mds/law.c | 3 +-- include/configs/MPC8568MDS.h | 12 ++++++++---- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c index e24b72bfe..c5cf7ba81 100644 --- a/board/freescale/mpc8568mds/law.c +++ b/board/freescale/mpc8568mds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008, 2010 Freescale Semiconductor, Inc. + * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -50,7 +50,6 @@ */ struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index a491650ab..f684e7969 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007, 2010 Freescale Semiconductor. + * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -35,6 +35,9 @@ #define CONFIG_SYS_TEXT_BASE 0xfff80000 +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* PCI controller */ #define CONFIG_PCIE1 1 /* PCIE controller */ @@ -303,9 +306,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ -#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ #ifdef CONFIG_QE /* From e5fe96b1ab84f8b2ce7aa26dc4cae52db07dc400 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 4 Jan 2011 18:04:01 -0600 Subject: [PATCH 51/63] powerpc/85xx: Convert MPC8569MDS to use common SRIO init code Signed-off-by: Kumar Gala --- board/freescale/mpc8569mds/law.c | 3 +-- include/configs/MPC8569MDS.h | 12 ++++++++---- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c index bcd03116f..4f4a93b8f 100644 --- a/board/freescale/mpc8569mds/law.c +++ b/board/freescale/mpc8569mds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -52,7 +52,6 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR), #endif SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 814c17546..3372d186b 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -35,6 +35,9 @@ #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI 1 /* Disable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ @@ -355,9 +358,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ -#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ #ifdef CONFIG_QE /* From 56551362086adaee7afb08ed618ac8e46b5f53ae Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 4 Jan 2011 17:07:54 -0600 Subject: [PATCH 52/63] powerpc/86xx: Enable common SRIO init code Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc86xx/cpu_init.c | 7 ++++++- arch/powerpc/cpu/mpc86xx/fdt.c | 7 ++++++- arch/powerpc/include/asm/immap_86xx.h | 4 +++- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c index 1d35c0c65..802202478 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc86xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2004,2009-2010 Freescale Semiconductor, Inc. + * Copyright 2004,2009-2011 Freescale Semiconductor, Inc. * Jeff Brown * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -34,6 +34,7 @@ #include #include +extern void srio_init(void); void setup_bats(void); DECLARE_GLOBAL_DATA_PTR; @@ -80,6 +81,10 @@ int cpu_init_r(void) /* needs to be in ram since code uses global static vars */ fsl_serdes_init(); +#ifdef CONFIG_SYS_SRIO + srio_init(); +#endif + #if defined(CONFIG_MP) setup_mp(); #endif diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index ff89ee554..61f5110b7 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2008,2010 Freescale Semiconductor, Inc. + * Copyright 2008, 2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -14,6 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; extern void ft_fixup_num_cores(void *blob); +extern void ft_srio_setup(void *blob); void ft_cpu_setup(void *blob, bd_t *bd) { @@ -58,4 +59,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) ft_fixup_num_cores(blob); #endif + +#ifdef CONFIG_SYS_SRIO + ft_srio_setup(blob); +#endif } diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index 4e60cbb7a..cc338e473 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -1,7 +1,7 @@ /* * MPC86xx Internal Memory Map * - * Copyright 2004 Freescale Semiconductor + * Copyright 2004, 2011 Freescale Semiconductor * Jeff Brown (Jeffrey@freescale.com) * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -1205,6 +1205,8 @@ typedef struct ccsr_gur { #define MPC86xx_DEVDISR_PCI1 0x80000000 #define MPC86xx_DEVDISR_PCIE1 0x40000000 #define MPC86xx_DEVDISR_PCIE2 0x20000000 +#define MPC86xx_DEVDISR_SRIO 0x00080000 +#define MPC86xx_DEVDISR_RMSG 0x00040000 #define MPC86xx_DEVDISR_CPU0 0x00008000 #define MPC86xx_DEVDISR_CPU1 0x00004000 #define MPC86xx_RSTCR_HRST_REQ 0x00000002 From 1b77ca8afaca8657a59a9d3ac39c3375c946365c Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 4 Jan 2011 17:45:13 -0600 Subject: [PATCH 53/63] powerpc/86xx: Convert MPC8641HPCN to use common SRIO init code Signed-off-by: Kumar Gala --- board/freescale/mpc8641hpcn/law.c | 5 +---- include/configs/MPC8641HPCN.h | 30 +++++++++++++----------------- 2 files changed, 14 insertions(+), 21 deletions(-) diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c index 30a7b706f..08f1eb25a 100644 --- a/board/freescale/mpc8641hpcn/law.c +++ b/board/freescale/mpc8641hpcn/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008,2010 Freescale Semiconductor, Inc. + * Copyright 2008,2010-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -52,9 +52,6 @@ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), -#endif -#if defined(CONFIG_RIO) - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), #endif SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC), diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index fea087649..0cca603ff 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -1,5 +1,5 @@ /* - * Copyright 2006, 2010 Freescale Semiconductor. + * Copyright 2006, 2010-2011 Freescale Semiconductor. * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -57,18 +57,14 @@ */ #define CONFIG_SYS_SCRATCH_VA 0xe0000000 -/* - * set this to enable Rapid IO. PCI and RIO are mutually exclusive - */ -/*#define CONFIG_RIO 1*/ +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ -#ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#endif #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ @@ -319,13 +315,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */ +#define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL +#define CONFIG_SYS_SRIO1_MEM_PHYS 0x0000000c00000000ULL #else -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE #endif -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ /* * General PCI @@ -514,18 +510,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #else /* CONFIG_RIO */ -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ +#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \ +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ +#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #endif From 7cee1dfdf6d686a48cd9309ea0e55e2a4b3d2fc4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 4 Jan 2011 17:48:51 -0600 Subject: [PATCH 54/63] powerpc/86xx: Convert SBC8641 to use common SRIO init code Signed-off-by: Kumar Gala Tested-by: Paul Gortmaker --- board/sbc8641d/law.c | 1 - include/configs/sbc8641d.h | 15 +++++++++------ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c index a6f60eeb6..14259d6a1 100644 --- a/board/sbc8641d/law.c +++ b/board/sbc8641d/law.c @@ -51,7 +51,6 @@ struct law_entry law_table[] = { #endif SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 90d84eba8..8d9f931b7 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -57,6 +57,9 @@ */ #define CONFIG_SYS_SCRATCH_VA 0xe8000000 +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI 1 /* Enable PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ @@ -297,9 +300,9 @@ /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ +#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ /* * General PCI @@ -417,10 +420,10 @@ * BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U /* From 28a096e7f25d43824618d210b5b20b1961b94d79 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Thu, 30 Dec 2010 11:17:44 -0600 Subject: [PATCH 55/63] powerpc/85xx: Add SRIO support to P2020DS The P2020 has 2 SRIO ports and they are useable on the P2020 DS board. Enable them using the common SRIO init code. Signed-off-by: Li Yang Signed-off-by: Kumar Gala --- include/configs/P2020DS.h | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 24f2498d0..c2636af71 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -45,6 +45,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff80000 #endif +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ @@ -472,6 +476,24 @@ #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET #endif +/* SRIO1 uses the same window as PCIE2 mem window */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ + +/* SRIO2 uses the same window as PCIE1 mem window */ +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */ + #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ From d621da0066dff92a76ca3c6fb031a7f823a811f3 Mon Sep 17 00:00:00 2001 From: Jerry Huang Date: Thu, 6 Jan 2011 23:42:19 -0600 Subject: [PATCH 56/63] fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080) Do not issue a manual asynchronous CMD12. Instead, use a (software) synchronous CMD12 or AUTOCMD12 to abort data transfer. Signed-off-by: Jerry Huang Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 5 ++++- drivers/mmc/fsl_esdhc.c | 10 +++++++++- include/configs/P4080DS.h | 4 +++- 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 2d32532f2..0c4820c08 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -49,6 +49,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111) + puts("Work-around for Erratum ESDHC111 enabled\n"); #endif return 0; } diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index cef2859ec..fe94164b0 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1,5 +1,5 @@ /* - * Copyright 2007,2010 Freescale Semiconductor, Inc + * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc * Andy Fleming * * Based vaguely on the pxa mmc code: @@ -79,6 +79,9 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) if (data->blocks > 1) { xfertyp |= XFERTYP_MSBSEL; xfertyp |= XFERTYP_BCEN; +#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 + xfertyp |= XFERTYP_AC12EN; +#endif } if (data->flags & MMC_DATA_READ) @@ -234,6 +237,11 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; +#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 + if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) + return 0; +#endif + esdhc_write32(®s->irqstat, -1); sync(); diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 21b48e9c4..705b22601 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -35,6 +35,8 @@ #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 From 3b4456ec391877a950dd5e98ee20df6560f0e1af Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Fri, 7 Jan 2011 00:06:47 -0600 Subject: [PATCH 57/63] fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080) The default value of the SRS, VS18 and VS30 and ADMAS fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one. Clear these bits out when we read HOSTCAPBLT. Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ drivers/mmc/fsl_esdhc.c | 5 +++++ include/configs/P4080DS.h | 1 + 3 files changed, 9 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 0c4820c08..d5c34c867 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -52,6 +52,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111) puts("Work-around for Erratum ESDHC111 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135) + puts("Work-around for Erratum ESDHC135 enabled\n"); #endif return 0; } diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index fe94164b0..d01c926c4 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -472,6 +472,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) voltage_caps = 0; caps = regs->hostcapblt; + +#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 + caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | + ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); +#endif if (caps & ESDHC_HOSTCAPBLT_VS18) voltage_caps |= MMC_VDD_165_195; if (caps & ESDHC_HOSTCAPBLT_VS30) diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 705b22601..a15dd761b 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -36,6 +36,7 @@ #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 From ae026ffd1e1a3f98b13c121acf5a677a5925a0e1 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Fri, 7 Jan 2011 00:24:27 -0600 Subject: [PATCH 58/63] fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080) False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 ++++++++ include/configs/P4080DS.h | 1 + 3 files changed, 12 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index d5c34c867..4e2cb4a64 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -55,6 +55,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135) puts("Work-around for Erratum ESDHC135 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136) + puts("Work-around for Erratum ESDHC136 enabled\n"); #endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 1d016c4d0..354b22231 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -394,6 +394,14 @@ int cpu_init_r(void) setup_mp(); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136 + { + void *p; + p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; + setbits_be32(p, 1 << (31 - 14)); + } +#endif + #ifdef CONFIG_SYS_LBC_LCRR /* * Modify the CLKDIV field of LCRR register to improve the writing diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index a15dd761b..4dd7faa1b 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -37,6 +37,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC136 #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 From 3dbd5d7d7e2c98380779a48a422afa239d3bbdf4 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sun, 9 Jan 2011 14:06:28 -0600 Subject: [PATCH 59/63] powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr code Move the parsing of hwconfig to determine if to use spd into common code so we can share it across all boards instead of duplicating it everywhere. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 22 +++++++++++++++++++++- arch/powerpc/include/asm/fsl_ddr_sdram.h | 3 ++- board/freescale/corenet_ds/ddr.c | 18 ++---------------- 3 files changed, 25 insertions(+), 18 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 774c0e4b4..c641e8506 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -1,5 +1,5 @@ /* - * Copyright 2008, 2010 Freescale Semiconductor, Inc. + * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free @@ -387,3 +387,23 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) "Memory controller interleaving disabled.\n"); } } + +int fsl_use_spd(void) +{ + int use_spd = 0; + +#ifdef CONFIG_DDR_SPD + /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ + if (hwconfig_sub("fsl_ddr", "sdram")) { + if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd")) + use_spd = 1; + else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed")) + use_spd = 0; + else + use_spd = 1; + } else + use_spd = 1; +#endif + + return use_spd; +} diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 8ceae1845..3de2113bd 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -213,6 +213,7 @@ typedef struct memctl_options_s { } memctl_options_t; extern phys_size_t fsl_ddr_sdram(void); +extern int fsl_use_spd(void); /* * The 85xx boards have a common prototype for fixed_sdram so put the diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 2ee018868..85b6c78ef 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -288,24 +288,10 @@ void fsl_ddr_board_options(memctl_options_t *popts, phys_size_t initdram(int board_type) { phys_size_t dram_size; - int use_spd = 0; puts("Initializing...."); -#ifdef CONFIG_DDR_SPD - /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ - if (hwconfig_sub("fsl_ddr", "sdram")) { - if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd")) - use_spd = 1; - else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed")) - use_spd = 0; - else - use_spd = 1; - } else - use_spd = 1; -#endif - - if (use_spd) { + if (fsl_use_spd()) { puts("using SPD\n"); dram_size = fsl_ddr_sdram(); } else { From 7c57f3e85970819e72e45cdb89d6dfbb896d557b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 11 Jan 2011 00:52:35 -0600 Subject: [PATCH 60/63] powerpc/85xx: Bump up the CONFIG_SYS_BOOTM_LEN to 16M on FSL 85xx boards CONFIG_SYS_BOOTMAPSZ has been 16M on these boards for some time so we should also allow the kernel image to be up to 16M decompressed. Signed-off-by: Kumar Gala --- include/configs/MPC8536DS.h | 3 ++- include/configs/MPC8540ADS.h | 3 ++- include/configs/MPC8541CDS.h | 3 ++- include/configs/MPC8544DS.h | 3 ++- include/configs/MPC8548CDS.h | 1 + include/configs/MPC8555CDS.h | 3 ++- include/configs/MPC8560ADS.h | 3 ++- include/configs/MPC8568MDS.h | 1 + include/configs/MPC8569MDS.h | 4 ++-- include/configs/MPC8572DS.h | 3 ++- include/configs/P1022DS.h | 3 ++- include/configs/P1_P2_RDB.h | 3 ++- include/configs/P2020DS.h | 1 + include/configs/corenet_ds.h | 1 + 14 files changed, 24 insertions(+), 11 deletions(-) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 94a542cef..d1ae35db0 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009,2010 Freescale Semiconductor, Inc. + * Copyright 2007-2009,2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -718,6 +718,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 9386f6488..8b3aff8e0 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * (C) Copyright 2002,2003 Motorola,Inc. * Xianghua Xiao * @@ -424,6 +424,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 12ce6f7e6..7101230e5 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -436,6 +436,7 @@ extern unsigned long get_clock_freq(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index dc821a381..62bac6d64 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2010 Freescale Semiconductor, Inc. + * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -456,6 +456,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index ececa3875..43e2c2eb1 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -495,6 +495,7 @@ extern unsigned long get_clock_freq(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 334a4106d..106034db4 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -434,6 +434,7 @@ extern unsigned long get_clock_freq(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 744e4a395..15ebb6f16 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2011 Freescale Semiconductor. * (C) Copyright 2002,2003 Motorola,Inc. * Xianghua Xiao * @@ -465,6 +465,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index f684e7969..3674e495c 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -455,6 +455,7 @@ extern unsigned long get_clock_freq(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 3372d186b..9e24e1290 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -593,8 +593,8 @@ extern unsigned long get_clock_freq(void); * have to be in the first 16 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) - /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 9ec02cce9..ea15831b7 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008,2010 Freescale Semiconductor, Inc. + * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -692,6 +692,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 272bd9ff6..2b8fc7dec 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * Authors: Srikanth Srinivasan * Timur Tabi * @@ -400,6 +400,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 6862e6db9..80b0b4009 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -542,6 +542,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index c2636af71..b6e3260d3 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -633,6 +633,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index d1ac756b5..23bbd42af 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -532,6 +532,7 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ #ifdef CONFIG_CMD_KGDB #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ From 1d2c2a62e328db22c38e3dfb3c0a8a373333471b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 13 Jan 2011 01:54:01 -0600 Subject: [PATCH 61/63] powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080) CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 4 ++++ arch/powerpc/include/asm/immap_85xx.h | 3 ++- include/configs/P4080DS.h | 1 + 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 4e2cb4a64..ae6af4f96 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -59,6 +59,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136) puts("Work-around for Erratum ESDHC136 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 + puts("Work-around for Erratum CPC-A002 enabled\n"); +#endif + return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 354b22231..c822d871a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -142,6 +142,10 @@ static void enable_cpc(void) u32 cpccfg0 = in_be32(&cpc->cpccfg0); size += CPC_CFG0_SZ_K(cpccfg0); +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 + setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); +#endif + out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); /* Read back to sync write */ in_be32(&cpc->cpccsr0); diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 30c64ebb1..6b19ee858 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1,7 +1,7 @@ /* * MPC85xx Internal Memory Map * - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * Copyright(c) 2002,2003 Motorola Inc. * Xianghua Xiao (x.xiao@motorola.com) @@ -1619,6 +1619,7 @@ typedef struct cpc_corenet { #define CPC_SRCR0_SRAMEN 0x00000001 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 +#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 #endif /* CONFIG_SYS_FSL_CPC */ /* Global Utilities Block */ diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 4dd7faa1b..950c8bcaf 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -40,6 +40,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 #define CONFIG_SYS_P4080_ERRATUM_CPU22 +#define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 #include "corenet_ds.h" From 868da5936e40b8685c813c1eb31eed629eaae295 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 13 Jan 2011 01:56:18 -0600 Subject: [PATCH 62/63] powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080) CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 3 +++ arch/powerpc/include/asm/immap_85xx.h | 1 + include/configs/P4080DS.h | 1 + 4 files changed, 8 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index ae6af4f96..bf70d2d89 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -62,6 +62,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 puts("Work-around for Erratum CPC-A002 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 + puts("Work-around for Erratum CPC-A003 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index c822d871a..8ece97009 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -145,6 +145,9 @@ static void enable_cpc(void) #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 + setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); +#endif out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); /* Read back to sync write */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 6b19ee858..b96dec7ce 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1620,6 +1620,7 @@ typedef struct cpc_corenet { #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 +#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 #endif /* CONFIG_SYS_FSL_CPC */ /* Global Utilities Block */ diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 950c8bcaf..c8f542eab 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -41,6 +41,7 @@ #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 +#define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 #include "corenet_ds.h" From f133796da8ec87ccbafc9c492636def619d99401 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 13 Jan 2011 02:58:23 -0600 Subject: [PATCH 63/63] powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080) Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus monitor timeout. Set timeout to maximum to avoid. Based on a patch from Lan Chunhe Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 7 ++++++- arch/powerpc/include/asm/fsl_lbc.h | 4 +++- include/configs/P4080DS.h | 1 + 4 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index bf70d2d89..7dfa596f0 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -65,6 +65,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 puts("Work-around for Erratum CPC-A003 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001 + puts("Work-around for Erratum ELBC-A001 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 6f401e750..7598ebf45 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -34,6 +34,11 @@ void init_early_memctl_regs(void) { uint init_br1 = 1; +#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001 + /* Set the local bus monitor timeout value to the maximum */ + clrsetbits_be32(&(LBC_BASE_ADDR)->lbcr, LBCR_BMT|LBCR_BMTPS, 0xf); +#endif + #ifdef CONFIG_MPC85xx /* if cs1 is already set via debugger, leave cs0/cs1 alone */ if (get_lbc_br(1) & BR_V) diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index c5047326a..8695a6269 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2008,2010 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -295,6 +295,8 @@ void lbc_sdram_init(void); #define LBCR_EPAR_SHIFT 16 #define LBCR_BMT 0x0000FF00 #define LBCR_BMT_SHIFT 8 +#define LBCR_BMTPS 0x0000000F +#define LBCR_BMTPS_SHIFT 0 /* LCRR - Clock Ratio Register */ diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index c8f542eab..5c818c903 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -43,5 +43,6 @@ #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #include "corenet_ds.h"