Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

master
Wolfgang Denk 2011-01-17 20:31:46 +01:00
commit e1ccf97c5d
149 changed files with 2043 additions and 7588 deletions

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@ -198,6 +198,14 @@ Siddarth Gore <gores@marvell.com>
guruplug ARM926EJS (Kirkwood SoC)
Paul Gortmaker <paul.gortmaker@windriver.com>
sbc8349 MPC8349
sbc8540 MPC8540
sbc8548 MPC8548
sbc8560 MPC8560
sbc8641d MPC8641D
Frank Gottschling <fgottschling@eltec.de>
MHPC MPC8xx
@ -212,11 +220,6 @@ Wolfgang Grandegger <wg@denx.de>
IPHASE4539 MPC8260
SCM MPC8260
Joe Hamman <joe.hamman@embeddedspecialties.com>
sbc8548 MPC8548
sbc8641d MPC8641D
Klaus Heydeck <heydeck@kieback-peter.de>
KUP4K MPC855
@ -256,10 +259,6 @@ Sangmoon Kim <dogoil@etinsys.com>
debris MPC8245
KVME080 MPC8245
Robert Lazarski <robertlazarski@gmail.com>
ATUM8548 MPC8548
The LEOX team <team@leox.org>
ELPT860 MPC860T

18
README
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@ -2787,6 +2787,24 @@ Low Level (hardware related) configuration options:
Disable PCI-Express on systems where it is supported but not
required.
- CONFIG_SYS_SRIO:
Chip has SRIO or not
- CONFIG_SRIO1:
Board has SRIO 1 port available
- CONFIG_SRIO2:
Board has SRIO 2 port available
- CONFIG_SYS_SRIOn_MEM_VIRT:
Virtual Address of SRIO port 'n' memory region
- CONFIG_SYS_SRIOn_MEM_PHYS:
Physical Address of SRIO port 'n' memory region
- CONFIG_SYS_SRIOn_MEM_SIZE:
Size of SRIO port 'n' memory region
- CONFIG_SPD_EEPROM
Get DDR timing information from an I2C EEPROM. Common
with pluggable memory modules such as SODIMMs

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@ -66,8 +66,6 @@ COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_FSL_CORENET) += liodn.o
COBJS-$(CONFIG_MP) += mp.o
COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
COBJS-$(CONFIG_P1022) += p1022_serdes.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-$(CONFIG_FSL_CORENET) += portals.o
@ -77,6 +75,22 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o
# SoC specific SERDES support
COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o
COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o
COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o
COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o
COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o
COBJS-$(CONFIG_P1011) += p1021_serdes.o
COBJS-$(CONFIG_P1012) += p1021_serdes.o
COBJS-$(CONFIG_P1013) += p1013_serdes.o
COBJS-$(CONFIG_P1020) += p1021_serdes.o
COBJS-$(CONFIG_P1021) += p1021_serdes.o
COBJS-$(CONFIG_P1022) += p1022_serdes.o
COBJS-$(CONFIG_P2010) += p2020_serdes.o
COBJS-$(CONFIG_P2020) += p2020_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS = $(COBJS-y)

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@ -1,5 +1,5 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -47,6 +47,28 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
puts("Work-around for Erratum CPU22 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
puts("Work-around for Erratum ESDHC111 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
puts("Work-around for Erratum ESDHC135 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
puts("Work-around for Erratum ESDHC136 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
puts("Work-around for Erratum CPC-A002 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
puts("Work-around for Erratum CPC-A003 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
puts("Work-around for Erratum ELBC-A001 enabled\n");
#endif
return 0;
}

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@ -34,6 +34,7 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
#include <post.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
@ -286,6 +287,57 @@ void mpc85xx_reginfo(void)
print_lbc_regs();
}
/* Common ddr init for non-corenet fsl 85xx platforms */
#ifndef CONFIG_FSL_CORENET
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
unsigned int x = 10;
unsigned int i;
/*
* Work around to stabilize DDR DLL
*/
out_be32(&gur->ddrdllcr, 0x81000000);
asm("sync;isync;msync");
udelay(200);
while (in_be32(&gur->ddrdllcr) != 0x81000100) {
setbits_be32(&gur->devdisr, 0x00010000);
for (i = 0; i < x; i++)
;
clrbits_be32(&gur->devdisr, 0x00010000);
x++;
}
}
#endif
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
dram_size = fsl_ddr_sdram();
#else
dram_size = fixed_sdram();
#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(dram_size);
#endif
/* Some boards also have sdram on the lbc */
lbc_sdram_init();
puts("DDR: ");
return dram_size;
}
#endif
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */

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@ -1,5 +1,5 @@
/*
* Copyright 2007-2010 Freescale Semiconductor, Inc.
* Copyright 2007-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2003 Motorola Inc.
* Modified by Xianghua Xiao, X.Xiao@motorola.com
@ -40,6 +40,8 @@
DECLARE_GLOBAL_DATA_PTR;
extern void srio_init(void);
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@ -140,6 +142,13 @@ static void enable_cpc(void)
u32 cpccfg0 = in_be32(&cpc->cpccfg0);
size += CPC_CFG0_SZ_K(cpccfg0);
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
#endif
out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
/* Read back to sync write */
in_be32(&cpc->cpccsr0);
@ -232,6 +241,12 @@ void cpu_init_f (void)
invalidate_cpc();
}
/* Implement a dummy function for those platforms w/o SERDES */
static void __fsl_serdes__init(void)
{
return ;
}
__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
/*
* Initialize L2 as cache.
@ -375,15 +390,25 @@ int cpu_init_r(void)
qe_reset();
#endif
#if defined(CONFIG_SYS_HAS_SERDES)
/* needs to be in ram since code uses global static vars */
fsl_serdes_init();
#ifdef CONFIG_SYS_SRIO
srio_init();
#endif
#if defined(CONFIG_MP)
setup_mp();
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
{
void *p;
p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
setbits_be32(p, 1 << (31 - 14));
}
#endif
#ifdef CONFIG_SYS_LBC_LCRR
/*
* Modify the CLKDIV field of LCRR register to improve the writing

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@ -1,5 +1,5 @@
/*
* Copyright 2007-2010 Freescale Semiconductor, Inc.
* Copyright 2007-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
extern void ft_qe_setup(void *blob);
extern void ft_fixup_num_cores(void *blob);
extern void ft_srio_setup(void *blob);
#ifdef CONFIG_MP
#include "mp.h"
@ -478,4 +479,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_qportals(blob);
#endif
#ifdef CONFIG_SYS_SRIO
ft_srio_setup(blob);
#endif
}

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@ -0,0 +1,95 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 8
#define SRDS2_MAX_LANES 4
static u32 serdes1_prtcl_map, serdes2_prtcl_map;
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
[0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
[0x6] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
};
static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
[0x1] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
[0x3] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
[0x5] = {NONE, NONE, SGMII_TSEC1, SGMII_TSEC3},
[0x6] = {PCIE3, NONE, NONE, NONE},
[0x7] = {PCIE3, NONE, SGMII_TSEC1, SGMII_TSEC3},
};
int is_serdes_configured(enum srds_prtcl device)
{
int ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
return (1 << device) & serdes2_prtcl_map;
}
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)
serdes2_prtcl_map &= ~(1 << SGMII_TSEC1);
if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)
serdes2_prtcl_map &= ~(1 << SGMII_TSEC3);
}

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@ -0,0 +1,65 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 8
static u32 serdes1_prtcl_map;
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
[0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
[0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
[0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
};
int is_serdes_configured(enum srds_prtcl prtcl)
{
return (1 << prtcl) & serdes1_prtcl_map;
}
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
return ;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
}

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@ -0,0 +1,65 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 8
static u32 serdes1_prtcl_map;
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
[0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
[0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
[0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
};
int is_serdes_configured(enum srds_prtcl prtcl)
{
return (1 << prtcl) & serdes1_prtcl_map;
}
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
}

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@ -0,0 +1,74 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 4
static u32 serdes1_prtcl_map;
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x0] = {PCIE1, NONE, NONE, NONE},
[0x1] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
[0x2] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
[0x3] = {SRIO1, SRIO2, NONE, NONE},
[0x4] = {PCIE1, NONE, SGMII_TSEC1, SGMII_TSEC2},
[0x5] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
[0x6] = {PCIE1, NONE, SRIO1, SRIO2},
[0x7] = {PCIE1, PCIE1, SRIO1, SRIO2},
[0x8] = {PCIE1, PCIE1, SRIO1, SRIO2},
[0x9] = {SRIO1, SRIO1, SRIO1, SRIO1},
[0xa] = {SRIO1, SRIO1, SRIO1, SRIO1},
[0xb] = {SRIO1, SRIO1, SRIO1, SRIO1},
[0xc] = {PCIE1, SRIO1, SGMII_TSEC1, SGMII_TSEC2},
[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1},
};
int is_serdes_configured(enum srds_prtcl prtcl)
{
return (1 << prtcl) & serdes1_prtcl_map;
}
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
}

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@ -0,0 +1,81 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 8
static u32 serdes1_prtcl_map;
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
[0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
[0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
[0xc] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
[0xd] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
[0xe] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
};
int is_serdes_configured(enum srds_prtcl prtcl)
{
return (1 << prtcl) & serdes1_prtcl_map;
}
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
serdes1_prtcl_map |= (1 << SGMII_TSEC1);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
serdes1_prtcl_map |= (1 << SGMII_TSEC2);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
serdes1_prtcl_map |= (1 << SGMII_TSEC3);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
serdes1_prtcl_map |= (1 << SGMII_TSEC4);
}

View File

@ -0,0 +1,64 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 4
static u32 serdes1_prtcl_map;
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x0] = {PCIE1, NONE, NONE, NONE},
[0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
[0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3},
};
int is_serdes_configured(enum srds_prtcl prtcl)
{
return (1 << prtcl) & serdes1_prtcl_map;
}
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
}

View File

@ -0,0 +1,73 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 4
static u32 serdes1_prtcl_map;
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x0] = {PCIE1, NONE, NONE, NONE},
[0x2] = {PCIE1, PCIE2, PCIE3, PCIE3},
[0x4] = {PCIE1, PCIE1, PCIE3, PCIE3},
[0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0x7] = {SRIO2, SRIO1, NONE, NONE},
[0x8] = {SRIO2, SRIO2, SRIO2, SRIO2},
[0x9] = {SRIO2, SRIO2, SRIO2, SRIO2},
[0xa] = {SRIO2, SRIO2, SRIO2, SRIO2},
[0xb] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3},
[0xc] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3},
[0xd] = {PCIE1, SRIO1, SGMII_TSEC2, SGMII_TSEC3},
[0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
[0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3},
};
int is_serdes_configured(enum srds_prtcl prtcl)
{
return (1 << prtcl) & serdes1_prtcl_map;
}
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
int lane;
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
}

View File

@ -1,5 +1,5 @@
/*
* Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
* Copyright (C) 2003 Motorola,Inc.
*
* See file CREDITS for list of people who contributed to this
@ -753,7 +753,7 @@ dcache_disable:
lis r4,0
ori r4,r4,L1CSR0_DCE
andc r3,r3,r4
mtspr L1CSR0,r0
mtspr L1CSR0,r3
isync
blr

View File

@ -250,10 +250,14 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
{
int i;
unsigned int tlb_size;
unsigned int wimge = 0;
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
u64 size, memsize = (u64)memsize_in_meg << 20;
#ifdef CONFIG_SYS_PPC_DDR_WIMGE
wimge = CONFIG_SYS_PPC_DDR_WIMGE;
#endif
size = min(memsize, CONFIG_MAX_MEM_MAPPED);
/* Convert (4^max) kB to (2^max) bytes */
@ -277,7 +281,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
tlb_size = (camsize - 10) / 2;
set_tlb(1, ram_tlb_address, p_addr,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
MAS3_SX|MAS3_SW|MAS3_SR, wimge,
0, ram_tlb_index, tlb_size, 1);
size -= 1ULL << camsize;

View File

@ -42,6 +42,8 @@ COBJS-$(CONFIG_MPC8641) += ddr-8641.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-y += interrupts.o
COBJS-$(CONFIG_MP) += mp.o
COBJS-$(CONFIG_MPC8610) += mpc8610_serdes.o
COBJS-$(CONFIG_MPC8641) += mpc8641_serdes.o
COBJS-y += speed.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)

View File

@ -1,5 +1,5 @@
/*
* Copyright 2004,2009 Freescale Semiconductor, Inc.
* Copyright 2004,2009-2011 Freescale Semiconductor, Inc.
* Jeff Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*
@ -31,8 +31,10 @@
#include <mpc86xx.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/mp.h>
extern void srio_init(void);
void setup_bats(void);
DECLARE_GLOBAL_DATA_PTR;
@ -76,6 +78,13 @@ void cpu_init_f(void)
*/
int cpu_init_r(void)
{
/* needs to be in ram since code uses global static vars */
fsl_serdes_init();
#ifdef CONFIG_SYS_SRIO
srio_init();
#endif
#if defined(CONFIG_MP)
setup_mp();
#endif

View File

@ -1,5 +1,5 @@
/*
* Copyright 2008,2010 Freescale Semiconductor, Inc.
* Copyright 2008, 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -14,6 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
extern void ft_fixup_num_cores(void *blob);
extern void ft_srio_setup(void *blob);
void ft_cpu_setup(void *blob, bd_t *bd)
{
@ -58,4 +59,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_fixup_num_cores(blob);
#endif
#ifdef CONFIG_SYS_SRIO
ft_srio_setup(blob);
#endif
}

View File

@ -0,0 +1,85 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 4
#define SRDS2_MAX_LANES 4
static u32 serdes1_prtcl_map, serdes2_prtcl_map;
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x1] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0x4] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0x7] = {NONE, NONE, NONE, NONE},
};
static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
[0x0] = {PCIE2, PCIE2, PCIE2, PCIE2},
[0x4] = {PCIE2, PCIE2, PCIE2, PCIE2},
[0x7] = {NONE, NONE, NONE, NONE},
};
int is_serdes_configured(enum srds_prtcl device)
{
int ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
return (1 << device) & serdes2_prtcl_map;
}
void fsl_serdes_init(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
ccsr_gur_t *gur = &immap->im_gur;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC8610_PORDEVSR_IO_SEL) >>
MPC8610_PORDEVSR_IO_SEL_SHIFT;
int lane;
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
}

View File

@ -0,0 +1,94 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 4
#define SRDS2_MAX_LANES 4
static u32 serdes1_prtcl_map, serdes2_prtcl_map;
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1},
};
static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
[0x3] = {PCIE2, PCIE2, PCIE2, PCIE2},
[0x5] = {SRIO1, SRIO1, SRIO1, SRIO1},
[0x6] = {SRIO1, SRIO1, SRIO1, SRIO1},
[0x7] = {SRIO1, SRIO1, SRIO1, SRIO1},
[0x9] = {SRIO1, SRIO1, SRIO1, SRIO1},
[0xa] = {SRIO1, SRIO1, SRIO1, SRIO1},
[0xb] = {SRIO1, SRIO1, SRIO1, SRIO1},
[0xe] = {PCIE2, PCIE2, PCIE2, PCIE2},
[0xf] = {PCIE2, PCIE2, PCIE2, PCIE2},
};
int is_serdes_configured(enum srds_prtcl device)
{
int ret = (1 << device) & serdes1_prtcl_map;
if (ret)
return ret;
return (1 << device) & serdes2_prtcl_map;
}
void fsl_serdes_init(void)
{
immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
ccsr_gur_t *gur = &immap->im_gur;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC8641_PORDEVSR_IO_SEL) >>
MPC8641_PORDEVSR_IO_SEL_SHIFT;
int lane;
debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
serdes1_prtcl_map |= (1 << lane_prtcl);
}
if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
return;
}
for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
serdes2_prtcl_map |= (1 << lane_prtcl);
}
}

View File

@ -12,11 +12,11 @@ LIB = $(obj)lib8xxx.o
ifneq ($(CPU),mpc83xx)
COBJS-y += cpu.o
COBJS-$(CONFIG_PCI) += pci_cfg.o
endif
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
COBJS-$(CONFIG_SYS_SRIO) += srio.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

View File

@ -469,8 +469,9 @@ phys_size_t fsl_ddr_sdram(void)
/* Check for 4G or more. Bad. */
if (total_memory >= (1ull << 32)) {
printf("Detected %lld MB of memory\n", total_memory >> 20);
printf("This U-Boot only supports < 4G of DDR\n");
printf("You could rebuild it with CONFIG_PHYS_64BIT\n");
printf(" This U-Boot only supports < 4G of DDR\n");
printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
printf(" "); /* re-align to match init_func_ram print */
total_memory = CONFIG_MAX_MEM_MAPPED;
}
#endif

View File

@ -1,5 +1,5 @@
/*
* Copyright 2008, 2010 Freescale Semiconductor, Inc.
* Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
@ -387,3 +387,23 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
"Memory controller interleaving disabled.\n");
}
}
int fsl_use_spd(void)
{
int use_spd = 0;
#ifdef CONFIG_DDR_SPD
/* if hwconfig is not enabled, or "sdram" is not defined, use spd */
if (hwconfig_sub("fsl_ddr", "sdram")) {
if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd"))
use_spd = 1;
else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed"))
use_spd = 0;
else
use_spd = 1;
} else
use_spd = 1;
#endif
return use_spd;
}

View File

@ -1,5 +1,5 @@
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@ -28,6 +28,7 @@
#include <fdt_support.h>
#include <asm/mp.h>
#include <asm/fsl_enet.h>
#include <asm/fsl_serdes.h>
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
@ -239,3 +240,23 @@ int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if phyc)
return fdt_setprop_string(blob, offset, "phy-connection-type",
fsl_phy_enet_if_str[phyc]);
}
#ifdef CONFIG_SYS_SRIO
void ft_srio_setup(void *blob)
{
#ifdef CONFIG_SRIO1
if (!is_serdes_configured(SRIO1)) {
fdt_del_node_and_alias(blob, "rio0");
}
#else
fdt_del_node_and_alias(blob, "rio0");
#endif
#ifdef CONFIG_SRIO2
if (!is_serdes_configured(SRIO2)) {
fdt_del_node_and_alias(blob, "rio1");
}
#else
fdt_del_node_and_alias(blob, "rio1");
#endif
}
#endif

View File

@ -1,5 +1,5 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -9,6 +9,16 @@
#include <common.h>
#include <asm/fsl_lbc.h>
#ifdef CONFIG_MPC85xx
/* Boards should provide their own version of this if they use lbc sdram */
void __lbc_sdram_init(void)
{
/* Do nothing */
}
void lbc_sdram_init(void) __attribute__((weak, alias("__lbc_sdram_init")));
#endif
void print_lbc_regs(void)
{
int i;
@ -24,6 +34,11 @@ void init_early_memctl_regs(void)
{
uint init_br1 = 1;
#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
/* Set the local bus monitor timeout value to the maximum */
clrsetbits_be32(&(LBC_BASE_ADDR)->lbcr, LBCR_BMT|LBCR_BMTPS, 0xf);
#endif
#ifdef CONFIG_MPC85xx
/* if cs1 is already set via debugger, leave cs0/cs1 alone */
if (get_lbc_br(1) & BR_V)

View File

@ -1,204 +0,0 @@
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <pci.h>
struct pci_info {
u32 cfg;
};
/* The cfg field is a bit mask in which each bit represents the value of
* cfg_IO_ports[] signal and the bit is set if the interface would be
* enabled based on the value of cfg_IO_ports[] signal
*
* On MPC86xx/PQ3 based systems:
* we extract cfg_IO_ports from GUTS register PORDEVSR
*
* cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems
* without PCIe)
*/
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560)
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCI] = {
.cfg = 0,
},
};
#elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
static struct pci_info pci_config_info[] =
{
[LAW_TRGT_IF_PCI] = {
.cfg = 0,
},
};
#elif defined(CONFIG_MPC8536)
static struct pci_info pci_config_info[] =