This is the first commit for the u-boot zylonite port. The following has be
done so far: * created zylonite board dir (based on lubbock) * extended some - but not all pxa sources and headers for Intel Monahans support (CONFIG_CPU_MONAHANS) * created Makefile zylonite target + MAKEALL entry * added some debug nonsense, remove later, grep for mk@tbd Status: compiles (eldk-4.0), and can be started with BDI, but runs forever and doesn't halt at breakpoints. Hmmm...
This commit is contained in:
Markus Klotzbcher
Markus Klotzbcher
parent
57cac1fa54
commit
e0269579a5
2
MAKEALL
2
MAKEALL
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@ -204,7 +204,7 @@ LIST_ARM11=" \
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LIST_pxa=" \
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adsvix cerf250 cradle csb226 \
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innokom lubbock pxa255_idp wepep250 \
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xaeniax xm250 xsengine \
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xaeniax xm250 xsengine zylonite \
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"
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LIST_ixp="ixdp425"
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5
Makefile
5
Makefile
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@ -1633,6 +1633,9 @@ xm250_config : unconfig
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xsengine_config : unconfig
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@./mkconfig $(@:_config=) arm pxa xsengine
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zylonite_config :
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@./mkconfig $(@:_config=) arm pxa zylonite
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#########################################################################
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## ARM1136 Systems
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#########################################################################
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@ -1838,7 +1841,7 @@ clobber: clean
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-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
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-print0 \
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| xargs -0 rm -f
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rm -f $(OBJS) *.bak tags TAGS
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rm -f $(OBJS) *.bak tags
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rm -fr *.*~
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rm -f u-boot u-boot.map u-boot.hex $(ALL)
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rm -f tools/crc32.c tools/environment.c tools/env/crc32.c
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@ -131,6 +131,10 @@ else
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CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
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endif
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ifdef WILD_WILD_WEST
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CFLAGS := $(CFLAGS) -Werror
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endif
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# avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9)
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# this option have to be placed behind -Wall -- that's why it is here
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ifeq ($(ARCH),nios)
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@ -143,6 +143,7 @@ int dcache_status (void)
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return 0; /* always off */
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}
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#ifndef CONFIG_CPU_MONAHANS
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void set_GPIO_mode(int gpio_mode)
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{
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int gpio = gpio_mode & GPIO_MD_MASK_NR;
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@ -160,3 +161,5 @@ void set_GPIO_mode(int gpio_mode)
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gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
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GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
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}
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#endif /* CONFIG_CPU_MONAHANS */
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@ -54,7 +54,11 @@ void serial_setbrg (void)
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hang ();
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#ifdef CONFIG_FFUART
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#ifdef CONFIG_CPU_MONAHANS
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CKENA |= CKENA_22_FFUART;
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#else
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CKEN |= CKEN6_FFUART;
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#endif /* CONFIG_CPU_MONAHANS */
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FFIER = 0; /* Disable for now */
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FFFCR = 0; /* No fifos enabled */
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@ -68,7 +72,11 @@ void serial_setbrg (void)
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FFIER = IER_UUE; /* Enable FFUART */
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#elif defined(CONFIG_BTUART)
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#ifdef CONFIG_CPU_MONAHANS
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CKENA |= CKENA_21_BTUART;
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#else
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CKEN |= CKEN7_BTUART;
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#endif /* CONFIG_CPU_MONAHANS */
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BTIER = 0;
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BTFCR = 0;
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@ -82,7 +90,11 @@ void serial_setbrg (void)
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BTIER = IER_UUE; /* Enable BFUART */
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#elif defined(CONFIG_STUART)
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#ifdef CONFIG_CPU_MONAHANS
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CKENA |= CKENA_23_STUART;
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#else
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CKEN |= CKEN5_STUART;
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#endif /* CONFIG_CPU_MONAHANS */
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STIER = 0;
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STFCR = 0;
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@ -190,10 +190,10 @@ cpuspeed: .word CFG_CPUSPEED
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#endif
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/* RS: ??? */
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.macro CPWAIT
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mrc p15,0,r0,c2,c0,0
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mov r0,r0
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/* takes care the CP15 update has taken place */
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.macro CPWAIT reg
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mrc p15,0,\reg,c2,c0,0
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mov \reg,\reg
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sub pc,pc,#4
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.endm
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@ -201,13 +201,28 @@ cpuspeed: .word CFG_CPUSPEED
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cpu_init_crit:
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/* mask all IRQs */
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#ifndef CONFIG_CPU_MONAHANS
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ldr r0, IC_BASE
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mov r1, #0x00
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str r1, [r0, #ICMR]
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#else
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/* Step 1 - Enable CP6 permission */
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mrc p15, 0, r1, c15, c1, 0 @ read CPAR
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orr r1, r1, #0x40
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mcr p15, 0, r1, c15, c1, 0
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CPWAIT r1
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#if defined(CFG_CPUSPEED)
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/* Step 2 - Mask ICMR & ICMR2 */
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mov r1, #0
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mcr p6, 0, r1, c1, c0, 0 @ ICMR
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mcr p6, 0, r1, c7, c0, 0 @ ICMR2
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#endif
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/* set clock speed */
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#ifndef CONFIG_CPU_MONAHANS
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#ifdef CFG_CPUSPEED
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/* set clock speed tbd@mk: required for monahans? */
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ldr r0, CC_BASE
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ldr r1, cpuspeed
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str r1, [r0, #CCCR]
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@ -215,7 +230,10 @@ cpu_init_crit:
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mcr p14, 0, r0, c6, c0, 0
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setspeed_done:
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#endif
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#endif /* CFG_CPUSPEED */
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#endif /* CONFIG_CPU_MONAHANS */
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/*
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* before relocating, we have to setup RAM timing
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@ -227,19 +245,21 @@ setspeed_done:
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mov lr, ip
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/* Memory interfaces are working. Disable MMU and enable I-cache. */
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/* mk: hmm, this is not in the monahans docs, leave it now but
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* check here if it doesn't work :-) */
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ldr r0, =0x2001 /* enable access to all coproc. */
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mcr p15, 0, r0, c15, c1, 0
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CPWAIT
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CPWAIT r0
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mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
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CPWAIT
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CPWAIT r0
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mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
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CPWAIT
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CPWAIT r0
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mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
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CPWAIT
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CPWAIT r0
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/* Enable the Icache */
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/*
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@ -8,11 +8,6 @@
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Note: This file was taken from linux-2.4.19-rmk4-pxa1
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*
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* - 2003/01/20 implementation specifics activated
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* Robert Schwebel <r.schwebel@pengutronix.de>
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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@ -21,16 +16,6 @@
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#include <linux/config.h>
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#include <asm/mach-types.h>
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/*
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* These are statically mapped PCMCIA IO space for designs using it as a
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* generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
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* The actual PCMCIA code is mapping required IO region at run time.
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*/
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#define PCMCIA_IO_0_BASE 0xf6000000
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#define PCMCIA_IO_1_BASE 0xf7000000
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/*
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* We requires absolute addresses.
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*/
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@ -44,22 +29,63 @@
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#define UNCACHED_ADDR UNCACHED_PHYS_0
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/*
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* Intel PXA internal I/O mappings:
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* Intel PXA2xx internal register mapping:
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*
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* 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
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* 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
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* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
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* 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
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* 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
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* 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
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* 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
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* 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
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* 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
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* 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
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*
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* Note that not all PXA2xx chips implement all those addresses, and the
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* kernel only maps the minimum needed range of this mapping.
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*/
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#ifndef CONFIG_CPU_MONAHANS
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#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
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#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
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#else
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/* There are too many IO area needed to map, so I divide them into 3 areas
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* 0x40000000 - 0x41ffffff <--> 0xf6000000 - 0xf7ffffff Devs
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*/
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#define io_p2v(x) ((((x) & 0xfc000000)>>4) + 0xf2000000 + ((x)&0x01ffffff))
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#define io_v2p(x) (((((x) - 0xf2000000)&0xfc000000)<<4) + ((x)&0x01ffffff))
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/*
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* 0x42000000 - 0x421fffff <--> 0xf8000000 - 0xf81fffff MMC2 & USIM2
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* 0x43000000 - 0x430fffff <--> 0xf8200000 - 0xf82fffff Caddo
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* 0x43100000 - 0x431fffff <--> 0xf8300000 - 0xf83fffff NAND
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* 0x44000000 - 0x440fffff <--> 0xf8400000 - 0xf84fffff LCD
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* 0x46000000 - 0x460fffff <--> 0xf8800000 - 0xf88fffff Mini LCD
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* 0x48100000 - 0x481fffff <--> 0xf8d00000 - 0xf8dfffff Dynamic Mem Ctl
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* 0x4a000000 - 0x4a0fffff <--> 0xf9000000 - 0xf90fffff Static Mem Ctl
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* 0x4c000000 - 0x4c0fffff <--> 0xf9400000 - 0xf94fffff USB Host
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*/
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/* FIXME: Only this does work for u-boot... find out why... [RS] */
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#define UBOOT_REG_FIX 1
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#define io_p2v_2(x) (((((x) - 0x42000000) & 0xff000000) >> 3) + 0xf8000000\
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+ ((x) & 0x001fffff))
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#define io_v2p_2(x) (((((x) & 0xffe00000) - 0xf8000000) << 3) + 0x42000000\
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+ (x & 0x001fffff))
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/*
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* 0x50000000 - 0x500fffff <--> 0xfa000000 - 0xfa0fffff Camera Interface
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* 0x54000000 - 0x540fffff <--> 0xfa400000 - 0xfa4fffff 2D Graphics Ctrl
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* 0x54100000 - 0x541fffff <--> 0xfa500000 - 0xfa5fffff USB Device 2.0 Ctrl
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* 0x58000000 - 0x580fffff <--> 0xfa800000 - 0xfa8fffff Internal SRAM Ctrl
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*/
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#define io_p2v_3(x) ((((x) & 0xfc000000) >> 4) + 0xf5000000 + \
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((x) & 0x001fffff))
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#define io_v2p_3(x) (((((x) - 0xf5000000) & 0x0fc00000) << 4) + \
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((x) & 0x001fffff))
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#endif /* CONFIG_CPU_MONAHANS */
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#ifndef UBOOT_REG_FIX
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#ifndef __ASSEMBLY__
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#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
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#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
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#if 0
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# define __REG(x) (*((volatile u32 *)io_p2v(x)))
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#else
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/*
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* This __REG() version gives the same results as the one above, except
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* that we are fooling gcc somehow so it generates far better and smaller
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@ -70,62 +96,56 @@
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typedef struct { volatile u32 offset[4096]; } __regbase;
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# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
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# define __REG(x) __REGP(io_p2v(x))
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#endif
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/* Let's kick gcc's ass again... */
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# define __REG2(x,y) \
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( __builtin_constant_p(y) ? (__REG((x) + (y))) \
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: (*(volatile u32 *)((u32)&__REG(x) + (y))) )
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/* __REG_2 is for NAND, LCD etc.
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* __REG_3 is for Camera Interface, 2D Graphics, U2D etc.*/
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#ifdef CONFIG_CPU_MONAHANS
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#define __REG_2(x) __REGP(io_p2v_2(x))
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#define __REG_3(x) __REGP(io_p2v_3(x))
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#endif /* CONFIG_CPU_MONAHANS */
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#endif /* if 0 */
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/* With indexed regs we don't want to feed the index through io_p2v()
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especially if it is a variable, otherwise horrible code will result. */
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# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
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# define __PREG(x) (io_v2p((u32)&(x)))
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#else
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#else /* ifndef __ASSEMBLY__ */
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# define __REG(x) io_p2v(x)
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# define __PREG(x) io_v2p(x)
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# undef io_p2v
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# undef __REG
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# ifndef __ASSEMBLY__
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# define io_p2v(PhAdd) (PhAdd)
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# define __REG(x) (*((volatile u32 *)io_p2v(x)))
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# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
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# else
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# define __REG(x) (x)
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# endif
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#endif /* UBOOT_REG_FIX */
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#ifdef CONFIG_CPU_MONAHANS
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# define __REG_2(x) io_p2v(x)
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# define __REG_3(x) io_p2v(x)
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#endif /* CONFIG_CPU_MONAHANS */
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#include "pxa-regs.h"
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#endif /* ifndef __ASSEMBLY__ */
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#ifndef __ASSEMBLY__
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/*
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* GPIO edge detection for IRQs:
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* IRQs are generated on Falling-Edge, Rising-Edge, or both.
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* This must be called *before* the corresponding IRQ is registered.
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* Use this instead of directly setting GRER/GFER.
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*/
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#define GPIO_FALLING_EDGE 1
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#define GPIO_RISING_EDGE 2
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#define GPIO_BOTH_EDGES 3
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extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask );
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#ifdef CONFIG_MACH_ZYLONITE
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#include "zylonite.h"
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#endif
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/*
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* Handy routine to set GPIO alternate functions
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*/
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extern void set_GPIO_mode( int gpio_mode );
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extern void pxa_gpio_mode( int gpio_mode );
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/*
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* return current lclk frequency in units of 10kHz
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* Routine to enable or disable CKEN
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*/
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extern unsigned int get_lclk_frequency_10khz(void);
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#endif
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extern void pxa_set_cken(int clock, int enable);
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/*
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* Implementation specifics
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* return current memory and LCD clock frequency in units of 10kHz
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*/
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extern unsigned int get_memclk_frequency_10khz(void);
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extern unsigned int get_lcdclk_frequency_10khz(void);
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#endif /* __ASSEMBLY__ */
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#ifdef CONFIG_ARCH_LUBBOCK
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#include "lubbock.h"
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@ -139,6 +159,15 @@ extern unsigned int get_lclk_frequency_10khz(void);
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#include "cerf.h"
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#endif
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#if CONFIG_CPU_MONAHANS_L2CACHE
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#define __cpuc_flush_l2cache_all xscale_flush_l2cache_all
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extern void __cpuc_flush_l2cache_all(void);
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#define flush_l2cache_all __cpuc_flush_l2cache_all
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#else
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#define __cpuc_flush_l2cache_all() do {} while (0)
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#define flush_l2cache_all() do {} while (0)
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#endif
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#ifdef CONFIG_ARCH_CSB226
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#include "csb226.h"
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#endif
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@ -151,4 +180,10 @@ extern unsigned int get_lclk_frequency_10khz(void);
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#include "pleb.h"
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#endif
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#endif /* _ASM_ARCH_HARDWARE_H */
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#ifdef CONFIG_MACH_MAINSTONE
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#include "mainstone.h"
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#endif
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#include "pxa-regs.h"
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#endif /* _ASM_ARCH_HARDWARE_H */
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|
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File diff suppressed because it is too large
Load Diff
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@ -38,6 +38,8 @@
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* FIQ Stack: 00ebef7c
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*/
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#define DEBUG 1
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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