Cleanup build problems (on Fedora Core x86_64 build host)
This commit is contained in:
Wolfgang Denk
parent
d3b86c496d
commit
dc17fb6dc2
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@ -2,6 +2,8 @@
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Changes for U-Boot 1.1.3:
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======================================================================
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* Cleanup build problems on 64 bit build hosts
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* Update MAINTAINERS file
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* Patch by Stefan Roese, 01 Aug 2005:
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152
MAINTAINERS
152
MAINTAINERS
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@ -129,6 +129,34 @@ Thomas Frieden <ThomasF@hyperion-entertainment.com>
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AmigaOneG3SE MPC7xx
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Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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ADCIOP IOP480 (PPC401)
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APC405 PPC405GP
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AR405 PPC405GP
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ASH405 PPC405EP
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CANBT PPC405CR
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CPCI405 PPC405GP
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CPCI4052 PPC405GP
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CPCI405AB PPC405GP
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CPCI405DT PPC405GP
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CPCI440 PPC440GP
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CPCIISER4 PPC405GP
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DASA_SIM IOP480 (PPC401)
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DP405 PPC405EP
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DU405 PPC405GP
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G2000 PPC405EP
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HH405 PPC405EP
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HUB405 PPC405EP
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OCRTC PPC405GP
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ORSG PPC405GP
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PCI405 PPC405GP
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PLU405 PPC405EP
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PMC405 PPC405GP
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VOH405 PPC405EP
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VOM405 PPC405EP
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WUH405 PPC405EP
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Frank Gottschling <fgottschling@eltec.de>
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MHPC MPC8xx
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@ -168,10 +196,6 @@ Sangmoon Kim <dogoil@etinsys.com>
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debris MPC8245
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Nye Liu <nyet@zumanetworks.com>
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ZUMA MPC7xx_74xx
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Thomas Lange <thomas@corelatus.se>
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GTH MPC860
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@ -180,6 +204,21 @@ The LEOX team <team@leox.org>
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ELPT860 MPC860T
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Nye Liu <nyet@zumanetworks.com>
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ZUMA MPC7xx_74xx
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Jon Loeliger <jdl@freescale.com>
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MPC8540ADS MPC8540
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MPC8560ADS MPC8560
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MPC8541CDS MPC8541
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MPC8555CDS MPC8555
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Dan Malek <dan@embeddededge.com>
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STxGP3 MPC85xx
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Eran Man <eran@nbase.co.il>
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EVB64260_750CX MPC750CX
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@ -194,6 +233,7 @@ Reinhard Meyer <r.meyer@emk-elektronik.de>
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TOP5200 MPC5200
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Tolunay Orkun <torkun@nextio.com>
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csb272 PPC405GP
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csb472 PPC405GP
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@ -202,17 +242,6 @@ Keith Outwater <Keith_Outwater@mvis.com>
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GEN860T MPC860T
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GEN860T_SC MPC860T
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Stefan Roese <sr@denx.de>
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bamboo PPC440EP
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bunbinga PPC405EP
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ebony PPC440GP
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ocotea PPC440GX
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sycamore PPC405GPr
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walnut PPC405GP
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yellowstone PPC440GR
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yosemite PPC440EP
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Frank Panno <fpanno@delphintech.com>
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ep8260 MPC8260
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@ -234,33 +263,20 @@ Daniel Poirot <dan.poirot@windriver.com>
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sbc8240 MPC8240
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sbc405 PPC405GP
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Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Stefan Roese <sr@denx.de>
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ADCIOP IOP480 (PPC401)
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APC405 PPC405GP
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AR405 PPC405GP
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ASH405 PPC405EP
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CANBT PPC405CR
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CPCI405 PPC405GP
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CPCI4052 PPC405GP
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CPCI405AB PPC405GP
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CPCI405DT PPC405GP
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CPCI440 PPC440GP
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CPCIISER4 PPC405GP
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DASA_SIM IOP480 (PPC401)
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DP405 PPC405EP
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DU405 PPC405GP
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G2000 PPC405EP
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HH405 PPC405EP
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HUB405 PPC405EP
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OCRTC PPC405GP
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ORSG PPC405GP
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PCI405 PPC405GP
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PLU405 PPC405EP
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PMC405 PPC405GP
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VOH405 PPC405EP
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VOM405 PPC405EP
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WUH405 PPC405EP
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bamboo PPC440EP
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bunbinga PPC405EP
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ebony PPC440GP
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ocotea PPC440GX
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sycamore PPC405GPr
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walnut PPC405GP
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yellowstone PPC440GR
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yosemite PPC440EP
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Yusdi Santoso <yusdi_santoso@adaptec.com>
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HIDDEN_DRAGON MPC8241/MPC8245
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Travis Sawyer (travis.sawyer@sandburst.com>
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@ -297,21 +313,6 @@ John Zhan <zhanz@sinovee.com>
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svm_sc8xx MPC8xx
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Jon Loeliger <jdl@freescale.com>
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MPC8540ADS MPC8540
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MPC8560ADS MPC8560
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MPC8541CDS MPC8541
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MPC8555CDS MPC8555
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Dan Malek <dan@embeddededge.com>
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STxGP3 MPC85xx
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Yusdi Santoso <yusdi_santoso@adaptec.com>
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HIDDEN_DRAGON MPC8241/MPC8245
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-------------------------------------------------------------------------
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Unknown / orphaned boards:
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@ -346,6 +347,10 @@ Unknown / orphaned boards:
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# Board CPU #
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#########################################################################
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Rishi Bhattacharya <rishi@ti.com>
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omap5912osk ARM926EJS
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George G. Davis <gdavis@mvista.com>
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assabet SA1100
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@ -364,6 +369,11 @@ Marius Gr
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impa7 ARM720T (EP7211)
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ep7312 ARM720T (EP7312)
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Kshitij Gupta <kshitij@ti.com>
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omap1510inn ARM925T
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omap1610inn ARM926EJS
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Kyle Harris <kharris@nexus-tech.net>
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lubbock xscale
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@ -375,29 +385,13 @@ Gary Jennejohn <gj@denx.de>
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smdk2400 ARM920T
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trab ARM920T
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Prakash Kumar <prakash@embedx.com>
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cerf250 xscale
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Kshitij Gupta <kshitij@ti.com>
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omap1510inn ARM925T
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omap1610inn ARM926EJS
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Dave Peverley <dpeverley@mpc-data.co.uk>
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omap730p2 ARM926EJS
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Nishant Kamat <nskamat@ti.com>
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omap1610h2 ARM926EJS
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Rishi Bhattacharya <rishi@ti.com>
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Prakash Kumar <prakash@embedx.com>
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omap5912osk ARM926EJS
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Richard Woodruff <r-woodruff2@ti.com>
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omap2420h4 ARM1136EJS
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cerf250 xscale
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David Müller <d.mueller@elsoft.ch>
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@ -408,6 +402,10 @@ Rolf Offermanns <rof@sysgo.de>
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shannon SA1100
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Dave Peverley <dpeverley@mpc-data.co.uk>
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omap730p2 ARM926EJS
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Robert Schwebel <r.schwebel@pengutronix.de>
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csb226 xscale
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@ -415,7 +413,7 @@ Robert Schwebel <r.schwebel@pengutronix.de>
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Andrea Scian <andrea.scian@dave-tech.it>
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B2 ARM7TDMI (S3C44B0X)
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B2 ARM7TDMI (S3C44B0X)
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Greg Ungerer <greg.ungerer@opengear.com>
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@ -423,6 +421,10 @@ Greg Ungerer <greg.ungerer@opengear.com>
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cm4116 ks8695p
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cm4148 ks8695p
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Richard Woodruff <r-woodruff2@ti.com>
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omap2420h4 ARM1136EJS
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Alex Züpke <azu@sysgo.de>
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lart SA1100
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7
Makefile
7
Makefile
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@ -881,15 +881,14 @@ yellowstone_config: unconfig
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#########################################################################
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## MPC8220 Systems
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#########################################################################
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Alaska8220_config: unconfig
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Alaska8220_config \
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Yukon8220_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8220 alaska
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sorcery_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8220 sorcery
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Yukon8220_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8220 yukon
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#########################################################################
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## MPC824x Systems
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#########################################################################
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@ -329,7 +329,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
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volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
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volatile FLASH_WORD_SIZE *addr2;
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int flag, prot, sect, l_sect;
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int i;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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@ -517,7 +516,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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*/
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static int write_word(flash_info_t * info, ulong dest, ulong data)
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{
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volatile vu_long *addr2 = (vu_long *) (info->start[0]);
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vu_long *addr2 = (vu_long *) (info->start[0]);
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volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
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volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
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ulong start;
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@ -315,10 +315,6 @@ int pci_pre_init(struct pci_controller *hose)
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller *hose)
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{
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u16 cmdstat;
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DECLARE_GLOBAL_DATA_PTR;
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/*--------------------------------------------------------------------------+
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* Set up Direct MMIO registers
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*--------------------------------------------------------------------------*/
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@ -21,7 +21,12 @@
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* MA 02111-1307 USA
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*/
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__ /* Dirty trick to get only #defines */
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#endif
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#define __ASM_STUB_PROCESSOR_H__ /* don't include asm/processor. */
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#include <config.h>
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#undef __ASSEMBLY__
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#include <environment.h>
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/*
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@ -0,0 +1,317 @@
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/*
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* (C) Copyright 2004
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* TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC8220 1
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#define CONFIG_YUKON8220 1 /* ... on Yukon board */
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/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
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determine the CPU speed. */
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#define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */
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#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Serial console configuration
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*/
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/* Define this for PSC console
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#define CONFIG_PSC_CONSOLE 1
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*/
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#define CONFIG_EXTUART_CONSOLE 1
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#ifdef CONFIG_EXTUART_CONSOLE
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# define CONFIG_CONS_INDEX 1
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# define CFG_NS16550_SERIAL
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# define CFG_NS16550
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# define CFG_NS16550_REG_SIZE 1
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# define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008)
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# define CFG_NS16550_CLK 18432000
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#endif
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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/*
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* Supported commands
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*/
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_BOOTD | \
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CFG_CMD_CACHE | \
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CFG_CMD_DHCP | \
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CFG_CMD_DIAG | \
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CFG_CMD_EEPROM | \
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CFG_CMD_ELF | \
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CFG_CMD_I2C | \
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CFG_CMD_NET | \
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CFG_CMD_NFS | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SDRAM | \
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CFG_CMD_SNTP )
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#define CONFIG_NET_MULTI
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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|
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/*
|
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* Autobooting
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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||||
#define CONFIG_BOOTARGS "root=/dev/ram rw"
|
||||
#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
|
||||
#define CONFIG_HAS_ETH1
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||||
#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
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#define CONFIG_IPADDR 192.162.1.2
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||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_SERVERIP 192.162.1.1
|
||||
#define CONFIG_GATEWAYIP 192.162.1.1
|
||||
#define CONFIG_HOSTNAME yukon
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE
|
||||
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CFG_I2C_MODULE 1
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||||
|
||||
#define CFG_I2C_SPEED 100000 /* 100 kHz */
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#define CFG_I2C_SLAVE 0x7F
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||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
|
||||
/*
|
||||
#define CFG_ENV_IS_IN_EEPROM 1
|
||||
#define CFG_ENV_OFFSET 0
|
||||
#define CFG_ENV_SIZE 256
|
||||
*/
|
||||
|
||||
/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
|
||||
else undefined it will boot from Intel Strata flash */
|
||||
#define CFG_AMD_BOOT 1
|
||||
|
||||
/*
|
||||
* Flexbus Chipselect configuration
|
||||
*/
|
||||
#if defined (CFG_AMD_BOOT)
|
||||
#define CFG_CS0_BASE 0xfff0
|
||||
#define CFG_CS0_MASK 0x00080000 /* 512 KB */
|
||||
#define CFG_CS0_CTRL 0x003f0d40
|
||||
|
||||
#define CFG_CS1_BASE 0xfe00
|
||||
#define CFG_CS1_MASK 0x01000000 /* 16 MB */
|
||||
#define CFG_CS1_CTRL 0x003f1540
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||||
#else
|
||||
#define CFG_CS0_BASE 0xff00
|
||||
#define CFG_CS0_MASK 0x01000000 /* 16 MB */
|
||||
#define CFG_CS0_CTRL 0x003f1540
|
||||
|
||||
#define CFG_CS1_BASE 0xfe08
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||||
#define CFG_CS1_MASK 0x00080000 /* 512 KB */
|
||||
#define CFG_CS1_CTRL 0x003f0d40
|
||||
#endif
|
||||
|
||||
#define CFG_CS2_BASE 0xf100
|
||||
#define CFG_CS2_MASK 0x00040000
|
||||
#define CFG_CS2_CTRL 0x003f1140
|
||||
|
||||
#define CFG_CS3_BASE 0xf200
|
||||
#define CFG_CS3_MASK 0x00040000
|
||||
#define CFG_CS3_CTRL 0x003f1100
|
||||
|
||||
|
||||
#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
|
||||
#define CFG_FLASH1_BASE (CFG_CS1_BASE << 16)
|
||||
|
||||
#if defined (CFG_AMD_BOOT)
|
||||
#define CFG_AMD_BASE CFG_FLASH0_BASE
|
||||
#define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000
|
||||
#define CFG_FLASH_BASE CFG_AMD_BASE
|
||||
#else
|
||||
#define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000
|
||||
#define CFG_AMD_BASE CFG_FLASH1_BASE
|
||||
#define CFG_FLASH_BASE CFG_INTEL_BASE
|
||||
#endif
|
||||
|
||||
#define CFG_CPLD_BASE (CFG_CS2_BASE << 16)
|
||||
#define CFG_FPGA_BASE (CFG_CS3_BASE << 16)
|
||||
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||
#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
|
||||
#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
|
||||
#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
|
||||
|
||||
#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
|
||||
#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
|
||||
|
||||
#define CFG_FLASH_CHECKSUM
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#if defined (CFG_AMD_BOOT)
|
||||
#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE
|
||||
#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
|
||||
#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
|
||||
#define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
|
||||
#define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
|
||||
#else
|
||||
#define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE
|
||||
#define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
|
||||
#define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
|
||||
#define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE
|
||||
#define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
|
||||
#endif
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
|
||||
#if defined CFG_ENV_IS_IN_FLASH
|
||||
#undef CFG_ENV_IS_IN_NVRAM
|
||||
#undef CFG_ENV_IS_IN_EEPROM
|
||||
#elif defined CFG_ENV_IS_IN_NVRAM
|
||||
#undef CFG_ENV_IS_IN_FLASH
|
||||
#undef CFG_ENV_IS_IN_EEPROM
|
||||
#elif defined CFG_ENV_IS_IN_EEPROM
|
||||
#undef CFG_ENV_IS_IN_NVRAM
|
||||
#undef CFG_ENV_IS_IN_FLASH
|
||||
#endif
|
||||
|
||||
#ifndef CFG_JFFS2_FIRST_SECTOR
|
||||
#define CFG_JFFS2_FIRST_SECTOR 0
|
||||
#endif
|
||||
#ifndef CFG_JFFS2_FIRST_BANK
|
||||
#define CFG_JFFS2_FIRST_BANK 0
|
||||
#endif
|
||||
#ifndef CFG_JFFS2_NUM_BANKS
|
||||
#define CFG_JFFS2_NUM_BANKS 1
|
||||
#endif
|
||||
#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*/
|
||||
#define CFG_MBAR 0xF0000000
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_DEFAULT_MBAR 0x80000000
|
||||
#define CFG_SRAM_BASE (CFG_MBAR + 0x20000)
|
||||
#define CFG_SRAM_SIZE 0x8000
|
||||
|
||||
/* Use SRAM until RAM will be available */
|
||||
#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000)
|
||||
#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
# define CFG_RAMBOOT 1
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/* SDRAM configuration */
|
||||
#define CFG_SDRAM_TOTAL_BANKS 2
|
||||
#define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
|
||||
#define CFG_SDRAM_SPD_SIZE 0x40
|
||||
#define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
|
||||
|
||||
/* SDRAM drive strength register */
|
||||
#define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
|
||||
(DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
|
||||
(DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
|
||||
(DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
|
||||
(DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MPC8220_FEC 1
|
||||
#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
|
||||
#define CONFIG_PHY_ADDR 0x18
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
|
||||
#define CFG_HID0_FINAL HID0_ICE
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -25,7 +25,10 @@
|
|||
#include <stdlib.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#define __ASSEMBLY__ /* Dirty trick to get only #defines */
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__ /* Dirty trick to get only #defines */
|
||||
#endif
|
||||
#define __ASM_STUB_PROCESSOR_H__ /* don't include asm/processor. */
|
||||
#include <config.h>
|
||||
#undef __ASSEMBLY__
|
||||
|
||||
|
|
@ -73,24 +76,24 @@ extern unsigned char environment;
|
|||
int main (int argc, char **argv)
|
||||
{
|
||||
#ifdef ENV_IS_EMBEDDED
|
||||
int crc ;
|
||||
unsigned char *envptr = &environment,
|
||||
*dataptr = envptr + ENV_HEADER_SIZE;
|
||||
unsigned int datasize = ENV_SIZE;
|
||||
int crc;
|
||||
unsigned char *envptr = &environment,
|
||||
*dataptr = envptr + ENV_HEADER_SIZE;
|
||||
unsigned int datasize = ENV_SIZE;
|
||||
|
||||
crc = crc32(0, dataptr, datasize) ;
|
||||
crc = crc32 (0, dataptr, datasize);
|
||||
|
||||
/* Check if verbose mode is activated passing a parameter to the program */
|
||||
if (argc > 1) {
|
||||
printf("CRC32 from offset %08X to %08X of environment = %08X\n",
|
||||
(unsigned int)(dataptr - envptr),
|
||||
(unsigned int)(dataptr - envptr) + datasize,
|
||||
crc);
|
||||
} else {
|
||||
printf("0x%08X\n", crc);
|
||||
}
|
||||
/* Check if verbose mode is activated passing a parameter to the program */
|
||||
if (argc > 1) {
|
||||
printf ("CRC32 from offset %08X to %08X of environment = %08X\n",
|
||||
(unsigned int) (dataptr - envptr),
|
||||
(unsigned int) (dataptr - envptr) + datasize,
|
||||
crc);
|
||||
} else {
|
||||
printf ("0x%08X\n", crc);
|
||||
}
|
||||
#else
|
||||
printf("0\n");
|
||||
printf ("0\n");
|
||||
#endif
|
||||
return EXIT_SUCCESS;
|
||||
return EXIT_SUCCESS;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue