Preliminary support for the iDMR board (ColdFire).
This commit is contained in:
Bartlomiej Sieka
parent
cdb97a6678
commit
daa6e418bc
4
MAKEALL
4
MAKEALL
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@ -299,8 +299,8 @@ LIST_microblaze=" \
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LIST_coldfire=" \
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cobra5272 EB+MCF-EV123 EB+MCF-EV123_internal \
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M5271EVB M5272C3 M5282EVB TASREG \
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r5200 M5271EVB \
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idmr M5271EVB M5272C3 M5282EVB \
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TASREG r5200 M5271EVB \
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"
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#########################################################################
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3
Makefile
3
Makefile
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@ -1569,6 +1569,9 @@ EB+MCF-EV123_internal_config : unconfig
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@echo "TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk
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@$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
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idmr_config : unconfig
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@$(MKCONFIG) $(@:_config=) m68k mcf52x2 idmr
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M5271EVB_config : unconfig
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@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5271evb
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@ -0,0 +1,44 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o flash.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,25 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xff800000
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@ -0,0 +1,356 @@
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/*
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* (C) Copyright 2000-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#define PHYS_FLASH_1 CFG_FLASH_BASE
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#define FLASH_BANK_SIZE 0x800000
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#define EN29LV640 0x227e227e
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
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void flash_print_info (flash_info_t * info)
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{
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int i;
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switch (info->flash_id & FLASH_VENDMASK) {
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case (AMD_MANUFACT & FLASH_VENDMASK):
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printf ("AMD: ");
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break;
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default:
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printf ("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case (EN29LV640 & FLASH_TYPEMASK):
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printf ("EN29LV640 (16Mbit)\n");
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break;
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default:
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printf ("Unknown Chip Type\n");
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goto Done;
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; i++) {
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if ((i % 5) == 0) {
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printf ("\n ");
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}
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printf (" %08lX%s", info->start[i],
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info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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Done:
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return;
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}
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unsigned long flash_init (void)
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{
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int i, j;
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ulong size = 0;
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
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ulong flashbase = 0;
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flash_info[i].flash_id =
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(AMD_MANUFACT & FLASH_VENDMASK) |
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(EN29LV640 & FLASH_TYPEMASK);
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flash_info[i].size = FLASH_BANK_SIZE;
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flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
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memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
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if (i == 0)
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flashbase = PHYS_FLASH_1;
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else
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panic ("configured to many flash banks!\n");
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for (j = 0; j < flash_info[i].sector_count; j++) {
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flash_info[i].start[j] = flashbase + 0x10000 * j;
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}
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size += flash_info[i].size;
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}
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flash_protect (FLAG_PROTECT_SET,
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CFG_FLASH_BASE,
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CFG_FLASH_BASE + 0x30000, &flash_info[0]);
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return size;
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}
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#define CMD_READ_ARRAY 0x00F0
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#define CMD_UNLOCK1 0x00AA
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#define CMD_UNLOCK2 0x0055
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#define CMD_ERASE_SETUP 0x0080
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#define CMD_ERASE_CONFIRM 0x0030
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#define CMD_PROGRAM 0x00A0
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#define CMD_UNLOCK_BYPASS 0x0020
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#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
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#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
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#define BIT_ERASE_DONE 0x0080
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#define BIT_RDY_MASK 0x0080
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#define BIT_PROGRAM_ERROR 0x0020
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#define BIT_TIMEOUT 0x80000000 /* our flag */
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#define READY 1
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#define ERR 2
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#define TMO 4
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int flash_erase (flash_info_t * info, int s_first, int s_last)
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{
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ulong result;
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int iflag, prot, sect;
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int rc = ERR_OK;
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int chip1;
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/* first look for protection bits */
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if (info->flash_id == FLASH_UNKNOWN)
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return ERR_UNKNOWN_FLASH_TYPE;
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if ((s_first < 0) || (s_first > s_last)) {
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return ERR_INVAL;
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}
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if ((info->flash_id & FLASH_VENDMASK) !=
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(AMD_MANUFACT & FLASH_VENDMASK)) {
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return ERR_UNKNOWN_FLASH_VENDOR;
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}
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prot = 0;
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for (sect = s_first; sect <= s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot)
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return ERR_PROTECTED;
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/*
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* Disable interrupts which might cause a timeout
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* here. Remember that our exception vectors are
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* at address 0 in the flash, and we don't want a
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* (ticker) exception to happen while the flash
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* chip is in programming mode.
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*/
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iflag = disable_interrupts ();
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printf ("\n");
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
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printf ("Erasing sector %2d ... ", sect);
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/* arm simple, non interrupt dependent timer */
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set_timer (0);
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if (info->protect[sect] == 0) { /* not protected */
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volatile u16 *addr =
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(volatile u16 *) (info->start[sect]);
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MEM_FLASH_ADDR1 = CMD_UNLOCK1;
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MEM_FLASH_ADDR2 = CMD_UNLOCK2;
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MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
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MEM_FLASH_ADDR1 = CMD_UNLOCK1;
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MEM_FLASH_ADDR2 = CMD_UNLOCK2;
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*addr = CMD_ERASE_CONFIRM;
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/* wait until flash is ready */
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chip1 = 0;
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do {
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result = *addr;
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/* check timeout */
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if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) {
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MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
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chip1 = TMO;
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break;
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}
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if (!chip1
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&& (result & 0xFFFF) & BIT_ERASE_DONE)
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chip1 = READY;
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} while (!chip1);
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MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
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if (chip1 == ERR) {
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rc = ERR_PROG_ERROR;
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goto outahere;
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}
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if (chip1 == TMO) {
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rc = ERR_TIMOUT;
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goto outahere;
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}
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printf ("ok.\n");
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} else { /* it was protected */
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printf ("protected!\n");
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}
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}
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if (ctrlc ())
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printf ("User Interrupt!\n");
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outahere:
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/* allow flash to settle - wait 10 ms */
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printf("Waiting 10 ms...");
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udelay (10000);
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/* for (i = 0; i < 10 * 1000 * 1000; ++i)
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asm(" nop");
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*/
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printf("done\n");
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if (iflag)
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enable_interrupts ();
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return rc;
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}
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static int write_word (flash_info_t * info, ulong dest, ulong data)
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{
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volatile u16 *addr = (volatile u16 *) dest;
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ulong result;
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int rc = ERR_OK;
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int iflag;
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int chip1;
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/*
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* Check if Flash is (sufficiently) erased
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*/
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result = *addr;
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if ((result & data) != data)
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return ERR_NOT_ERASED;
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|
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|
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/*
|
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* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
iflag = disable_interrupts ();
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|
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MEM_FLASH_ADDR1 = CMD_UNLOCK1;
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MEM_FLASH_ADDR2 = CMD_UNLOCK2;
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MEM_FLASH_ADDR1 = CMD_PROGRAM;
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*addr = data;
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/* arm simple, non interrupt dependent timer */
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set_timer (0);
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|
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/* wait until flash is ready */
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chip1 = 0;
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do {
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result = *addr;
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/* check timeout */
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||||
if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) {
|
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chip1 = ERR | TMO;
|
||||
break;
|
||||
}
|
||||
if (!chip1 && ((result & 0x80) == (data & 0x80)))
|
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chip1 = READY;
|
||||
|
||||
} while (!chip1);
|
||||
|
||||
*addr = CMD_READ_ARRAY;
|
||||
|
||||
if (chip1 == ERR || *addr != data)
|
||||
rc = ERR_PROG_ERROR;
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts ();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong wp, data;
|
||||
int rc;
|
||||
|
||||
if (addr & 1) {
|
||||
printf ("unaligned destination not supported\n");
|
||||
return ERR_ALIGN;
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (cnt & 1) {
|
||||
printf ("odd transfer sizes not supported\n");
|
||||
return ERR_ALIGN;
|
||||
}
|
||||
#endif
|
||||
|
||||
wp = addr;
|
||||
|
||||
if (addr & 1) {
|
||||
data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
|
||||
src);
|
||||
if ((rc = write_word (info, wp - 1, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 1;
|
||||
wp += 1;
|
||||
cnt -= 1;
|
||||
}
|
||||
|
||||
while (cnt >= 2) {
|
||||
data = *((volatile u16 *) src);
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 2;
|
||||
wp += 2;
|
||||
cnt -= 2;
|
||||
}
|
||||
|
||||
if (cnt == 1) {
|
||||
data = (*((volatile u8 *) src) << 8) |
|
||||
*((volatile u8 *) (wp + 1));
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 1;
|
||||
wp += 1;
|
||||
cnt -= 1;
|
||||
}
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2006
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/m5271.h>
|
||||
#include <asm/immap_5271.h>
|
||||
|
||||
int checkboard (void) {
|
||||
puts ("Board: iDMR\n");
|
||||
return 0;
|
||||
};
|
||||
|
||||
long int initdram (int board_type) {
|
||||
int i;
|
||||
|
||||
/*
|
||||
* After reset, CS0 is configured to cover entire address space. We
|
||||
* need to configure it to its proper values, so that writes to
|
||||
* CFG_SDRAM_BASE and vicinity during SDRAM controller setup below do
|
||||
* now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
|
||||
*/
|
||||
|
||||
/* Flash chipselect, CS0 */
|
||||
/* ;CSAR0: Flash at 0xFF800000 */
|
||||
mbar_writeShort(0x0080, 0xFF80);
|
||||
|
||||
/* CSCR0: Flash 6 waits, 16bit */
|
||||
mbar_writeShort(0x008A, 0x1980);
|
||||
|
||||
/* CSMR0: Flash 8MB, R/W, valid */
|
||||
mbar_writeLong(0x0084, 0x007F0001);
|
||||
|
||||
|
||||
/*
|
||||
* SDRAM configuration proper
|
||||
*/
|
||||
|
||||
/*
|
||||
* Address/Data Pin Assignment Reg.: enable address lines 23-21; do
|
||||
* not enable data pins D[15:0], as we have 16 bit port to SDRAM
|
||||
*/
|
||||
mbar_writeByte(MCF_GPIO_PAR_AD,
|
||||
MCF_GPIO_AD_ADDR23 |
|
||||
MCF_GPIO_AD_ADDR22 |
|
||||
MCF_GPIO_AD_ADDR21);
|
||||
|
||||
/* No need to configure BS pins - reset values are OK */
|
||||
|
||||
/* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */
|
||||
mbar_writeByte(MCF_GPIO_PAR_CS, 0x00);
|
||||
|
||||
/* SDRAM Control Pin Assignment Reg. */
|
||||
mbar_writeByte(MCF_GPIO_PAR_SDRAM,
|
||||
MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */
|
||||
MCF_GPIO_SDRAM_SDWE |
|
||||
MCF_GPIO_SDRAM_SCAS |
|
||||
MCF_GPIO_SDRAM_SRAS |
|
||||
MCF_GPIO_SDRAM_SCKE |
|
||||
MCF_GPIO_SDRAM_SDCS_01);
|
||||
|
||||
/*
|
||||
* Wait 100us. We run the bus at 50Mhz, one cycle is 20ns. So 5
|
||||
* iterations will do, but we do 10 just to be safe.
|
||||
*/
|
||||
for (i = 0; i < 10; ++i)
|
||||
asm(" nop");
|
||||
|
||||
|
||||
/* 1. Initialize DRAM Control Register: DCR */
|
||||
mbar_writeShort(MCF_SDRAMC_DCR,
|
||||
MCF_SDRAMC_DCR_RTIM(0x10) | /* 65ns */
|
||||
MCF_SDRAMC_DCR_RC(0x60)); /* 1562 cycles */
|
||||
|
||||
|
||||
/*
|
||||
* 2. Initialize DACR0
|
||||
*
|
||||
* CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1)
|
||||
* CBM: cmd at A20, bank select bits 21 and up
|
||||
* PS: 16 bit
|
||||
*/
|
||||
mbar_writeLong(MCF_SDRAMC_DACR0,
|
||||
MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) |
|
||||
MCF_SDRAMC_DACRn_BA(0x00) |
|
||||
MCF_SDRAMC_DACRn_CASL(0x03) |
|
||||
MCF_SDRAMC_DACRn_CBM(0x03) |
|
||||
MCF_SDRAMC_DACRn_PS(0x03));
|
||||
|
||||
/* Initialize DMR0 */
|
||||
mbar_writeLong(MCF_SDRAMC_DMR0,
|
||||
MCF_SDRAMC_DMRn_BAM_16M |
|
||||
MCF_SDRAMC_DMRn_V);
|
||||
|
||||
|
||||
/* 3. Set IP bit in DACR to initiate PALL command */
|
||||
mbar_writeLong(MCF_SDRAMC_DACR0,
|
||||
mbar_readLong(MCF_SDRAMC_DACR0) |
|
||||
MCF_SDRAMC_DACRn_IP);
|
||||
|
||||
/* Write to this block to initiate precharge */
|
||||
*(volatile u16 *)(CFG_SDRAM_BASE) = 0xa5a5;
|
||||
|
||||
/*
|
||||
* Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
|
||||
* wait a wee longer, just to be safe.
|
||||
*/
|
||||
for (i = 0; i < 5; ++i)
|
||||
asm(" nop");
|
||||
|
||||
|
||||
/* 4. Set RE bit in DACR */
|
||||
mbar_writeLong(MCF_SDRAMC_DACR0,
|
||||
mbar_readLong(MCF_SDRAMC_DACR0) |
|
||||
MCF_SDRAMC_DACRn_RE);
|
||||
|
||||
/*
|
||||
* Wait for at least 8 auto refresh cycles to occur, i.e. at least
|
||||
* 781 bus cycles.
|
||||
*/
|
||||
for (i = 0; i < 1000; ++i)
|
||||
asm(" nop");
|
||||
|
||||
/* Finish the configuration by issuing the MRS */
|
||||
mbar_writeLong(MCF_SDRAMC_DACR0,
|
||||
mbar_readLong(MCF_SDRAMC_DACR0) |
|
||||
MCF_SDRAMC_DACRn_MRS);
|
||||
|
||||
/*
|
||||
* Write to the SDRAM Mode Register A0-A11 = 0x400
|
||||
*
|
||||
* Write Burst Mode = Programmed Burst Length
|
||||
* Op Mode = Standard Op
|
||||
* CAS Latency = 3
|
||||
* Burst Type = Sequential
|
||||
* Burst Length = 1
|
||||
*/
|
||||
*(volatile u32 *)(CFG_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
|
||||
|
||||
return CFG_SDRAM_SIZE * 1024 * 1024;
|
||||
};
|
||||
|
||||
|
||||
int testdram (void) {
|
||||
|
||||
/* TODO: XXX XXX XXX */
|
||||
printf ("DRAM test not implemented!\n");
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(m68k)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
GROUP(libgcc.a)
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/mcf52x2/start.o (.text)
|
||||
lib_m68k/traps.o (.text)
|
||||
cpu/mcf52x2/interrupts.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
common/environment.o (.ppcenv)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
|
||||
.reloc :
|
||||
{
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
_sbss = .;
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -61,6 +61,7 @@
|
|||
defined(CONFIG_TRAB) || \
|
||||
defined(CONFIG_PPCHAMELEONEVB) || \
|
||||
defined(CONFIG_M5271EVB) || \
|
||||
defined(CONFIG_IDMR) || \
|
||||
defined(CONFIG_NAND_U_BOOT)) && \
|
||||
defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
|
||||
/* XXX - This only works with GNU C */
|
||||
|
|
|
|||
|
|
@ -140,11 +140,11 @@ _start:
|
|||
move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
|
||||
move.l %d0, 0x40000000
|
||||
|
||||
#if defined(CONFIG_M5282)
|
||||
/* Initialize RAMBAR1: locate SRAM and validate it */
|
||||
move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
|
||||
movec %d0, %RAMBAR1
|
||||
|
||||
#if defined(CONFIG_M5282)
|
||||
#if (TEXT_BASE == CFG_INT_FLASH_BASE)
|
||||
/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,197 @@
|
|||
/*
|
||||
* Configuration settings for the iDMR board
|
||||
*
|
||||
* Based on MC5272C3, r5200 and M5271EVB board configs
|
||||
* (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
|
||||
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _IDMR_H
|
||||
#define _IDMR_H
|
||||
|
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MCF52x2 /* define processor family */
|
||||
#define CONFIG_M5271 /* define processor type */
|
||||
#define CONFIG_IDMR /* define board type */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* disable watchdog */
|
||||
|
||||
/*
|
||||
* Default environment settings
|
||||
*/
|
||||
#define CONFIG_BOOTCOMMAND "run net_nfs"
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
#define CONFIG_BAUDRATE 19200
|
||||
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
|
||||
#define CONFIG_ETHADDR 00:06:3b:01:41:55
|
||||
#define CONFIG_ETHPRIME
|
||||
#define CONFIG_IPADDR 192.168.30.1
|
||||
#define CONFIG_SERVERIP 192.168.1.1
|
||||
#define CONFIG_ROOTPATH
|
||||
#define CONFIG_GATEWAYIP 192.168.1.1
|
||||
#define CONFIG_NETMASK 255.255.0.0
|
||||
#define CONFIG_HOSTNAME idmr
|
||||
#define CONFIG_BOOTFILE /tftpboot/idmr/uImage
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root " \
|
||||
"filesystem over NFS; echo"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):" \
|
||||
"$(netmask):$(hostname):$(netdev):off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip;bootm $(kernel_addr) " \
|
||||
"$(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ethact=FEC ETHERNET\0" \
|
||||
"update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; " \
|
||||
"cp.b 200000 ff800000 $(filesize);" \
|
||||
"prot on ff800000 ff81ffff\0" \
|
||||
"load=tftp 200000 $(u-boot)\0" \
|
||||
"u-boot=/tftpboot/idmr/u-boot.bin\0" \
|
||||
""
|
||||
|
||||
/*
|
||||
* Commands' definition
|
||||
*/
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_MII) & \
|
||||
~(CFG_CMD_LOADS | \
|
||||
CFG_CMD_LOADB))
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Configuration for environment, which occupies third sector in flash.
|
||||
*/
|
||||
#ifndef CONFIG_MONITOR_IS_IN_RAM
|
||||
#define CFG_ENV_ADDR 0xff820000
|
||||
#define CFG_ENV_SECT_SIZE 0x10000
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
#else /* CONFIG_MONITOR_IS_IN_RAM */
|
||||
#define CFG_ENV_OFFSET 0x4000
|
||||
#define CFG_ENV_SECT_SIZE 0x2000
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
#endif /* !CONFIG_MONITOR_IS_IN_RAM */
|
||||
|
||||
#define CFG_PROMPT "=> "
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else /* !(CONFIG_COMMANDS & CFG_CMD_KGDB) */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif /* (CONFIG_COMMANDS & CFG_CMD_KGDB) */
|
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000
|
||||
|
||||
#define CFG_MEMTEST_START 0x400
|
||||
#define CFG_MEMTEST_END 0x380000
|
||||
|
||||
#define CFG_HZ (50000000 / 64)
|
||||
#define CFG_CLK 100000000
|
||||
|
||||
#define CFG_MBAR 0x40000000 /* Register Base Addrs */
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
#define FEC_ENET
|
||||
#define CONFIG_NET_RETRY_COUNT 5
|
||||
#define CFG_ENET_BD_BASE 0x480000
|
||||
#define CFG_DISCOVER_PHY 1
|
||||
#define CONFIG_MII 1
|
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR 0x20000000
|
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
|
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
|
||||
#define CFG_FLASH_BASE 0xff800000
|
||||
|
||||
#ifdef CONFIG_MONITOR_IS_IN_RAM
|
||||
#define CFG_MONITOR_BASE 0x20000
|
||||
#else /* !CONFIG_MONITOR_IS_IN_RAM */
|
||||
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
|
||||
#endif /* CONFIG_MONITOR_IS_IN_RAM */
|
||||
|
||||
#define CFG_MONITOR_LEN 0x20000
|
||||
#define CFG_MALLOC_LEN (256 << 10)
|
||||
#define CFG_BOOTPARAMS_LEN (64*1024)
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization ??
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/* FLASH organization */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
#define CFG_FLASH_ERASE_TOUT 1000
|
||||
|
||||
#define CFG_FLASH_SIZE 0x800000
|
||||
/*
|
||||
* #define CFG_FLASH_USE_BUFFER_WRITE 1
|
||||
*/
|
||||
|
||||
/* Cache Configuration */
|
||||
#define CFG_CACHELINE_SIZE 16
|
||||
|
||||
/* Port configuration */
|
||||
#define CFG_FECI2C 0xF0
|
||||
#endif /* _IDMR_H */
|
||||
|
|
@ -153,7 +153,11 @@ void udelay(unsigned long usec)
|
|||
timerp[MCFTIMER_PMR] = 0;
|
||||
/* set period to 1 us */
|
||||
timerp[MCFTIMER_PCSR] =
|
||||
#ifdef CONFIG_M5271
|
||||
(6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
|
||||
#else /* !CONFIG_M5271 */
|
||||
(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
|
||||
#endif /* CONFIG_M5271 */
|
||||
|
||||
timerp[MCFTIMER_PMR] = tmp;
|
||||
while (timerp[MCFTIMER_PCNTR] > 0);
|
||||
|
|
@ -171,7 +175,11 @@ void timer_init (void)
|
|||
timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
|
||||
timerp[MCFTIMER_PMR] = lastinc = 0;
|
||||
timerp[MCFTIMER_PCSR] =
|
||||
#ifdef CONFIG_M5271
|
||||
(6 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
|
||||
#else /* !CONFIG_M5271 */
|
||||
(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
|
||||
#endif /* CONFIG_M5271 */
|
||||
}
|
||||
|
||||
void set_timer (ulong t)
|
||||
|
|
|
|||
Loading…
Reference in New Issue